Abstract: A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

Abstract: According to some possible implementations, a monitoring device may receive a set of inputs from one or more drivers of a device connected to a bus. The one or more drivers may be capable of driving a bus line of the bus, and the bus may connect multiple devices capable of driving the bus line. The monitoring device may determine a length of time over which the set of inputs maintains a value indicating that the bus is not idle. The monitoring device may compare the length of time and a threshold. The monitoring device may output a signal based on comparing the length of time and the threshold.

Abstract: A sensor control arrangement may comprise a host controller, a remote sensor interface, a power/data bus extending between the host controller and the remote sensor interface, and an electromagnetic sensor configured to receive an AC signal from the host controller via the power/data bus, and send an a sensor signal to the remote sensor interface via the power/data bus.

Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.

Abstract: A system is provided relating to a peripheral component interconnect express bus bar. In use, the bus bar includes a circuit board and at least two electrical interface surface mount connectors attached to the circuit board, each of the at least two electrical interface surface mount connectors configured to be connected to a respective add-in card. Further, at least one power connector is attached to the circuit board and connected to at least one electrical interface surface mount connector of the at least two electrical interface surface mount connectors, and is configured to receive power and distribute the power to the at least two electrical interface surface connectors.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include configuring multiple servers coupled to a network as a software defined storage (SDS) grid. A first given server receives, via the network, an input/output (I/O) request from a host computer, and determines a location of data associated with the I/O request. In some embodiments, each of the servers maintains a local grid data map that store locations for all data managed by the SDS grid. Upon identifying, in its respective local grid data map, that a second given server is configured to process the I/O request, the first given server forwards the I/O request to the second given server for processing, and upon receiving a result of the I/O request from the second given server, the first given server conveys the result of the I/O request to the host computer.

Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.

Abstract: A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Abstract: A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.

Abstract: In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.

Abstract: In general, embodiments of the technology relate to a method and system for performing fast ordered writes in a storage appliance that includes multiple separate storage modules. More specifically, embodiments of the technology enable multicasting of data to multiple storage modules in a storage appliance, where the order in which the write requests are processed is the same across all storage modules in the storage appliance.

Abstract: A peripheral device class identifier is generated for a class of peripheral devices, and is used to identify a setup record that indicates how to install or otherwise set up the class of peripheral devices on a computing device. The peripheral device class identifier is a combination of three components: a vendor identifier, a namespace identifier, and a namespace entry identifier. The vendor identifier is an identifier of the vendor of the class of peripheral devices. The namespace identifier is an identifier of different collections or groups of types of peripheral devices or types of functionality of peripheral devices. The namespace entry identifier is an identifier of a particular type of peripheral device (or particular functionality) of the different collections or groups of types of peripheral devices (or types of functionality of peripheral devices).

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

Abstract: This disclosure describes systems, methods, and apparatus for a combined LED driver and emergency backup battery system. The LED driver can include current regulation circuitry as well as a bus enabling charging and discharging of an energy storage device from and to the bus. A master controller can control charging and discharging of the energy storage device via a controller of an energy storage management system, and also communicate with the current regulation circuitry to control a balance of power between an AC mains, the energy storage device, and driving of an LED light source. Accessories may be coupled to the bus and receive low voltage power from the bus and optionally receive commands from the master controller and provide sensed data back to the controller. A wireless network interface to the master controller can enable system states based on electrical power company indications and instructions.

Abstract: Disclosed are techniques for downloading of filtering rules onto a mobile device. The described technique includes determining, from among at least two lists of filtering rules intended for downloading onto a mobile device, a priority sublist with a high indicator of frequency of actuation of the filtering rules from the list. The priority list is downloaded onto the mobile device. Each of the remaining non-downloaded lists of filtering rules is broken up into parts of a certain size, and a set of groups of filtering rules is formed, in each of whose groups is placed not more than one part of each remaining non-downloaded list of filtering rules. The groups of filtering rules are downloaded onto the mobile device with a certain interval of time until said formed set of groups is fully downloaded.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

Abstract: A communication apparatus includes a first communicator configured to receive signals of a plurality of standards containing a first network signal as a transmitted and received signal for a network, a second communicator configured to receive a second network signal as a transmitted and received signal for the network, a selector configured to select one of the first and second network signals, and a controller configured to control the first and second communicators and the selector. The first communicator includes a first confirmer configured to confirm a reception of the first network signal among the signals of the plurality of standards for the first communicator, and a first operation mode setter configured to set an operation mode to the first communicator.

Abstract: A system and method includes generating, with a configuration controller, a configuration bitstream including configuration bits to dynamically define the configuration of a reconfigurable integrated circuit by setting a state of a subset of configuration state memory units. The configuration controller accesses individual configuration state memory units of the subset according to a scan path through the configuration state memory units traversed according to a delay factor based, at least in part, on clock frequency of a clock signal produced by a configuration clock and configures the individual configuration state memory units with corresponding configuration bits of the configuration bitstream.

Abstract: In one embodiment, a method includes identifying insertion of a plug at a port of power sourcing equipment for delivery of Power over Ethernet, the plug connected to one end of a cable with another plug connected to an opposite end of the cable, checking for resistors at each of the plugs, determining a power rating of the cable based on the resistors located at the plugs, and powering the port to a power level based on the power rating. An apparatus is also disclosed herein.

Abstract: A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports. One or more of the data card connectors may be repurposed as one or more host interface connections or one or more of the host interface connectors may be repurposed as one or more data card connectors.

Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

Abstract: Embodiments of the present invention disclose an access request scheduling method and apparatus. The method includes: receiving a to-be-enqueued access request, and determining a memory that the to-be-enqueued access request requests to access; writing the to-be-enqueued access request to one queue in one access queue group corresponding to the memory; selecting one candidate access queue from each candidate access queue group, as a to-be-scheduled queue; selecting, from the to-be-scheduled queues according to an access timeslot of each memory, alternative queues that can participate in scheduling in a current clock period; selecting, from the alternative queues, a specified queue in scheduling in the current clock period; extracting a to-be-scheduled access request from the specified queue; and granting an access authorization to the to-be-scheduled access request.

Abstract: A method for implementing a configurable on-chip interconnection system. The method comprises: in an interconnection system, master devices set bit widths of bus identifiers of the master devices, wherein the bit widths of the bus identifiers of the master devices are the same (301); and in a memory access process, the mater devices interact, by means of interconnection matrices only, with slave devices according to the bus identifiers (302). Also provided are a system and apparatus for implementing the method, and a storage medium.

Abstract: An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.

Abstract: A connecting device able to allocate master and slave roles between two intelligent devices having On-The-Go functions, depending on the intelligent device connects at a first point in time to one of two connectors, the connecting device also includes a control circuit connected between the two connectors. The control circuit between the connectors maintains and controls the master-slave relationship between the two intelligent devices.

Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics.

Abstract: The techniques described herein automatically and programmatically harmonize data, and map variable names from a dataset to standards of domains for data in the dataset. Each variable may be stored in a table which holds related groups of variables. The variables may be named by defining mappings, each mapping including two mapping rules. A first mapping rule maps a domain of the standard to the table, while a second mapping rule maps a variable within the table to a variable within the domain. When a mapping rule exists that provides an exact match between a variable name and a standard, an auto-mapping feature may be applied that automatically maps the variable name to the standard. If no exact match exists, then an analysis is performed to determine the most likely mapping candidate.

Abstract: A bidirectional bus system that includes a bus master having a first transmitter coupled to a bidirectional bus. The first transmitter transmits a signal in a first voltage range onto the bus. The bus master has a first receiver coupled to the bus. A bus slave having a second transmitter coupled to the bus is included. The second transmitter transmits a signal in a second voltage range onto the bus, where the bus slave having a second receiver is coupled to the bus. The first receiver is configured to interpret the signal in the first voltage range to indicate an idle state while the second receiver interprets the signal in the first voltage range as indicating data. The second receiver interprets the signal in the second voltage range as indicative of an idle state while the first receiver interprets the signal in the second voltage range as indicating data.

Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.

Abstract: An object is disclosed, the object (100) comprising a body comprising an antenna; and an integrated circuit embedded in the body and electrically connected to the antenna for receiving and transmitting wireless signals. The integrated circuit receives wireless signals at first and second different frequencies, waits until a command is received at the first frequency from a first reader device before transmitting a first signal and, upon detection of a signal at a second frequency different to the first frequency from a second reader device (201), transmits a second signal without waiting until a command is received.

Abstract: The present disclosure pertains to a programmable data width converter device, system and method thereof. Programmable data width converter (pDWC) of the present disclosure can include a control Finite State Machine (FSM) that is configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n; and a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. The pDWC can be configured to programmably convert width of m k-bit word input to n k-bit word output, and wherein 1?m?M and 1?n?N.

Abstract: The disclosure extends to methods, systems, and computer program products for digitally imaging with area limited image sensors, such as within a lumen of an endoscope. The system includes an image sensor comprising a pixel array for sensing electromagnetic radiation. The pixel array comprises a plurality of pixel groups comprising only active pixels, a plurality of pixel groups comprising only optical black pixels, and a plurality of line readouts, wherein each line readout is configured to read out a single group of the plurality of pixel groups in the pixel array. The imaging system samples one or more of the plurality of pixel groups comprising only optical black pixels a plurality of times to reduce a size of the image sensor by reducing a number of optical black columns.

Abstract: A device is connected to a connector of a computing system. In response, the computing system determines whether the device is a management device. In response to determining that the device is the management device, the computing system couples the connector to a management port of a service processor of the computing system. In response to determining that the device is not the management device, the computing system couples the connector to a system port of a primary processor of the computing system.

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Abstract: An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.

Abstract: System, methods and apparatus are described that facilitate a device to encode/decode data in a data communications interface coupled to a plurality of wires. The device determines a value of a sequence of data bits allocated to a frame, converts the value into a sequence of symbols associated with the frame, and transmits the sequence of symbols to a receiver. The device performs the converting by calculating base-N coefficients of a base-N number polynomial for the frame based on the value, where N is greater than 2, calculating base-2 coefficients of a base-2 number polynomial for each symbol according to a respective base-N coefficient corresponding to each symbol, determining changes of states of the plurality of wires for each symbol according to the base-2 coefficients respectively calculated for each symbol, and generating the sequence of symbols based on the changes of states of the plurality of wires for each symbol.

Abstract: A product, according to one embodiment, includes a support portion, the support portion being elongated in a first direction; and an insertion portion extending from the support portion in a second direction orthogonal to the first direction, the insertion portion having dimensions allowing insertion of the insertion portion in a card connector of a circuit board. At least an exterior of the insertion portion is electrically insulating. The support portion is wider than the insertion portion in a third direction orthogonal to each of the first and second directions.

Abstract: A method may include creating a priority order among two or more transport media based on an availability of each transport medium when a request to establish an outbound communication session is received. The method may further include receiving the request to establish an outbound communication session with a contact and selecting a transport medium of the two or more transport media based on the priority order and one or more user identifications associated with the contact. The method may also include selecting a software controller in response to the selection of the transport medium based on the software controller being associated with the selected transport medium and sending the request to establish the outbound communication session to an electronic device by the selected software controller through the selected transport medium. The method may also include establishing the outbound communication session with the electronic device through the selected transport medium.

Abstract: The memory control unit includes a descriptor fetch block suitable for fetching a descriptor from a volatile memory; an instruction fetch block suitable for fetching an instruction set from an instruction memory through an address information, wherein the instruction fetch block obtains the address information from the instruction memory through an index information included in the fetched descriptor; and a memory instruction generation block suitable for generating a memory instruction by combining a descriptor parameter value included in the fetched descriptor to the fetched instruction set.

Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.

Abstract: A media item is presented via a media player, the media player configured to receive the media item, the media item being associated with a format and including an audio component. Responsive to a change in a display mode associated with the media player, a second media player is identified that is configured to receive a corresponding media item, the corresponding media item being associated with a second format and including a second audio component that matches the audio component. A particular location is determined in the media item to cease presentation of the media item via the media player and a corresponding location in the corresponding media item to begin presentation of the corresponding media item using the second media player. Responsive to reaching the particular location, concurrently, presentation of the media item is ceased and presentation of the corresponding media item at the corresponding location is begun.

Abstract: Systems, methods, circuits and computer-readable mediums for managing single-wire communications. In one aspect, a method includes starting a transmission cycle by transmitting a clock pulse to a single-wire bus, sampling a data bit transmitted from a single-wire device through the single-wire bus within the transmission cycle after the transmission of the clock pulse, and determining whether a sampling period of the sampling is smaller than a sampling threshold for the data bit. In response to determining that the sampling period is not smaller than the sampling threshold, the method further includes determining that the transmitted data bit is an invalid data bit, and in response: transmitting a high logic voltage level pulse to the single-wire bus for timeout and restarting the transmission cycle for retransmission of the data bit.

Abstract: A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

Abstract: A system-on-Chip (SoC) and a load imbalance detecting method of the same are provided. The SoC includes at least one master, a plurality of slaves, an interconnect, a measurement block, a central controller. The interconnect is configured to connect the at least one master and each of the plurality of slaves. The measurement block is configured to connect each of the plurality of slaves and the interconnect using a channel and to measure a load of each of the plurality of slaves. The central controller is configured to measure a load imbalance among the plurality of channels using the measured load information.

Abstract: Methods and systems for implementing a pre-processing and processing pipeline for a queue client are disclosed. A queue client receives, from a queue service, data indicative of an estimated time to process a first message in a queue. The queue client initiates processing of the first message. The queue client receives, from the queue service, data indicative of an estimated time to pre-process a second message in the queue. The queue client initiates pre-processing of the second message during the processing of the first message. The pre-processing of the second message is scheduled based on the estimated time to process the first message and the estimated time to pre-process the second message.

Abstract: An electronic device has a management data input/output (MDIO) bus, a control unit, and an MDIO master. The control circuit receives a host command from a host device, and outputs a plurality of MDIO commands in response to the host command. The MDIO master receives the MDIO commands from the control circuit, and transmits the MDIO commands to the MDIO bus.