Abstract: A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.

Abstract: A device includes protocol logic to determine a packet type for a packet and generate and send the corresponding packet. The packet includes a packet header with a header base, the header base including a type field and a header content field. The type field indicates the packet type and the header content field indicates which of a plurality of header content blocks is to be included in the packet header with the header base. Information in fields of the header base indicate a total length of the packet.

Abstract: An Ethernet bridge architecture enables timing replication. The Ethernet bridge receives data packets from a sensor (such as a video sensor) and immediately tags each data packet with a transmitter timecode. The tagged data packets are then forwarded to the appropriate receiver over the digital data network or link that may exhibit packet delivery time variations and reordering. The receiver identifies data packets including the local timecode and delays processing (display) of the data packet until a timecode local to the receiving node matches the transmitter timecode plus some delay. The receiver also restores the original order of the packets by observing packet sequence number and placing them at appropriate location in memory buffer. By delaying processing, the Ethernet bridge compensates for any variance in network latency. The delay should be greater than a worst-case delay as defined by the network architecture.

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

Abstract: Disclosed are devices and methods, among which is a pattern-recognition processor coupled to a microcontroller. The pattern-recognition processor may act as a peripheral device to the microcontroller and provide supplemental pattern recognition functionality to the existing functionality of the microcontroller.

Abstract: Methods, systems, and computer program products for high-performance cluster computing. Multiple components are operatively interconnected to carry out operations for high-performance RDMA I/O transfers over an RDMA NIC. A virtual machine of a virtualization environment initiates a first I/O call to an HCI storage pool controller using RDMA. Responsive to the first I/O call, a second I/O call is initiated from the HCI storage pool controller to a storage device of an HCI storage pool. The first I/O call to the HCI storage pool controller is implemented through a first virtual function of an RDMA NIC that is exposed in the user space of the virtualization environment. Prior to the first RDMA I/O call, a contiguous unit of memory to use in an RDMA I/O transfer is registered with the RDMA NIC. The contiguous unit of memory comprises memory that is registered using non-RDMA paths such as TCP or iSCSI.

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

Abstract: The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.

Abstract: The present invention relates to methods for enabling use of a pluggable module in a host system, regardless of the type of pluggable module used in view of the module ports of the host system, which is realized using an adaptation device. The disclosure also relates to corresponding devices; adaptation devices and host systems. The methods comprise inserting a pluggable module in a module port of a host system, obtaining information indicating an electrical interface of pluggable module and setting a mode of operation of the adaptation device for re-routing and adapting signals to/from the pluggable module towards one or more controlling entities of the host system based on the electrical interface of the pluggable module.

Abstract: A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.

Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Abstract: A non-transitory computer-readable storage medium may be executable by a processor to receive a designation of a message bus producer, a set of business logic to be stored in a set of containers, a designation of a message bus consumer, and a designation of a set of message-handling functions. The non-transitory computer-readable storage medium may generate a serverless application stack, based upon the message bus producer, the set of business logic, the message bus consumer, and the set of message-handling functions. The non-transitory computer-readable storage medium may cause the serverless application stack to receive a message stream from the message bus producer as streaming data, process the message stream according to at least one function, stored in the set of containers, perform at least one message-handling function of the set of message-handling functions on the message stream, and transport the set of messages to the message bus consumer.

Abstract: A power supplying apparatus stores power flow direction information related to a power role of the power supplying apparatus relative to an external apparatus in a storage, and performs control, in a case where the external apparatus has been connected to a connecter of the power supplying apparatus, to match a power role of the power supplying apparatus and a power role corresponding to the power flow direction information stored in the storage based on the power flow direction information stored in the storage unit.

Abstract: An example operation includes one or more of sending data from a component on a transport to at least one other component on the transport in at least one location on a bus, comparing the data at the at least one other component to a threshold, and sending a notification, by the at least one other component, to a processor when the data is outside the threshold.

Abstract: An information processing device is connected via a communication network to a different information processing device. In the information processing device, a periodic message is received as a learning periodic message from the different information processing device. A reception interval is calculated between (i) a one message of the learning periodic message and (ii) a different message that is received immediately before the one message. A reference value of the reception interval of the periodic message is judged based on the calculated reception interval. The reference value is used as a judgment reference to judge whether or not a judgment target periodic message is normal. The judgment target periodic message is the periodic message transmitted by the different information processing device after the reference value is determined.

Abstract: Computer modules that can have a high-capacity, can simplify the design of a computer system housing the modules, can utilize system resources in a highly configurable manner, can provide a variety of functionality, and can be readily inserted into, and removed from, a computer system.

Abstract: An interface module for a communication control device of a subscriber station. The interface module has at least one configuration register for configuring the bit time of a first communication phase of a frame and/or the bit time of a second communication phase of the frame by means of which frame messages are exchanged between subscriber stations of the bus system, and a modulator for modulating a transmission signal to form a modulated transmission signal which has the bit time of the second communication phase, which bit time is configured in the at least one configuration register and differs from the bit time of the first communication phase. The interface module is configured to output the transmission signal input into the modulator to a transmitting/receiving device of the subscriber station.

Abstract: The present disclosure provides a method for detecting controller area network (CAN) bus intrusion of a vehicle-mounted network based on a Gaussian mixture model-hidden Markov model (GMM-HMM), including the following steps: obtaining a normal packet of a CAN bus of a vehicle-mounted network, and counting cycles of all packets of each CAN ID based on a time sequence, that is, a time difference between two frames of packets of a same CAN ID, to form a cycle sequence as an input of an algorithm; dividing the cycle sequence of each CAN ID into a fixed length based on the algorithm, and then training a GMM-HMM for each CAN ID to obtain a likelihood probability of a normal cycle sequence; and further counting a cycle sequence of each CAN ID for a tested packet sequence, calculating, after the cycle sequence is input a model, a likelihood probability of generating the sequence, and determining whether the packet sequence is abnormal by comparing the likelihood probability with a threshold of the likelihood probabili

Abstract: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device to serially transmit a transmission signal, generated by the communication control device, onto a bus, and serially receive signals from the bus. The communication control device generates the transmission signal according to a frame and inserts into the frame two check sums that include different bits of the frame in the computation. The communication control device inserts dynamic stuff bits into the frame in such a way that an inverse stuff bit is inserted into the bit stream of the frame after 5 identical bits in succession. The communication control device computes the two check sums so that a maximum of one of the two check sums includes the dynamic stuff bits in the computation.

Abstract: A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.

Abstract: Examples of synchronization of a gyroscope in a virtual-reality (VR) environment are described. In some examples, gyroscopic feedback for VR application content may be predicted. In some examples, a time shift corresponding to a physical system lag of a gyroscope may be added to synchronize the gyroscopic feedback with the VR application content. In some examples, the gyroscopic feedback may be applied based on the time shift.

Abstract: An unauthorized frame detection device that can keep an unauthorized ECU from spoofing as a legitimate server or client while suppressing an overhead during communication is provided. The unauthorized frame detection device includes a plurality of communication ports corresponding to the respective of networks, a communication controller, and an unauthorized frame detector. The plurality of communication ports are each connected to a corresponding predetermined network among the plurality of networks and each transmit or receive a frame via the predetermined network. The unauthorized frame detector determines whether an identifier of a service, a type of the service, and port information that are each included in the frame match a permission rule set in advance and outputs a result of the determination.

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

Abstract: The present disclosure relates to a consumable chip system and a consumable container. The consumable chip system includes a consumable chip and an antenna board. The consumable chip includes a first die and a first substrate. The first die is encapsulated on the first substrate, and the first die is provided with an interface module. The first substrate is provided with a signal conversion module, and the antenna board is provided with a wireless transceiver module. The wireless transceiver module is configured to receive connection information and an instruction for storing and reading. The signal conversion module is connected to the interface module and the wireless transceiver module, respectively. The consumable chip system is configured to receive connection information by the wireless transceiver module, and establish a wireless connection between the consumable chip and a device for storing and reading on the basis of the connection information.

Abstract: A machine power system of a machine may use energy provided by one or more batteries. The machine power system may also use battery data associated with the batteries to monitor the batteries, configure electrical components to operate in association with the batteries, to provide battery information via a user interface, and/or for other operations. The machine power system may be configured to use a particular battery data format. A battery data translator receives native battery data provided by a battery, uses a translation map associated with the battery to convert the native battery data into translated battery data formatted based on the particular battery data format used by the machine power system, and provides the translated battery data to the machine power system.

Abstract: A transceiver device for a user station of a serial bus system, a communication control device, and a method. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus of the bus system, a reception module for receiving the signal from the bus, the reception module being designed to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place as a result of the operating mode changeover signal.

Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Abstract: Various embodiments to enable Spectrum Access System (SAS) interference mitigation options are disclosed herein. In one embodiment, an apparatus is provided. The apparatus includes a memory to store a data sequence, and one or more processing devices coupled to the memory. The processing devices to generate an interference metric associated with a first group and a second group of infrastructure nodes of a Long-Term Evolution (LTE) network infrastructure based on measurement information. The measurement information comprises measurements related to the transmission of data sequences associated with the first group and the second group. Thereupon, configuration settings are determined for infrastructure nodes of the first group and second group based on the generated interference metric. Each configuration setting represents a frequency band and transmission power level for a corresponding infrastructure node to access data in the LTE network infrastructure.

Abstract: An I2C apparatus (100) comprising: a master device (102) and two slave devices connected through an I2C bus, whereby the two slave devices are programmed with the same default device address. A first slave device (108) is connected to the bus in a conventional configuration whereas a second slave device (110) is connected to the bus in a cross connected configuration such that a clock pin of the second slave is connected to the serial data line and the data pin of the second slave is connected to the serial clock line. In response to a detection that the data pin of the second slave is connected to the serial clock line, the second slave swaps the lines going from the clock and data pins to processing logic of the second slave; and modifies its default device address to ensure that each slave device has a unique device address.

Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

Abstract: A message-level policy implemented with for a message routing system may be used to mediate between a variety of message sources and message targets that receive and use messages. The message-level policy may allow fine grained message-by-message policy assessment that a message routing system policy may be able to provide. The message-level policy may furthermore interact with the message routing system policy to provide mechanisms to avoid accidental leakage of protected messages or spill-over to protected regions.

Abstract: An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

Abstract: A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.

Abstract: A communication system intended for use in a motor vehicle includes a plurality of devices (26, 28), a transmission channel (32) that connects the plurality of devices (26, 28) to one another, and a signal source (30) coupled to the transmission channel (32). Each of the devices (26, 28) includes a control unit (36) configured for evaluating signals of the transmission channel (32), and at least two coupling units (38, 40) configured for connecting and disconnecting the particular device (26, 28) to/from the transmission channel (32). The control units (36) of the devices (26, 28) are configured for causing the coupling units (38, 40), at a certain point in time, in each case to connect no more than one of the devices (26, 28) to the transmission channel (32), and to disconnect the other of the devices (26, 28) from the transmission channel (32).

Abstract: An electronic control unit for vehicle capable of receiving a program by communication expands the received program in a volatile memory and executes the expanded program. As an example of this program, there is a program for changing a communication environment for communicating with another unit.

Abstract: An electric system for transmitting serial communication messages with different priorities over a communication link. The data to be transmitted is arranged in serial communication messages comprising a start of packet (SOP) symbol and data symbols. The ongoing transmission of a first message is interrupted if a SOP symbol of a second message is sent before the first message has been completed. Transmission of the first message is continued only after the second message has been sent.

Abstract: In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.

Abstract: Provided are an in-vehicle communication apparatus, a communication program, and a message transmission method. The in-vehicle communication apparatus according is connected to another apparatus via a plurality of communication lines, and includes a plurality of communication units that are provided respectively for the communication lines, and transmit/receive a message via the communication lines, a classification processing unit that performs processing for classifying messages that are to be transmitted to the other apparatus, into a plurality of groups in accordance with priorities of the messages and a message transmission processing unit that distributes messages classified into each of the plurality of groups, to one or more communication units allocated to the group, and the number of communication units allocated to a group into which a higher-priority message is classified is larger than the number of communication units allocated to a group into which a lower-priority message is classified.

Abstract: An apparatus and method for controlling an interface between a plurality of processors in an electronic device are disclosed. The electronic device may include: a first integrated circuit; a second integrated circuit; and a Peripheral Component Interconnect Express (PCIe) interface interconnecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit may be configured to identify the required latency level associated with a service provided by the electronic device, and restrict the use of at least one power mode among a plurality of power modes supported by the PCIe interface, based on the required latency level associated with the service. Additional embodiments are possible.

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

Abstract: A device, having a safe state, is coupleable to a communication bus. The device includes a first logic unit; a second logic unit; a monitoring circuit; a transmission unit; and a first test line. The device is adapted such that the first logic unit communicates with a bus via the transmission unit in a communication phase and the monitoring circuit emits a monitoring signal to the transmission unit upon a fault so that the transmission unit blocks the communication. The first and/or the second logic unit is coupled to the monitoring circuit via the first test line so as to emit a first test signal to the monitoring circuit.

Abstract: Techniques are provided for generating groups of filtering rules. A priority list of filtering rules having a highest indicator of frequency of utilization among the filtering rules from the plurality of lists is determined from a plurality of lists of filtering rules. The priority list of filtering rules is transmitted to a mobile device. Each of remaining lists of filtering rules that have not been transmitted to the mobile device is divided into a plurality of parts. A plurality of groups of filtering rules is generated based on frequency of utilization within each of the remaining lists of filtering rules. Each generated group contains at most one part of each remaining list of filtering rules.

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for routing events of an event stream in a stream processing system. One of the methods includes receiving, by a router, an event stream of events; identifying, for each event, by the router, a respective partition of context data that includes context data related to the event and providing the event to a respective local modeler that stores the partition of context data identified for the event in operational memory of the local modeler; processing, by each local modeler, events received from the router and aggregating information associated with each event to generate aggregated information; providing, by one or more of the local modelers, to a central modeler, the respective aggregated information; and determining, by the central modeler, a plurality of parameters of a machine learning model using the received aggregated information.

Abstract: A method and device are for recognizing an apparatuses and computer readable storage medium and program are provided. In an embodiment, the method includes reading a combined sequence table including candidate device information, candidate communication parameters and historical occurrence numbers of combinations of the candidate device information and the candidate communication parameters for each candidate device information; determining priority levels of the combinations according to the historical occurrence numbers; and determining a current combination according to the priority levels, sending a message to the apparatus to be recognized by using a candidate communication parameter in the current combination, and determining whether the current combination is the correct combination capable of establishing a communication with the apparatus to be recognized according to a feedback from the apparatus to be recognized.