Protocol Patents (Class 710/105)
  • Patent number: 11570250
    Abstract: A communication system intended for use in a motor vehicle includes a plurality of devices (26, 28), a transmission channel (32) that connects the plurality of devices (26, 28) to one another, and a signal source (30) coupled to the transmission channel (32). Each of the devices (26, 28) includes a control unit (36) configured for evaluating signals of the transmission channel (32), and at least two coupling units (38, 40) configured for connecting and disconnecting the particular device (26, 28) to/from the transmission channel (32). The control units (36) of the devices (26, 28) are configured for causing the coupling units (38, 40), at a certain point in time, in each case to connect no more than one of the devices (26, 28) to the transmission channel (32), and to disconnect the other of the devices (26, 28) from the transmission channel (32).
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: January 31, 2023
    Assignee: ZF ACTIVE SAFETY GMBH
    Inventor: Stefan Grieser-Schmitz
  • Patent number: 11556104
    Abstract: An electronic control unit for vehicle capable of receiving a program by communication expands the received program in a volatile memory and executes the expanded program. As an example of this program, there is a program for changing a communication environment for communicating with another unit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 17, 2023
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Yusuke Abe, Koji Yuasa, Toshihisa Arai
  • Patent number: 11552820
    Abstract: An electric system for transmitting serial communication messages with different priorities over a communication link. The data to be transmitted is arranged in serial communication messages comprising a start of packet (SOP) symbol and data symbols. The ongoing transmission of a first message is interrupted if a SOP symbol of a second message is sent before the first message has been completed. Transmission of the first message is continued only after the second message has been sent.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 10, 2023
    Assignee: Vacon Oy
    Inventor: Petri Ylirinne
  • Patent number: 11429284
    Abstract: In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shirish D. Bahirat, Jonathan M. Haswell, William Akin
  • Patent number: 11405322
    Abstract: Provided are an in-vehicle communication apparatus, a communication program, and a message transmission method. The in-vehicle communication apparatus according is connected to another apparatus via a plurality of communication lines, and includes a plurality of communication units that are provided respectively for the communication lines, and transmit/receive a message via the communication lines, a classification processing unit that performs processing for classifying messages that are to be transmitted to the other apparatus, into a plurality of groups in accordance with priorities of the messages and a message transmission processing unit that distributes messages classified into each of the plurality of groups, to one or more communication units allocated to the group, and the number of communication units allocated to a group into which a higher-priority message is classified is larger than the number of communication units allocated to a group into which a lower-priority message is classified.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 2, 2022
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Tsuyoshi Kontani, Katsuya Ikuta, Yuki Sano
  • Patent number: 11392474
    Abstract: An apparatus and method for controlling an interface between a plurality of processors in an electronic device are disclosed. The electronic device may include: a first integrated circuit; a second integrated circuit; and a Peripheral Component Interconnect Express (PCIe) interface interconnecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit may be configured to identify the required latency level associated with a service provided by the electronic device, and restrict the use of at least one power mode among a plurality of power modes supported by the PCIe interface, based on the required latency level associated with the service. Additional embodiments are possible.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suha Yoon, Mooyoung Kim, Minjung Kim, Hyunkeun Song
  • Patent number: 11386034
    Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Xilinx, Inc.
    Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna
  • Patent number: 11372796
    Abstract: A device, having a safe state, is coupleable to a communication bus. The device includes a first logic unit; a second logic unit; a monitoring circuit; a transmission unit; and a first test line. The device is adapted such that the first logic unit communicates with a bus via the transmission unit in a communication phase and the monitoring circuit emits a monitoring signal to the transmission unit upon a fault so that the transmission unit blocks the communication. The first and/or the second logic unit is coupled to the monitoring circuit via the first test line so as to emit a first test signal to the monitoring circuit.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: June 28, 2022
    Assignee: Eaton Intelligent Power Limited
    Inventors: Horea-Stefan Culca, Olaf Boecker
  • Patent number: 11368871
    Abstract: Techniques are provided for generating groups of filtering rules. A priority list of filtering rules having a highest indicator of frequency of utilization among the filtering rules from the plurality of lists is determined from a plurality of lists of filtering rules. The priority list of filtering rules is transmitted to a mobile device. Each of remaining lists of filtering rules that have not been transmitted to the mobile device is divided into a plurality of parts. A plurality of groups of filtering rules is generated based on frequency of utilization within each of the remaining lists of filtering rules. Each generated group contains at most one part of each remaining list of filtering rules.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: June 21, 2022
    Assignee: AO Kaspersky Lab
    Inventors: Alexey P. Komissarov, Victor V. Yablokov, Alexey M. Chikov
  • Patent number: 11347662
    Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Rupin H. Vakharwala, Rajesh M. Sankaran, Stephen R. Van Doren
  • Patent number: 11343156
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for routing events of an event stream in a stream processing system. One of the methods includes receiving, by a router, an event stream of events; identifying, for each event, by the router, a respective partition of context data that includes context data related to the event and providing the event to a respective local modeler that stores the partition of context data identified for the event in operational memory of the local modeler; processing, by each local modeler, events received from the router and aggregating information associated with each event to generate aggregated information; providing, by one or more of the local modelers, to a central modeler, the respective aggregated information; and determining, by the central modeler, a plurality of parameters of a machine learning model using the received aggregated information.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: May 24, 2022
    Assignee: Pivotal Software, Inc.
    Inventors: Michael Brand, Lyndon John Adams, David Russell Brown, Kee Siong Ng
  • Patent number: 11334366
    Abstract: A method and device are for recognizing an apparatuses and computer readable storage medium and program are provided. In an embodiment, the method includes reading a combined sequence table including candidate device information, candidate communication parameters and historical occurrence numbers of combinations of the candidate device information and the candidate communication parameters for each candidate device information; determining priority levels of the combinations according to the historical occurrence numbers; and determining a current combination according to the priority levels, sending a message to the apparatus to be recognized by using a candidate communication parameter in the current combination, and determining whether the current combination is the correct combination capable of establishing a communication with the apparatus to be recognized according to a feedback from the apparatus to be recognized.
    Type: Grant
    Filed: September 30, 2018
    Date of Patent: May 17, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventor: Junhu He
  • Patent number: 11308019
    Abstract: A method for monitoring automatic mechanical devices selected from at least one of automatic doors and automatic dock equipment located at a commercial site. The method may include installing, at the commercial site, a plurality of internet-of-things (IoT) monitoring devices. Each of the IoT monitoring devices may include a plurality of connectors corresponding to respective data communication standards, and a wireless transceiver configured to transmit operational information. Electronic communication between each automatic mechanical device and one of the IoT monitoring devices may be established via one of the connectors. A device profile may be assigned for each of the automatic mechanical devices. Each device profiles defines a respective connector and combination of manufacturer and device model.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 19, 2022
    Assignee: D. H. Pace Company, Inc.
    Inventors: Mike Maloney, Amir Kashani, William A. Snead, William James McGrath, Eric Poulsen
  • Patent number: 11277427
    Abstract: A system and method for providing security to a network may include maintaining, by a processor, a model of an expected behavior of data communications over the in-vehicle communication network; receiving, by the processor, a message sent over the network; determining, by the processor, based on the model and based on a timing attribute of the message, whether or not the message complies with the model; and if the message does not comply with the model then performing, by the processor, at least one action related to the message.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 15, 2022
    Assignee: Argus Cyber Security Ltd.
    Inventors: Ofer Ben-Noon, Yaron Galula, Ofer Kapota, Alexei Kovelman
  • Patent number: 11276135
    Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 15, 2022
    Assignee: ATI Technologies ULC
    Inventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
  • Patent number: 11237905
    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: February 1, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Daniel Brad Wu
  • Patent number: 11216049
    Abstract: A bus system is provided. The bus system includes a master device and a plurality of slave devices electrically connected to the master device. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When the alert handshake control line is at a first voltage level and a first slave device want to communicate with the master device, the first slave device controls the alert handshake control line to a second voltage level via the alert handshake pin, such that the slave devices enter a synchronization stage. Among phases of each assignment period, in a first phase corresponding to the first slave device, the first slave device controls the alert handshake control line to the second voltage level via the alert handshake pin.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: January 4, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Huang, Chun-Wei Chiu, Hao-Yang Chang
  • Patent number: 11194945
    Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: December 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: I-Hsiu Lo, Yung-Jen Chen, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11184194
    Abstract: A method for the distributed processing of process data in a local bus, wherein the local bus has a local bus master and at least two data bus participants, and the method comprises: sending a data packet with process data from the local bus master via the local bus; receiving the data packet at a first data bus participant; pre-processing at least one item of process data using the first data bus participant; sending the data packet with the at least one item of pre-processed process data via the local bus to the second data bus participant using the first data bus participant; receiving the data packet with the at least one item of pre processed process data at the second data bus participant; and further processing the at least one item of pre-processed process data using the second data bus participant.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 23, 2021
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventor: Daniel Jerolm
  • Patent number: 11177687
    Abstract: This disclosure describes systems, methods, and apparatus for a combined LED driver and emergency backup battery system. The LED driver can include current regulation circuitry as well as a bus enabling charging and discharging of an energy storage device from and to the bus. A master controller can control charging and discharging of the energy storage device via a controller of an energy storage management system, and also communicate with the current regulation circuitry to control a balance of power between an AC mains, the energy storage device, and driving of an LED light source. Accessories may be coupled to the bus and receive low voltage power from the bus and optionally receive commands from the master controller and provide sensed data back to the controller. A wireless network interface to the master controller can enable system states based on electrical power company indications and instructions.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: November 16, 2021
    Assignee: LEDVANCE LLC
    Inventors: Anthony Catalano, Steven S. Davis, Charles Teplin, Anthony N. McDougle
  • Patent number: 11138102
    Abstract: A method and apparatus to reduce read latency and improve read quality of service (Read QoS) for non-volatile memory, such as NAND array in a NAND device. For read commands that collide with an in-progress program array operation targeting the same program locations in a NAND array, the in-progress program is suspended and the controller allows the read command to read from the internal NAND buffer instead of waiting for the in-progress program to complete. For read commands queued during an in-progress program that is processing pre-reads in preparation for a program array operation, pre-read bypass allows the reads to be serviced between the pre-reads and before the program's array operation starts. In this manner, read commands can be serviced without suspending the in-progress program. Allowing internal NAND buffer reads and enabling pre-read bypass reduces read latency and improves Read QoS.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Sagar S. Sidhpura, Yogesh B. Wakchaure, Aliasgar S. Madraswala, Fei Xue
  • Patent number: 11132215
    Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Maksymilian Kunt, Piotr Wysocki, Slawomir Ptak, Kapil Karkra
  • Patent number: 11126375
    Abstract: A system controller of a memory system can present multiple physical functions (PFs) to a host computing system. The system controller can store commands from the host in separate queues and uses an arbiter circuit to issue commands. The arbiter can determine a difference value between a quota of commands and a count of commands issued from a respective queue. The quota is derived from a share specified by the host for the respective PF. The arbiter circuit determines a subset of queues by excluding queues that are empty and queues having a negative difference value. The arbiter circuit can randomly choose a selected queue from the subset and issue a command from the selected queue.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jiangli Zhu, Ying Yu Kai
  • Patent number: 11096298
    Abstract: A power distribution bus bar is provided for distributing power to surface mount connectors. In use, the power distribution bus bar includes a circuit board and at least two add-in card connectors each mounted to a first surface of the circuit board. Additionally, at least one power supply connector distributing a power supply to the add-in card connectors is provided. The at least one power supply connector may be mounted to a second surface of the circuit board and connected to the at least two add-in card connectors.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: August 17, 2021
    Assignee: KRAMBU INC.
    Inventor: Travis Jank
  • Patent number: 11088815
    Abstract: Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes a plurality of slave radio frequency (RF) devices, a master RF device configured to set a configuration parameter in a register to be applied by an RF slave device of the plurality of RF slave devices, and a clock line coupled between the master RF device and the plurality of slave RF devices. The slave RF device may be configured to: count a number of cycles of a clock signal on the clock line; and apply the configuration parameter for the slave RF device based on the count of the number of cycles, wherein the master RF device is further configured to disable an interrupt reporting function of the plurality of slave RF device during a time period between setting the configuration parameter in the register and the configuration parameter being applied.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 10, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt, Umesh Srikantiah, Karthik Manivannan
  • Patent number: 11010248
    Abstract: Provided are a method, system, and computer program product in which a storage controller receives a first write command with a first token over a first interface from a host computational device. In response to a failure of the first write command in the storage controller, the storage controller retains selected resources for reuse for a retry of the first write command, wherein the retry of the first write command is expected from the host computational device over a second interface that is a slower communication link than the first interface. In response to receiving, by the storage controller, a second write command with a second token over the second interface, wherein the second token is identical to the first token, the storage controller determines that the second write command is a retry of the first write command and reuses the retained selected resources for executing the second write command.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Beth A. Peterson, Kevin J. Ash, Lokesh M. Gupta, Chung M. Fung
  • Patent number: 11010317
    Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node and a second computer node. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; and (B) transmitting, by the first BMC and to the second BMC via electrical connection between the first and second BMCs, a reset signal that corresponds to the reset command, so as to trigger reset of the second BMC.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 18, 2021
    Assignee: Mitas Computing Technology Corporation
    Inventor: Ming-Shou Shen
  • Patent number: 10990545
    Abstract: A multiplexor for an I3C) network includes a switch, a routing map, and an interrupt detector. The switch selectably couples I3C slave interfaces to I3C master interfaces. The routing map includes map entries associating each I3C slave interface with an I3C master interfaces based upon an I3C address of the I3C slave interface, such that, for each map entry, an IBI received from the associated I3C slave interface is mapped to the associated I3C master interface. The interrupt detector detects an IBI from an I3C slave interface, determines that a map entry associated with the I3C slave interface maps the I3C slave interface with a particular I3C master interface based upon the IBI, and directs the switch to couple the I3C slave interface to the I3C master interface based upon the map entry.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jordan Chin, Nihit S. Bhavsar
  • Patent number: 10915493
    Abstract: Embodiments are provided herein for component composition of a disaggregated computing system. A plurality of general purpose links connecting a computing element to other hardware elements are provided within the disaggregated computing system. Each of the plurality of general purpose links comprise a point-to-point connection to at least one of the other hardware elements such that the plurality of general purpose links conform to a configuration used by the other hardware elements regardless of a type of data being transferred through the plurality of general purpose links.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Min Li, John A. Bivens, Ruchi Mahindru, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10893392
    Abstract: Methods and apparatus for providing enhanced access options for wireless access points (e.g., cellular femtocells). These access options in one embodiment include various grades or levels of private and public access to available femtocell services. Each service may be separately assigned a various access type, such that a femtocell may service multiple users both within the “closed” group authorized by the femtocell white list, and non-members. In one variant, a femtocell broadcasts enhanced system information to all terminals (regardless of member/non-member status) such that a non-CSG (Closed Subscriber Group) member terminal or UE is capable of obtaining partial service access within the femtocell. Broadcast multimedia or other services can be delivered to both CSG members and non-members, advantageously without having to establish a dedicated connection for the non-member users.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 12, 2021
    Assignee: Apple Inc.
    Inventors: Andreas Schmidt, Martin Hans, Maik Bienas
  • Patent number: 10884972
    Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 5, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Martin Kessler, Lewis F. Lahr, William Hooper
  • Patent number: 10880117
    Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijeeth Aarey Premanath, Richard Edwin Hubbard, Maxwell Guy Robertson, Lokesh Kumar Gupta, Mark Edward Wentroble, Roland Sperlich, Dejan Radic
  • Patent number: 10880151
    Abstract: A notification control device includes a first communication status detector configured to detect a status of a first communication protocol of communication between a first device and a second device in a process control system, and a second communication status detector configured to detect a status of a second communication protocol of the communication. The first communication status detector inputs into an operation monitoring terminal first notification information to which tag information is added on the basis of notification common information in which a status of the first communication protocol, a status of the second communication protocol, and the tag information are associated and the detected status of first communication protocol. The second communication status detector inputs into the operation monitoring terminal second notification information to which the tag information is added on the basis of the notification common information and the detected status of second communication protocol.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 29, 2020
    Assignee: Yokogawa Electric Corporation
    Inventors: Hiroyuki Saito, Isamu Suzuki, Masanori Sueki
  • Patent number: 10869216
    Abstract: Techniques are provided for downloading of filtering rules from a remote server onto a mobile device. A priority list is determined from lists of filtering rules, the priority list having a highest indicator of frequency of actuation of the filtering rules from the lists. The filtering rules are designated for use by a first application on the mobile device. The priority list is transmitted to the mobile device with the aid of a second application, the second application on the mobile device being a provider of the filtering rules for the first application. Each of the remaining lists of filtering rules are divided into parts. Groups of filtering rules are generated based on frequency of actuation within each of the remaining lists of filtering rules, each group having not more than one part of each remaining list of filtering rules.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 15, 2020
    Assignee: AO Kaspersky Lab
    Inventors: Alexey P. Komissarov, Victor V. Yablokov, Alexey M. Chikov
  • Patent number: 10853214
    Abstract: An application processor includes a central processing unit, a root complex that communicates with at least one external device under control of the central processing unit and generates a state change interrupt when an operation state changes, and an interrupt aggregation and debug unit that performs debugging on at least one component associated with the state change interrupt depending on the state change interrupt.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Heon Lee
  • Patent number: 10852977
    Abstract: A system for providing a virtual data storage medium according to an embodiment of the invention may be a system for providing a virtual data storage medium using data storage federation, where the system may include: heterogeneous data storage media including a multiple number of data storage media using different interfaces, protocols, and commands for using stored data; and a federation unit configured to generate a virtual data storage medium by federating the heterogeneous data storage media.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: December 1, 2020
    Assignee: University-Industry Cooperation Group of Kyung-Hee University
    Inventors: Eui Nam Huh, Ka-Won Lee, Yunkon Kim
  • Patent number: 10831700
    Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: Daniel Wilson, Anand Dalal, Josh De Cesare
  • Patent number: 10827629
    Abstract: A SOM circuit board includes a main body having a first face surface, an opposing second face surface, a first side surface, an opposing second side surface, a first end surface, and an opposing second end surface. The first and second side surfaces have maximum lengths along a longitudinal direction which are greater than maximum lengths of the first and second end surfaces along a lateral direction. The SOM circuit board further includes a plurality of computing components, each of the plurality of computing components mounted on one of the first face surface or the second face surface. The SOM circuit board further includes an input/output connector mounted on the second face surface. The SOM circuit board further includes a plurality of mounting holes extending along the transverse direction through and between the first face surface and the second face surface.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: November 3, 2020
    Assignee: GE AVIATION SYSTEMS LLC
    Inventors: Randall Lee Neuman, Stefano Angelo Mario Lassini, Jason Eggiman
  • Patent number: 10817765
    Abstract: The present invention discloses an asynchronous serial communication system and method. The asynchronous serial communication system may include a semiconductor device having two terminals and configured to receive a voltage required for an operation from data transmitted through one terminal; and a controller configured to perform asynchronous serial communication with the semiconductor device with two terminals. The asynchronous serial communication system may perform asynchronous serial communication between the semiconductor device and the controller in order to write or read data through the one terminal.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 27, 2020
    Assignee: DUALITY INC.
    Inventor: Jin Hong Ahn
  • Patent number: 10797893
    Abstract: In one embodiment, a method includes detecting a slave device at a master device, determining at the master device if the slave device is configured for I2C (Inter-Integrated Circuit) or SPE (Single Pair Ethernet) based on an output at the slave device, and selecting an I2C mode of operation at the master device if the slave device is configured for I2C, or selecting an SPE mode of operation at the master device if the slave device is configured for SPE. Data and control are selected from an I2C controller at the master device in the I2C mode of operation and selected from a physical coding sublayer at the master device in the SPE mode of operation.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 6, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amrik S. Bains, Kenneth Christian Naumann
  • Patent number: 10742443
    Abstract: A method for transmitting messages in a data bus system, wherein the messages can be transmitted in the form of data frames by a data bus and a data frame that is to be sent by a bus subscriber is checked for a piece of changeover information, which method is furthermore distinguished in that changeover of the rise time and/or edge shape of edges of bit pulses of the data frame that is to be sent is performed on the basis of the presence of a defined value of the piece of changeover information. In addition, a corresponding transceiver and to an electronic control unit is disclosed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 11, 2020
    Assignees: Continental Teves AG & Co. oHG, NXP USA Inc.
    Inventors: Tobias Beckmann, Ireneusz Janiszewski, Claas Cornelius, Pierre Turpin, Eugeny Alexandrovich Kulkov, Robert Gach, Sergey Sergeevich Ryabchenkov
  • Patent number: 10740253
    Abstract: Technologies for facilitating communication between a master programmable logic controller and one or more target drives are disclosed. In an illustrative embodiment, a remote device emulation appliance is configured to receive a communication from a master programmable logic controller that is formatted according to a remote input/output protocol unusable by the target drive. The remote device emulation appliance converts the communication from the remote input/output protocol to a drive protocol usable by the target drive to control operations of the drive and transmits the converted communication to the target drive. The remote device emulation appliance may also convert communications received from the target drive from the drive protocol usable by the target drive to the remote input/output protocol and transmit such converted communications to the master programmable logic controller.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: August 11, 2020
    Assignee: ABB Schweiz AG
    Inventors: Bryan D. Sisler, Jeffrey M. Fell
  • Patent number: 10725960
    Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 28, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Morten Werner Lund, Lloyd Clark, Odd Magne Reitan
  • Patent number: 10725961
    Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 28, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Morten Werner Lund, Lloyd Clark, Odd Magne Reitan
  • Patent number: 10713193
    Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node, a second computer node and a control unit. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; (B) transmitting, by the first BMC and to the control unit, a control signal that corresponds to the reset command; and (C) transmitting, by the control unit and to the second BMC, a reset signal that corresponds to the control signal, so as to trigger reset of the second BMC.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Mitac Computing Technology Corporation
    Inventor: Ming-Shou Shen
  • Patent number: 10708357
    Abstract: A network-displaced direct storage architecture transports storage commands over a network interface. In one implementation, the architecture maps, at hosts, block storage commands to remote direct memory access operations (e.g., over converged Ethernet). The mapped operations are communicated across the network to a network storage appliance. At the network storage appliance, network termination receives the mapped commands, extracts the operation and data, and passes the operation and data to a storage device that implements the operation on a memory.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Ariel Hendel, Karagada Ramarao Kishore
  • Patent number: 10707875
    Abstract: Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 7, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Kent Orthner, Travis Johnson, Sarma Jonnavithula
  • Patent number: 10698847
    Abstract: This disclosure relates generally to bus interface systems for mobile user devices. In one embodiment, the bus interface system includes a first bus interface subsystem that operates in accordance with a one wire bus protocol, a second bus interface subsystem that operates in accordance with a Mobile Industry Processor Interface (MIPI) radio frequency front end (RFFE) bus protocol, and a translation bus controller that translates commands between the first bus interface subsystem and the second bus interface system. The translation bus controller is configured to implement cross over bus operations between a master bus controller that operates in accordance with in the one wire bus protocol and a slave bus controller in the second bus interface system. In this manner, the translation bus allows the master bus controller to be the master of different bus systems that operate in accordance with different bus protocols.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 30, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Alexander Wayne Hietala
  • Patent number: 10693816
    Abstract: Embodiments of the present disclosure disclose communication methods and systems, electronic devices, and computer clusters. The method includes: separately creating a corresponding thread for at least one of a plurality of target devices, where the created thread corresponding to the target device includes a communication thread and a message processing thread, and the message processing thread includes a message sending thread and/or a message receiving thread; and communicating with a corresponding target device on the basis of the corresponding created thread.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Beijing SenseTime Technology Development Co., Ltd
    Inventors: Yingdi Guo, Shengen Yan
  • Patent number: 10678213
    Abstract: An intrinsically-safe handheld field maintenance tool includes a controller, a process communication module, and a display. The process communication module is configured to communicate with a field device using a process communication protocol. The display is coupled to the controller. A user interface module is also coupled to the controller and is configured to receive user input. The controller is configured to detect a user input help request and provide a video output on the display in response to the user input help request.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: June 9, 2020
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Susan A. Campbell, Christopher G Kasic, Christopher P Kantzes