Abstract: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device to serially transmit a transmission signal, generated by the communication control device, onto a bus, and serially receive signals from the bus. The communication control device generates the transmission signal according to a frame and inserts into the frame two check sums that include different bits of the frame in the computation. The communication control device inserts dynamic stuff bits into the frame in such a way that an inverse stuff bit is inserted into the bit stream of the frame after 5 identical bits in succession. The communication control device computes the two check sums so that a maximum of one of the two check sums includes the dynamic stuff bits in the computation.

Abstract: A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.

Abstract: Examples of synchronization of a gyroscope in a virtual-reality (VR) environment are described. In some examples, gyroscopic feedback for VR application content may be predicted. In some examples, a time shift corresponding to a physical system lag of a gyroscope may be added to synchronize the gyroscopic feedback with the VR application content. In some examples, the gyroscopic feedback may be applied based on the time shift.

Abstract: An unauthorized frame detection device that can keep an unauthorized ECU from spoofing as a legitimate server or client while suppressing an overhead during communication is provided. The unauthorized frame detection device includes a plurality of communication ports corresponding to the respective of networks, a communication controller, and an unauthorized frame detector. The plurality of communication ports are each connected to a corresponding predetermined network among the plurality of networks and each transmit or receive a frame via the predetermined network. The unauthorized frame detector determines whether an identifier of a service, a type of the service, and port information that are each included in the frame match a permission rule set in advance and outputs a result of the determination.

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

Abstract: The present disclosure relates to a consumable chip system and a consumable container. The consumable chip system includes a consumable chip and an antenna board. The consumable chip includes a first die and a first substrate. The first die is encapsulated on the first substrate, and the first die is provided with an interface module. The first substrate is provided with a signal conversion module, and the antenna board is provided with a wireless transceiver module. The wireless transceiver module is configured to receive connection information and an instruction for storing and reading. The signal conversion module is connected to the interface module and the wireless transceiver module, respectively. The consumable chip system is configured to receive connection information by the wireless transceiver module, and establish a wireless connection between the consumable chip and a device for storing and reading on the basis of the connection information.

Abstract: A machine power system of a machine may use energy provided by one or more batteries. The machine power system may also use battery data associated with the batteries to monitor the batteries, configure electrical components to operate in association with the batteries, to provide battery information via a user interface, and/or for other operations. The machine power system may be configured to use a particular battery data format. A battery data translator receives native battery data provided by a battery, uses a translation map associated with the battery to convert the native battery data into translated battery data formatted based on the particular battery data format used by the machine power system, and provides the translated battery data to the machine power system.

Abstract: A transceiver device for a user station of a serial bus system, a communication control device, and a method. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus of the bus system, a reception module for receiving the signal from the bus, the reception module being designed to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place as a result of the operating mode changeover signal.

Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Abstract: Various embodiments to enable Spectrum Access System (SAS) interference mitigation options are disclosed herein. In one embodiment, an apparatus is provided. The apparatus includes a memory to store a data sequence, and one or more processing devices coupled to the memory. The processing devices to generate an interference metric associated with a first group and a second group of infrastructure nodes of a Long-Term Evolution (LTE) network infrastructure based on measurement information. The measurement information comprises measurements related to the transmission of data sequences associated with the first group and the second group. Thereupon, configuration settings are determined for infrastructure nodes of the first group and second group based on the generated interference metric. Each configuration setting represents a frequency band and transmission power level for a corresponding infrastructure node to access data in the LTE network infrastructure.

Abstract: An I2C apparatus (100) comprising: a master device (102) and two slave devices connected through an I2C bus, whereby the two slave devices are programmed with the same default device address. A first slave device (108) is connected to the bus in a conventional configuration whereas a second slave device (110) is connected to the bus in a cross connected configuration such that a clock pin of the second slave is connected to the serial data line and the data pin of the second slave is connected to the serial clock line. In response to a detection that the data pin of the second slave is connected to the serial clock line, the second slave swaps the lines going from the clock and data pins to processing logic of the second slave; and modifies its default device address to ensure that each slave device has a unique device address.

Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

Abstract: A message-level policy implemented with for a message routing system may be used to mediate between a variety of message sources and message targets that receive and use messages. The message-level policy may allow fine grained message-by-message policy assessment that a message routing system policy may be able to provide. The message-level policy may furthermore interact with the message routing system policy to provide mechanisms to avoid accidental leakage of protected messages or spill-over to protected regions.

Abstract: An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

Abstract: A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.

Abstract: A communication system intended for use in a motor vehicle includes a plurality of devices (26, 28), a transmission channel (32) that connects the plurality of devices (26, 28) to one another, and a signal source (30) coupled to the transmission channel (32). Each of the devices (26, 28) includes a control unit (36) configured for evaluating signals of the transmission channel (32), and at least two coupling units (38, 40) configured for connecting and disconnecting the particular device (26, 28) to/from the transmission channel (32). The control units (36) of the devices (26, 28) are configured for causing the coupling units (38, 40), at a certain point in time, in each case to connect no more than one of the devices (26, 28) to the transmission channel (32), and to disconnect the other of the devices (26, 28) from the transmission channel (32).

Abstract: An electronic control unit for vehicle capable of receiving a program by communication expands the received program in a volatile memory and executes the expanded program. As an example of this program, there is a program for changing a communication environment for communicating with another unit.

Abstract: An electric system for transmitting serial communication messages with different priorities over a communication link. The data to be transmitted is arranged in serial communication messages comprising a start of packet (SOP) symbol and data symbols. The ongoing transmission of a first message is interrupted if a SOP symbol of a second message is sent before the first message has been completed. Transmission of the first message is continued only after the second message has been sent.

Abstract: In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.

Abstract: Provided are an in-vehicle communication apparatus, a communication program, and a message transmission method. The in-vehicle communication apparatus according is connected to another apparatus via a plurality of communication lines, and includes a plurality of communication units that are provided respectively for the communication lines, and transmit/receive a message via the communication lines, a classification processing unit that performs processing for classifying messages that are to be transmitted to the other apparatus, into a plurality of groups in accordance with priorities of the messages and a message transmission processing unit that distributes messages classified into each of the plurality of groups, to one or more communication units allocated to the group, and the number of communication units allocated to a group into which a higher-priority message is classified is larger than the number of communication units allocated to a group into which a lower-priority message is classified.

Abstract: An apparatus and method for controlling an interface between a plurality of processors in an electronic device are disclosed. The electronic device may include: a first integrated circuit; a second integrated circuit; and a Peripheral Component Interconnect Express (PCIe) interface interconnecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit may be configured to identify the required latency level associated with a service provided by the electronic device, and restrict the use of at least one power mode among a plurality of power modes supported by the PCIe interface, based on the required latency level associated with the service. Additional embodiments are possible.

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

Abstract: A device, having a safe state, is coupleable to a communication bus. The device includes a first logic unit; a second logic unit; a monitoring circuit; a transmission unit; and a first test line. The device is adapted such that the first logic unit communicates with a bus via the transmission unit in a communication phase and the monitoring circuit emits a monitoring signal to the transmission unit upon a fault so that the transmission unit blocks the communication. The first and/or the second logic unit is coupled to the monitoring circuit via the first test line so as to emit a first test signal to the monitoring circuit.

Abstract: Techniques are provided for generating groups of filtering rules. A priority list of filtering rules having a highest indicator of frequency of utilization among the filtering rules from the plurality of lists is determined from a plurality of lists of filtering rules. The priority list of filtering rules is transmitted to a mobile device. Each of remaining lists of filtering rules that have not been transmitted to the mobile device is divided into a plurality of parts. A plurality of groups of filtering rules is generated based on frequency of utilization within each of the remaining lists of filtering rules. Each generated group contains at most one part of each remaining list of filtering rules.

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for routing events of an event stream in a stream processing system. One of the methods includes receiving, by a router, an event stream of events; identifying, for each event, by the router, a respective partition of context data that includes context data related to the event and providing the event to a respective local modeler that stores the partition of context data identified for the event in operational memory of the local modeler; processing, by each local modeler, events received from the router and aggregating information associated with each event to generate aggregated information; providing, by one or more of the local modelers, to a central modeler, the respective aggregated information; and determining, by the central modeler, a plurality of parameters of a machine learning model using the received aggregated information.

Abstract: A method and device are for recognizing an apparatuses and computer readable storage medium and program are provided. In an embodiment, the method includes reading a combined sequence table including candidate device information, candidate communication parameters and historical occurrence numbers of combinations of the candidate device information and the candidate communication parameters for each candidate device information; determining priority levels of the combinations according to the historical occurrence numbers; and determining a current combination according to the priority levels, sending a message to the apparatus to be recognized by using a candidate communication parameter in the current combination, and determining whether the current combination is the correct combination capable of establishing a communication with the apparatus to be recognized according to a feedback from the apparatus to be recognized.

Abstract: A method for monitoring automatic mechanical devices selected from at least one of automatic doors and automatic dock equipment located at a commercial site. The method may include installing, at the commercial site, a plurality of internet-of-things (IoT) monitoring devices. Each of the IoT monitoring devices may include a plurality of connectors corresponding to respective data communication standards, and a wireless transceiver configured to transmit operational information. Electronic communication between each automatic mechanical device and one of the IoT monitoring devices may be established via one of the connectors. A device profile may be assigned for each of the automatic mechanical devices. Each device profiles defines a respective connector and combination of manufacturer and device model.

Abstract: A system and method for providing security to a network may include maintaining, by a processor, a model of an expected behavior of data communications over the in-vehicle communication network; receiving, by the processor, a message sent over the network; determining, by the processor, based on the model and based on a timing attribute of the message, whether or not the message complies with the model; and if the message does not comply with the model then performing, by the processor, at least one action related to the message.

Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

Abstract: A bus system is provided. The bus system includes a master device and a plurality of slave devices electrically connected to the master device. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When the alert handshake control line is at a first voltage level and a first slave device want to communicate with the master device, the first slave device controls the alert handshake control line to a second voltage level via the alert handshake pin, such that the slave devices enter a synchronization stage. Among phases of each assignment period, in a first phase corresponding to the first slave device, the first slave device controls the alert handshake control line to the second voltage level via the alert handshake pin.

Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Abstract: A method for the distributed processing of process data in a local bus, wherein the local bus has a local bus master and at least two data bus participants, and the method comprises: sending a data packet with process data from the local bus master via the local bus; receiving the data packet at a first data bus participant; pre-processing at least one item of process data using the first data bus participant; sending the data packet with the at least one item of pre-processed process data via the local bus to the second data bus participant using the first data bus participant; receiving the data packet with the at least one item of pre processed process data at the second data bus participant; and further processing the at least one item of pre-processed process data using the second data bus participant.

Abstract: This disclosure describes systems, methods, and apparatus for a combined LED driver and emergency backup battery system. The LED driver can include current regulation circuitry as well as a bus enabling charging and discharging of an energy storage device from and to the bus. A master controller can control charging and discharging of the energy storage device via a controller of an energy storage management system, and also communicate with the current regulation circuitry to control a balance of power between an AC mains, the energy storage device, and driving of an LED light source. Accessories may be coupled to the bus and receive low voltage power from the bus and optionally receive commands from the master controller and provide sensed data back to the controller. A wireless network interface to the master controller can enable system states based on electrical power company indications and instructions.

Abstract: A method and apparatus to reduce read latency and improve read quality of service (Read QoS) for non-volatile memory, such as NAND array in a NAND device. For read commands that collide with an in-progress program array operation targeting the same program locations in a NAND array, the in-progress program is suspended and the controller allows the read command to read from the internal NAND buffer instead of waiting for the in-progress program to complete. For read commands queued during an in-progress program that is processing pre-reads in preparation for a program array operation, pre-read bypass allows the reads to be serviced between the pre-reads and before the program's array operation starts. In this manner, read commands can be serviced without suspending the in-progress program. Allowing internal NAND buffer reads and enabling pre-read bypass reduces read latency and improves Read QoS.

Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.

Abstract: A system controller of a memory system can present multiple physical functions (PFs) to a host computing system. The system controller can store commands from the host in separate queues and uses an arbiter circuit to issue commands. The arbiter can determine a difference value between a quota of commands and a count of commands issued from a respective queue. The quota is derived from a share specified by the host for the respective PF. The arbiter circuit determines a subset of queues by excluding queues that are empty and queues having a negative difference value. The arbiter circuit can randomly choose a selected queue from the subset and issue a command from the selected queue.

Abstract: A power distribution bus bar is provided for distributing power to surface mount connectors. In use, the power distribution bus bar includes a circuit board and at least two add-in card connectors each mounted to a first surface of the circuit board. Additionally, at least one power supply connector distributing a power supply to the add-in card connectors is provided. The at least one power supply connector may be mounted to a second surface of the circuit board and connected to the at least two add-in card connectors.

Abstract: Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes a plurality of slave radio frequency (RF) devices, a master RF device configured to set a configuration parameter in a register to be applied by an RF slave device of the plurality of RF slave devices, and a clock line coupled between the master RF device and the plurality of slave RF devices. The slave RF device may be configured to: count a number of cycles of a clock signal on the clock line; and apply the configuration parameter for the slave RF device based on the count of the number of cycles, wherein the master RF device is further configured to disable an interrupt reporting function of the plurality of slave RF device during a time period between setting the configuration parameter in the register and the configuration parameter being applied.

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node and a second computer node. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; and (B) transmitting, by the first BMC and to the second BMC via electrical connection between the first and second BMCs, a reset signal that corresponds to the reset command, so as to trigger reset of the second BMC.

Abstract: Provided are a method, system, and computer program product in which a storage controller receives a first write command with a first token over a first interface from a host computational device. In response to a failure of the first write command in the storage controller, the storage controller retains selected resources for reuse for a retry of the first write command, wherein the retry of the first write command is expected from the host computational device over a second interface that is a slower communication link than the first interface. In response to receiving, by the storage controller, a second write command with a second token over the second interface, wherein the second token is identical to the first token, the storage controller determines that the second write command is a retry of the first write command and reuses the retained selected resources for executing the second write command.

Abstract: A multiplexor for an I3C) network includes a switch, a routing map, and an interrupt detector. The switch selectably couples I3C slave interfaces to I3C master interfaces. The routing map includes map entries associating each I3C slave interface with an I3C master interfaces based upon an I3C address of the I3C slave interface, such that, for each map entry, an IBI received from the associated I3C slave interface is mapped to the associated I3C master interface. The interrupt detector detects an IBI from an I3C slave interface, determines that a map entry associated with the I3C slave interface maps the I3C slave interface with a particular I3C master interface based upon the IBI, and directs the switch to couple the I3C slave interface to the I3C master interface based upon the map entry.

Abstract: Embodiments are provided herein for component composition of a disaggregated computing system. A plurality of general purpose links connecting a computing element to other hardware elements are provided within the disaggregated computing system. Each of the plurality of general purpose links comprise a point-to-point connection to at least one of the other hardware elements such that the plurality of general purpose links conform to a configuration used by the other hardware elements regardless of a type of data being transferred through the plurality of general purpose links.

Abstract: Methods and apparatus for providing enhanced access options for wireless access points (e.g., cellular femtocells). These access options in one embodiment include various grades or levels of private and public access to available femtocell services. Each service may be separately assigned a various access type, such that a femtocell may service multiple users both within the “closed” group authorized by the femtocell white list, and non-members. In one variant, a femtocell broadcasts enhanced system information to all terminals (regardless of member/non-member status) such that a non-CSG (Closed Subscriber Group) member terminal or UE is capable of obtaining partial service access within the femtocell. Broadcast multimedia or other services can be delivered to both CSG members and non-members, advantageously without having to establish a dedicated connection for the non-member users.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: A notification control device includes a first communication status detector configured to detect a status of a first communication protocol of communication between a first device and a second device in a process control system, and a second communication status detector configured to detect a status of a second communication protocol of the communication. The first communication status detector inputs into an operation monitoring terminal first notification information to which tag information is added on the basis of notification common information in which a status of the first communication protocol, a status of the second communication protocol, and the tag information are associated and the detected status of first communication protocol. The second communication status detector inputs into the operation monitoring terminal second notification information to which the tag information is added on the basis of the notification common information and the detected status of second communication protocol.

Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.

Abstract: Techniques are provided for downloading of filtering rules from a remote server onto a mobile device. A priority list is determined from lists of filtering rules, the priority list having a highest indicator of frequency of actuation of the filtering rules from the lists. The filtering rules are designated for use by a first application on the mobile device. The priority list is transmitted to the mobile device with the aid of a second application, the second application on the mobile device being a provider of the filtering rules for the first application. Each of the remaining lists of filtering rules are divided into parts. Groups of filtering rules are generated based on frequency of actuation within each of the remaining lists of filtering rules, each group having not more than one part of each remaining list of filtering rules.

Abstract: A system for providing a virtual data storage medium according to an embodiment of the invention may be a system for providing a virtual data storage medium using data storage federation, where the system may include: heterogeneous data storage media including a multiple number of data storage media using different interfaces, protocols, and commands for using stored data; and a federation unit configured to generate a virtual data storage medium by federating the heterogeneous data storage media.