METHOD TO COOL BAKE PLATES IN A TRACK LITHOGRAPHY TOOL

Abstract

A method of reducing a temperature of a bake plate within a semiconductor processing tool includes (a) providing a substrate and (b) transferring the substrate to a position adjacent the bake plate. The bake plate is characterized by an initial bake plate temperature greater than a set point temperature. The method also includes (c) reducing the temperature of the bake plate by a first predetermined amount and (d) transferring the substrate from the position adjacent the bake plate to a position adjacent a chill plate. The chill plate is characterized by a chill plate temperature less than the set point temperature. The method further includes (e) transferring the substrate from the position adjacent the chill plate to the position adjacent the bake plate, (f) reducing the temperature of the bake plate by a second predetermined amount, (g) monitoring the temperature of the bake plate, and (h) repeating steps (d) through (g) until the bake plate temperature is within a predetermined tolerance of the set point temperature.

Description

BACKGROUND OF THE INVENTION

The present invention relates generally to the field of substrate processing equipment. More particularly, the present invention relates to a method for controlling the temperature of substrates, such as semiconductor substrates, used in the formation of integrated circuits.

Modern integrated circuits contain millions of individual elements that are formed by patterning the materials that make up the integrated circuit, such as silicon, metal and/or dielectric layers, to sizes that are small fractions of a micrometer. One of the techniques used throughout the industry for forming such patterns is photolithography. A typical photolithography process sequence generally includes applying a uniform photoresist (resist) layer on the surface of a substrate, drying and curing the deposited layer, patterning the layer by exposing the photoresist to intense light of a particular wavelength that is suitable for modifying the exposed layer, and then developing the patterned photoresist layer.

It is common in the semiconductor industry for many of the steps associated with the photolithography process to be performed in a multi-chamber processing system (e.g., a cluster tool) that has the capability to sequentially process semiconductor wafers in a controlled manner. One example of a cluster tool that is used to deposit (i.e., coat) and develop a photoresist material is commonly referred to as a track lithography tool.

Track lithography tools typically include a mainframe that houses multiple chambers (which are sometimes referred to herein as stations) dedicated to performing the various tasks associated with pre- and post-lithography processing. There are typically both wet and dry processing chambers within track lithography tools. Wet chambers include coat and/or develop bowls, while dry chambers include thermal control units that house bake and/or chill plates. Track lithography tools also frequently include one or more pod/cassette mounting devices, such as an industry standard FOUP (front opening unified pod), to receive substrates from and return substrates to the clean room, multiple substrate transfer robots to transfer substrates between the various chambers/stations of the track tool, and an interface that allows the tool to be operatively coupled to a lithography exposure tool.

Over the years there has been a strong push within the semiconductor industry to shrink the size of semiconductor devices. The reduced feature size has caused the industry's tolerance of process variability to shrink, which in turn, has resulted in semiconductor manufacturing specifications having more stringent requirements for process uniformity and repeatability. An important factor in minimizing process variability during track lithography processing sequences is to ensure that every substrate processed within the track lithography tool for a particular application has the same “wafer history.” A substrate's wafer history is generally monitored and controlled by process engineers to ensure that all device fabrication processing variables that may later affect a device's performance are controlled, ensuring that all substrates in the same batch are always processed the same way.

To ensure that each substrate has the same wafer history requires that each substrate experience the same repeatable processing steps (e.g., consistent coating process, consistent hard bake process, consistent chill process, etc.) and that the timing between the various processing steps is the same for each substrate. Lithography type device fabrication processes can be especially sensitive to variations in process recipe variables and the timing between recipe steps, which can directly affect process variability and ultimately device performance.

One source of variation that may affect wafer history is the change of process conditions between different process recipes. For example, a particular process recipe in a track lithography tool may require a bake process at a set point temperature of 150° C. Generally, substrates are processed in batches, which may consist of as few as one or as many as 100 or more substrates, and each substrate within a batch is usually processed using the same process recipe. However, substrates in subsequent batches may require a different process recipe, for example, a bake process with a set point temperature of 120° C. In this case the bake plate temperature must be rapidly changed from 150° C. to 120° C. to minimize the time between recipes and the impact on wafer history. Also, minimizing the time between recipes increases throughput which provides efficient utilization of the track lithography tool.

One approach that has been utilized to reduce the temperature of a bake plate is to turn off the power to the bake plate heater and let the bake plate cool unassisted. This approach has the advantage of requiring no additional hardware or modifications to existing hardware. However, the cooling rate of a bake plate, which may be made of a metal or ceramic material, is slow, and the extended time between recipes can adversely affect wafer history and throughput.

As an alternative approach, the cooling rate of a bake plate may be enhanced by forcing air over the surface of the bake plate. This approach reduces idle time and thus improves throughput, but the cooling is generally non-uniform across the bake plate and thus requires an increase in temperature stabilization time. In addition, semiconductor devices are extremely sensitive to contamination and particles, and forcing air across the surface of a bake plate increases the risk of either or both of these problems occurring.

Another more complex approach requires placing chilled disks of varying thermal mass on the bake plate to conduct heat away from the bake plate. The thermal mass of the disks is varied by altering the thickness and/or material of the disks. Under this approach, a controller determines which disks to use depending on the bake plate temperature and the desired set point temperature. The disks are placed on the bake plate for either a specified period of time or until the bake plate reaches a set point temperature. Additionally, the temperature of the chilled disks may be controlled to further optimize the cooling rate of the bake plate. Although this approach increases the cooling rate of the bake plate, it requires substantial hardware modifications to store and cool the disks as well as the ability to transfer and stack multiple disks on the bake plate. These modifications result in a larger and more expensive track lithography tool.

As a result, there is a need for a method of rapidly and uniformly cooling a bake plate in a track lithography tool that doesn't introduce contamination or particles and that requires minimal hardware modifications.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method of reducing a temperature of a bake plate within a semiconductor processing tool is provided. The method includes: (a) providing a substrate and (b) transferring the substrate to a position adjacent the bake plate. The bake plate is characterized by an initial bake plate temperature greater than a set point temperature. The method also includes (c) reducing the temperature of the bake plate by a first predetermined amount and (d) transferring the substrate from the position adjacent the bake plate to a position adjacent a chill plate. The chill plate is characterized by a chill plate temperature less than the set point temperature. The method further includes (e) transferring the substrate from the position adjacent the chill plate to the position adjacent the bake plate, (f) reducing the temperature of the bake plate by a second predetermined amount, (g) monitoring the temperature of the bake plate, and (h) repeating steps (d) through (g) until the bake plate temperature is within a predetermined tolerance of the set point temperature.

According to another embodiment of the present invention, a method of reducing a temperature of a bake plate within a track lithography tool is provided. The method includes: (a) providing a substrate and (b) transferring the substrate to a position adjacent the bake plate. The bake plate is characterized by an initial bake plate temperature greater than a set point temperature. The method also includes (c) performing a first heat transfer process for a first predetermined time period to reduce the temperature of the bake plate and (d) transferring the substrate from the position adjacent the bake plate to a position adjacent a chill plate. The chill plate is characterized by a chill plate temperature less than the set point temperature. The method further includes (e) transferring the substrate from the position adjacent the chill plate to the position adjacent the bake plate, (f) performing a second heat transfer process for a second predetermined time period to reduce the temperature of the bake plate, (g) monitoring the temperature of the bake plate, and (h) repeating steps (d) through (g) until the temperature of the bake plate is within a predetermined tolerance of the set point temperature.

According to yet another embodiment of the present invention, a method of cooling a bake plate is provided. The method includes: (a) providing a substrate and (b) transferring the substrate to a position adjacent the bake plate. The bake plate is characterized by an initial bake plate temperature greater than the set point temperature. The method also includes (c) performing a first heat transfer process for a first predetermined time period to reduce a temperature of the bake plate, (d) removing the substrate from the bake plate, (e) transferring the substrate to the position adjacent the bake plate, (f) performing a second heat transfer process for a second predetermined time period to reduce the temperature of the bake plate, (g) monitoring the temperature of the bake plate, and (h) repeating steps (d) through (g) until the temperature of the bake plate is within a predetermined tolerance of the set point temperature.

Many benefits are achieved by way of the present invention over conventional techniques. For example, embodiments of the present invention provide methods for rapidly and uniformly cooling a bake plate. Additionally, embodiments of the present invention can be integrated within new or existing track lithography tools without significant hardware modifications. Depending upon the embodiment, one or more of these benefits, as well as other benefits, may be achieved. The objects, features, and advantages of the present invention, which to the best of our knowledge are novel, are set forth with particularity in the appended claims. The present invention, both as to its organization and manner of operation, together with further objects and advantages, may best be understood by reference to the following description, taken in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of one configuration of a track lithography tool;

FIG. 2 is a simplified perspective view of an integrated thermal unit;

FIG. 3 is a simplified perspective view of the integrated thermal unit depicted in FIG. 2 with the top of the unit removed;

FIG. 4 is a perspective view of one configuration of a bake station;

FIG. 5 is a perspective view of a cross-section of the bake station shown in FIG. 4;

FIG. 6 is a cross-sectional view of the bake station shown in FIG. 5;

FIG. 7 is a simplified flowchart illustrating a method of reducing the temperature of a bake plate within a semiconductor processing tool according to an embodiment of the present invention; and

FIG. 8 is a simplified flowchart illustrating a method of cooling a bake plate according to another embodiment of the invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The present invention generally provides methods for heating and cooling substrates in a highly controllable manner. While it is to be recognized that embodiments of the invention are particularly useful in helping to ensure a consistent wafer history for each substrate in a plurality of substrates that are heated and cooled according to a particular thermal recipe within a track lithography tool, other embodiments of the invention can be used in other applications where it is desirable to heat and cool substrates in a highly controllable manner. Thus, the invention should not be construed as limited to the embodiments set forth herein. The present invention is described more fully below with reference to the accompanying drawings, where like numbers refer to like elements throughout.

FIG. 1 is a plan view of one configuration of a track lithography tool 100 in which the embodiments of the present invention may be used. As illustrated in FIG. 1, track lithography tool 100 contains a front end module 128 (sometimes referred to as a factory interface), a central module 136, and a rear module 146 (sometimes referred to as a scanner interface). Front end module 128 generally contains one or more pod assemblies or FOUPS (e.g., items 112A-D), a front end robot 124, and front end processing racks 122A and 122B. The one or more pod assemblies 112A-D are generally adapted to accept one or more cassettes 110 that may contain one or more substrates, or wafers (“W”), that are to be processed in track lithography tool 100. Central module 136 generally contains a first central processing rack 132A, a second central processing rack 132B, and a central robot 134. Rear module 146 generally contains first and second rear processing racks 142A and 142B and a back end robot 144.

Front end robot 124 is adapted to access processing modules in front end processing racks 122A and 122B. Central robot 134 is adapted to access processing modules in front end processing racks 122A and 122B, central processing racks 132A and 132B, and rear processing racks 142A and 142B. Back end robot 144 is adapted to access processing modules in rear processing racks 142A and 142B and in some cases exchange substrates with a stepper/scanner 140.

The stepper/scanner 140, which may be purchased from Canon USA, Inc. of San Jose, Calif., Nikon Precision Inc. of Belmont, Calif., or ASML US, Inc. of Tempe, Ariz., is a lithographic projection apparatus used, for example, in the manufacture of integrated circuits (ICs). The stepper/scanner tool 140 exposes a photosensitive material (resist), deposited on the substrate in the cluster tool, to electromagnetic radiation to generate a pattern corresponding to an individual layer of the integrated circuit device to be formed on the substrate surface.

Each of the processing racks 122A/122B, 132A/132B, and 142A/142B, contain multiple processing modules in a vertically stacked arrangement. That is, each of the processing racks may contain multiple stacked integrated thermal units 116, multiple stacked coater modules 130, multiple stacked coater/developer modules with shared dispense 138, or other modules that are adapted to perform the various processing steps required of a track photolithography tool. As examples, coater modules 130 may deposit a bottom antireflective coating (BARC), coater/developer modules 138 may be used to deposit and/or develop photoresist layers, and integrated thermal units 116 may perform bake and chill operations associated with hardening BARC and/or photoresist layers.

In one configuration, a system controller 114 is used to control all of the components and processes performed in the cluster tool 100. The controller 114 is generally adapted to communicate with the stepper/scanner 140, monitor and control aspects of the processes performed in the cluster tool 100, and is adapted to control all aspects of the complete substrate processing sequence. In some instances, controller 114 works in conjunction with other controllers, such as controllers 210A-210D in FIG. 2, which control certain aspects of the processing sequence of bake station 118 and chill plate 120 of integrated thermal unit 116. The controller 114, which is typically a microprocessor-based controller, is configured to receive inputs from a user and/or various sensors in one of the process chambers and appropriately control the process chamber components in accordance with the various inputs and software instructions retained in the controller's memory. The controller 114 generally contains memory and a CPU (not shown) which are utilized by the controller to retain various programs, process the programs, and execute the programs when necessary. The memory (not shown) is connected to the CPU, and may be one or more of a readily available memory, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage which may be local or remote. Software instructions and data can be coded and stored within the memory for instructing the CPU. The support circuits (not shown) are also connected to the CPU for supporting the processor in a conventional manner. The support circuits may include cache, power supplies, clock circuits, input/output circuitry, subsystems and the like all well known in the art. A program (or computer instructions) readable by the controller 114 determines which tasks to perform in the process chambers. Preferably, the program is software readable by the controller 114 and includes instructions to monitor and control the process based on defined rules and input data.

It is to be understood that embodiments of the invention are not limited to use with a track lithography tool such as that depicted in FIG. 1. Rather, embodiments of the invention may be used in any substrate processing tool including the many different tool configurations described in U.S. application Ser. No. 11/112,281 entitled “Cluster Tool Architecture for Processing a Substrate” filed on Apr. 22, 2005, which is hereby incorporated by reference for all purposes. In addition, embodiments of the invention may be used in conjunction with other substrate processing tools.

As shown in FIG. 2, which is a simplified perspective view of the integrated thermal unit 116 depicted in FIG. 1, thermal unit 116 includes an exterior housing 212 made of aluminum or another suitable material. Housing 212 is long relative to its height in order to allow bake station 118, chill plate 120 and shuttle station 126 (shown in FIG. 1) to be laterally adjacent to each other and to allow multiple integrated thermal units to be stacked on top of each other in a track lithography tool as described above with respect to FIG. 1. In one particular configuration housing 212 is just 20 centimeters high.

Housing 212 includes side pieces 212A, a top piece 212B and a bottom piece 212C. Front side piece 212A includes two elongated openings 216A and 216B that allow substrates to be transferred into and out of the thermal unit. Opening 216A is operatively coupled to be closed and sealed by a shutter (not shown), and opening 216B is also operatively coupled to be closed and sealed by a shutter (also not shown). Top piece 212B of housing 212 includes coolant channels 218 that allow a coolant fluid to be circulated through the channels in order to control the temperature of top piece 212B when an appropriate plate (not shown) is attached to top piece 212B via screw holes 214. Similar coolant channels are formed in the lower surface of bottom piece 212C.

Also shown in FIG. 2 is various control circuitry 210A-210D which controls the precision baking operation of bake station 118 and the precision cooling operation of chill plate 120. FIG. 2 also shows tracks 220 and 222 which enable shuttle 126 (shown in FIG. 3) to move linearly along the length of the thermal unit and vertically within the thermal unit. In one configuration, control circuitry 210A-210D is positioned near bake station 118 and chill plate 120 in order to enable more accurate and responsive control of temperature adjusting mechanisms associated with each station.

FIG. 3 is a simplified perspective view of integrated thermal unit 116 as seen with top 212B removed. In FIG. 3, shuttle 126, chill plate 120 and bake station 118 are visible. Also visible is a space 310 between rear support piece 312 of housing 212 and bottom piece 212C. Space 310 extends along much of the length of integrated thermal unit 116 to allow shuttle 126 to transfer wafers between bake station 118 and chill plate 120 as discussed below in detail.

Reference is now made to FIGS. 4, 5 and 6. FIG. 4 is a perspective view of one configuration of a bake station 118, FIG. 5 is a perspective view of a cross-section of the bake station 118 shown in FIG. 4, and FIG. 6 is a cross-sectional view of the bake station 118 shown in FIG. 5 with top piece 212B of housing 212 attached. As shown in FIGS. 4-6, bake station 118 has three separate isothermal heating elements: bake plate 510 (FIGS. 5 and 6 only), top heat plate 410, and side heat plate 412. Each of the heating elements are manufactured from a material exhibiting a high heat conductivity, such as aluminum or an other appropriate material. Each plate (510, 410 and 412) has a heating element, for example resistive heating elements, embedded within the plate. Bake station 118 also includes side heat shields, indicated as 416 and 418, as well as a bottom cup 420 that surrounds bake plate 510 and lid 610 (shown in FIG. 6 only). Each of heat shields 416, 418, cup 420 and lid 610 are made from aluminum. Lid 610 is attached to top heat plate 410 by screws through threaded holes 422.

Bake plate 510 is operatively coupled to a motorized lift 516 so that the bake plate can be raised into the clam shell enclosure and lowered into a wafer receiving position. Typically, wafers 620 are heated on bake plate 510 when it is raised to a baking position 624 as shown in FIG. 6. When in baking position 624, cup 420 encircles a bottom portion of side heat plate 412 forming a clam shell arrangement that helps confine heat generated by bake plate 510 within an inner cavity formed by the bake plate and the enclosure. In one configuration the upper surface of bake plate 510 includes a plurality of wafer pocket buttons and proximity pins similar to those with respect to shuttle 126 and chill plate 120. Also, in some configurations bake plate 510 includes a plurality of vacuum ports that can be operatively coupled to a vacuum to secure a wafer to the bake plate during the baking process.

During the baking process, faceplate 618 is positioned just above and opposite the upper surface of bake plate 510. Faceplate 618 can be made from aluminum as well as other suitable materials and includes a plurality of holes or channels 622 that allow gases and contaminants that are volatized during the bake process to drift through faceplate 618 and into a radially inward gas flow 616 that is created between faceplate 618 and top heat plate 410.

Gas from radially inward gas flow 616 is initially introduced into bake station 118 at an annular gas manifold 612 that encircles the outer portion of top heat plate 410 by gas inlet line 424. Gas manifold 612 includes numerous small gas inlets 414 that allow gas to flow from manifold 612 into the cavity 620 between the lower surface of the top heat plate 410 and the upper surface of the faceplate 618. The gas flows radially inward toward the center of the station through a diffusion plate 512 that includes a plurality of gas outlet holes 514. After flowing through diffusion plate 512, the gas exits bake station 118 through gas outlet line 428.

As previously mentioned, bake plate 510 heats a wafer according to a particular thermal recipe. One component of the thermal recipe is the set point temperature to which the bake plate heats the wafer. During the baking process, the temperature of the wafer is routinely measured and one or more zones of the bake plate can be adjusted independently to ensure uniform heating of the substrate. Typically bake plate 510 is heated to the desired set point temperature while a large batch of wafers are processed according to the same thermal recipe. Thus, for example, if a particular thermal recipe calls for a set point temperature of 150° C., and that recipe is to be implemented on 100 consecutive wafers, bake plate 510 will be heated to 15° C. while the 100 wafers are processed. If, however, a subsequent batch of wafers is to be processed according to a different thermal recipe, for example, that requires a set point temperature of 120° C., the set point temperature of bake plate 510 needs to be rapidly changed from 150° C. to 120° C. Embodiments of the present invention enable a rapid reduction in the set point temperature of bake plate 510, which helps minimize delay associated with switching from one thermal recipe to another thermal recipe and thus helps ensure high wafer throughput through integrated thermal unit 116.

FIG. 7 is a simplified flowchart illustrating a method 700 of reducing the temperature of a bake plate within a semiconductor processing tool according to an embodiment of the present invention. Method 700 can be used, for example, to reduce the temperature of the bake plate when switching from one thermal recipe to another thermal recipe that has a lower set point temperature. In the first step 710 a substrate is provided to be used in the process. In step 712 the substrate is transferred to a position adjacent the bake plate. The substrate may be in substantial contact with the bake plate while in the position adjacent the bake plate, or it may be supported by proximity pins which create a gap between the substrate and the bake plate. In step 714 the temperature of the bake plate is reduced by a first predetermined amount by transferring thermal energy from the bake plate to the substrate. In step 716 the substrate is transferred from the position adjacent the bake plate to a position adjacent a chill plate. In the position adjacent the chill plate the temperature of the substrate is reduced. In step 718 the substrate is transferred from the position adjacent the chill plate back to the position adjacent the bake plate. In step 720 the temperature of the bake plate is reduced by a second predetermined amount. Step 722 monitors the temperature of the bake plate. Step 724 repeats steps 716-722 until the temperature of the bake plate is within a predetermined tolerance of the set point temperature.

FIG. 8 is a simplified flowchart illustrating a method 800 of cooling a bake plate according to another embodiment of the invention. In step 810 a substrate is provided to be used in the cooling process. In step 812 the substrate is transferred to a position adjacent the bake plate. In step 814 a first heat transfer process is performed for a first predetermined time period which reduces the bake plate temperature by transferring thermal energy from the bake plate to the substrate. In step 816 the substrate is removed from the bake plate and the temperature of the substrate is reduced. The temperature of the substrate may be reduced by letting the substrate cool in air, forcing air over the surface of the substrate, placing the substrate on a cool surface, or any other process which reduces the temperature of the substrate. In step 818 the substrate is transferred back to the position adjacent the bake plate. In step 820 a second heat transfer process is performed for a second predetermined time period. Step 822 monitors the temperature of the bake plate. Step 824 repeats steps 816-822 until the temperature of the bake plate is within a predetermined tolerance of the set point temperature.

It should be appreciated that the specific steps illustrated in FIGS. 7 and 8 provide particular methods of cooling a bake plate according to embodiments of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in FIGS. 7 and 8 may include multiple sub-steps that may be performed in various sequences as appropriate to the individual step. Furthermore, additional steps may be added or removed depending on the particular applications. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

In some embodiments of the invention, the substrate used to cool the bake plate is made of the same material and is the same size and shape as the substrates normally processed in the tool. For example, the substrate may be a silicon wafer in a track lithography tool that is normally used to process silicon semiconductor wafers. Using a substrate of the same kind normally processed in the tool is advantageous because such substrates are generally readily available, they will not contaminate the surface of the bake plate, and they can be handled by the tool robotics without modification. Alternatively, the substrate may be composed of other materials, including the same material as the bake plate. In addition, the substrate may be of a different shape and/or thickness from that of the substrates normally processed in the tool.

Embodiments of the present invention enable a rapid reduction in the temperature of bake plate by transferring thermal energy by conduction from the bake plate to a substrate. Cooling by conduction reduces the temperature more uniformly than cooling by convection, which in turn leads to a shortened stabilization time at the new set point temperature. This further reduces the total time required to change the temperature of the bake plate between different recipes.

When a substrate is placed on a bake plate, the resulting temperature reduction of the bake plate can be approximated by the ratio of the thermal mass of the substrate to the thermal mass of the bake plate. As an example, Table 1 lists the material properties for calculating the thermal mass of a silicon wafer and an aluminum bake plate. Accordingly, the 300 mm silicon wafer in this example has a thermal mass of 84.4 J/K, and the 10 mm thick aluminum bake plate has a thermal mass of 1711.9 J/K. Thus, the ratio of the thermal mass of the silicon wafer to the thermal mass of the bake plate is approximately 0.05.

	TABLE 1
	Units	Silicon Wafer	Bake Plate
Thickness	m	0.000725	0.010000
Diameter	m	0.300	0.300
Volume	m3	0.0000512	0.0007069
Density	kg/m3	2330	2700
Weight	kg	0.119	1.909
Heat Capacity	J/kg * K	707	897
Thermal Mass	J/K	84.4	1711.9

As an example, the temperature of the bake plate in Table 1 can be reduced from 150° C. to approximately 120° C. in less than three minutes by transferring the silicon wafer between the bake plate and a chill plate four times. Table 2 shows this heat reduction process. The silicon wafer, with an initial temperature of 20° C., is first placed on the bake plate for 15 seconds. After 15 seconds, the temperature of the silicon wafer and the bake plate are both approximately 143.6° C. The silicon wafer is then transferred to the chill plate, where after 20 seconds the temperature of the silicon wafer is reduced to approximately 20° C. The wafer is then transferred back to the bake plate for a second heat transfer cycle. As shown in Table 2, after placing the silicon wafer on the bake plate five times, the temperature of the bake plate is reduced to 121.0° C. in a total of 155 seconds.

	TABLE 2
	Elapsed Time	Wafer	Bake Plate
	(sec)	Temp (C.)	Temp (C.)
Initial Temp.	0	20.0	150.0
1st Cycle on Bake Plate	15	143.6	143.6
1st Cycle on Chill Plate	35	20.0	143.6
2nd Cycle on Bake Plate	50	137.5	137.5
2nd Cycle on Chill Plate	70	20.0	137.5
3rd Cycle on Bake Plate	85	131.7	131.7
3rd Cycle on Chill Plate	105	20.0	131.7
4th Cycle on Bake Plate	120	126.2	126.2
4th Cycle on Chill Plate	140	20.0	126.2
Final Placement on Bake Plate	155	121.0	121.0

Some embodiments of the present invention provide flexibility to optimize the bake plate cooling process. For example, the substrate may be placed on the bake plate for a predetermined period of time, or the substrate may remain on the bake plate until the temperature of the bake plate is reduced by a predetermined amount as in the example shown in Table 2. If the latter method is utilized, the predetermined amount may be dependant on the temperature of the bake plate, or it may be dependant on the set point temperature.

In one embodiment, the period of time the substrate remains in contact with the bake plate can be optimized to increase the cooling rate of the bake plate. For example, Table 3 shows a cooling process using the same silicon wafer and bake plate of Table 1, but the period of time the wafer remains on the bake plate is reduced to nine seconds and the period of time the wafer remains on the chill plate is reduced to 11 seconds. The periods of time are reduced because the heat transfer rate decreases with time, and most of the heat is transferred during the first few seconds the substrate is in contact with the bake plate or chill plate. By decreasing the periods of time and increasing the number of heat transfer cycles, the overall cooling rate of the bake plate is increased. As shown in Table 3, after placing the silicon wafer on the bake plate seven times, the temperature of the bake plate is reduced from 150° C. to approximately 120.2° C. in 135 seconds.

	TABLE 3
	Elapsed Time	Wafer	Bake Plate
	(sec)	Temp (C.)	Temp (C.)
Initial Temp.	0	20.0	150.0
1st Cycle on Bake Plate	9	<144.6	144.6
1st Cycle on Chill Plate	21	>20.0	144.6
2nd Cycle on Bake Plate	30	<140.1	140.1
2nd Cycle on Chill Plate	42	>20.0	140.1
3rd Cycle on Bake Plate	51	<135.8	135.8
3rd Cycle on Chill Plate	63	>20.0	135.8
4th Cycle on Bake Plate	72	<131.7	131.7
4th Cycle on Chill Plate	84	>20.0	131.7
5th Cycle on Bake Plate	93	<127.7	127.7
5th Cycle on Chill Plate	105	>20.0	127.7
6th Cycle on Bake Plate	114	<123.9	123.9
6th Cycle on Cool Plate	126	>20.0	123.9
Final Placement on Bake Plate	135	<120.2	120.2

Advantages of the present invention include the integration of some embodiments within new or existing track lithography tools without requiring the addition or modification of hardware. Additionally, the substrate may be stored within the tool after terminating the cooling process, and the same substrate may be used in subsequent cooling processes. Also, the same substrate may be used to cool multiple bake plates within a single track lithography tool.

Based on the description of the present invention herein, a person of skill in the art will appreciate that embodiments of the invention may be beneficially used to cool a bake plate. A skilled artisan will also appreciate that some of the various bake and cool sequence sets just described have differing bake and or cool requirements. Thus, the skilled artisan will appreciate that the functional specifications of a particular bake plate and chill plate incorporated into an integrated thermal unit will depend on the material that the bake plate and chill plate are intended to heat and cool. For example, BARC materials may be adequately heated with a low temperature, low precision bake plate (e.g., a maximum 250° C., single zone heater) while photoresist materials may require a high temperature, mid-precision bake plate (e.g., a maximum 350° C., three zone heater) and the post exposure bake process may require a low temperature, high precision bake plate (e.g., a maximum 250° C., multiple zone heater). Thus, embodiments of the invention are not limited to use with any particular type of or configuration of bake plate or chill plate. Instead, generally each bake plate and chill plate is designed to particular performance standards as required by the application for which the bake plate and chill plate will be used as can be determined by a person of skill in the art.

While the present invention has been described with respect to particular embodiments and specific examples thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention. The scope of the invention should, therefore, be determined with reference to the appended claims along with their full scope of equivalents.

Claims

1. A method of reducing a temperature of a bake plate within a semiconductor processing tool, the method comprising:

(a) providing a substrate;

(b) transferring the substrate to a position adjacent the bake plate, wherein the bake plate is characterized by an initial bake plate temperature greater than a set point temperature;

(c) reducing the temperature of the bake plate by a first predetermined amount;

(d) transferring the substrate from the position adjacent the bake plate to a position adjacent a chill plate, wherein the chill plate is characterized by a chill plate temperature less than the set point temperature;

(e) transferring the substrate from the position adjacent the chill plate to the position adjacent the bake plate;

(f) reducing the temperature of the bake plate by a second predetermined amount;

(g) monitoring the temperature of the bake plate; and

(h) repeating steps (d) through (g) until the bake plate temperature is within a predetermined tolerance of the set point temperature.

2. The method of claim 1 wherein the substrate is a silicon wafer.

3. The method of claim 1 wherein the first predetermined amount depends on the bake plate temperature.

4. The method of claim 1 wherein the first predetermined amount depends on the set point temperature.

5. The method of claim 1 wherein the first predetermined amount is different than the second predetermined amount.

6. The method of claim 1 further comprising reducing the temperature of the substrate by a third predetermined amount after transferring the substrate to the position adjacent the chill plate.

7. A method of reducing a temperature of a bake plate within a track lithography tool, the method comprising:

(a) providing a substrate;

(b) transferring the substrate to a position adjacent the bake plate, wherein the bake plate is characterized by an initial bake plate temperature greater than a set point temperature;

(c) performing a first heat transfer process for a first predetermined time period to reduce the temperature of the bake plate;

(d) transferring the substrate from the position adjacent the bake plate to a position adjacent a chill plate, wherein the chill plate is characterized by a chill plate temperature less than the set point temperature;

(e) transferring the substrate from the position adjacent the chill plate to the position adjacent the bake plate;

(f) performing a second heat transfer process for a second predetermined time period to reduce the temperature of the bake plate;

(g) monitoring the temperature of the bake plate; and

(h) repeating steps (d) through (g) until the temperature of the bake plate is within a predetermined tolerance of the set point temperature.

8. The method of claim 7 wherein a duration of the first predetermined time period depends on the bake plate temperature.

9. The method of claim 7 wherein a duration of the first predetermined time period depends on the set point temperature.

10. The method of claim 7 where the duration of the first predetermined time period is different than the duration of the second predetermined time period.

11. The method of claim 7 wherein the substrate is a silicon wafer.

12. The method of claim 7 further comprising performing a third heat transfer process for a third predetermined time period to reduce the temperature of the substrate after transferring the substrate to the position adjacent the chill plate.

13. The method of claim 7 wherein the substrate in the position adjacent the bake plate is supported by proximity pins which create a gap between the substrate and the bake plate.

14. A method of cooling a bake plate, the method comprising:

(a) providing a substrate;

(b) transferring the substrate to a position adjacent the bake plate, wherein the bake plate is characterized by an initial bake plate temperature greater than a set point temperature;

(c) performing a first heat transfer process for a first predetermined time period to reduce a temperature of the bake plate;

(d) removing the substrate from the bake plate;

(e) transferring the substrate to the position adjacent the bake plate;

(f) performing a second heat transfer process for a second predetermined time period to reduce the temperature of the bake plate;

(g) monitoring the temperature of the bake plate; and

(h) repeating steps (d) through (g) until the temperature of the bake plate is within a predetermined tolerance of the set point temperature.

15. The method of claim 14 wherein a duration of the first predetermined time period depends on the bake plate temperature.

16. The method of claim 14 wherein a duration of the first predetermined time period depends on the set point temperature.

17. The method of claim 14 wherein a duration of the second predetermined time period depends on the bake plate temperature.

18. The method of claim 14 wherein determining a duration of the second predetermined time period depends on the set point temperature.

19. The method of claim 14 wherein the duration of the first predetermined time period is different than the duration of the second predetermined time period.

20. The method of claim 14 wherein the substrate is a silicon wafer.