Compiler Optimization
Provides effective use of architecture-specific instructions. There is provided a compiler including: a target partial program detecting unit for detecting, from among a partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced, so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with a target instruction sequence determined in accordance with the pattern to be replaced.
The present invention relates to a compiler, an optimization method, a compiler program, and a recording medium. In particular, the present invention relates to a compiler, an optimization method, a compiler program, and a recording medium that replace an instruction arrangement pattern that is known to be optimizable with a target instruction sequence corresponding to the arrangement pattern.
BACKGROUNDThere has been proposed a technique of detecting an instruction sequence matching a predetermined pattern from a program to be optimized and replacing the instruction sequence with another instruction sequence determined in advance in accordance with the pattern. This technique can optimize a program, for example, by replacing a sequence of instructions for performing a certain kind of processing with a single instruction producing the same processing result as the processing performed by the sequence of instructions. The instruction which replaces the sequence of instructions is, for example, a TRT instruction in the S/390 architecture provided by IBM Corporation.
The following are documents are referred to and/or considered with respect to an embodiment:
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- [Non-Patent Document 1]
- Jianghai Fu. Directed graph pattern matching and topological embedding. Journal of Algorithms, 22(2):372-391, February 1997.
- [Non-Patent Document 2]
- S. S. Muchnick. Advanced compiler design and implementation, Morgan Kaufmann Publishers, Inc., 1997.
- [Non-Patent Document 3]
- Arvind Gupta and Naomi Nishimura. Finding Largest Subtrees and Smallest Supertrees, Algorithmica, Vol. 21, No. 2, pp. 183-210, 1998
- [Non-Patent Document 4]
- http://publibz.boulder.ibm.com/epubs/pdf/dz9zr002.pdf, pp. 7-180
A TRT instruction is an instruction to scan a predetermined storage area in order from the top and output an address or the like at which a value satisfying a predetermined condition is stored (see Non-Patent Document 4).
However, it is rare that a program to be optimized completely matches a predetermined pattern. If such a match does not occur, optimization is abandoned in the conventional art. Therefore there has been a possibility of failure to effectively utilize an instruction such as a TRT instruction specific to an architecture.
It is, therefore, an object of the present invention to provide a compiler, an optimization method, a compiler program, and a recording medium as a solution to the above-described problem. This object can be attained by a combination of features described in the independent claims in the appended claims. In the dependent claims, further advantageous examples of the present invention are specified.
SUMMARY OF THE INVENTIONTo solve the above-described problem, according to a first aspect of the present invention, there is provided a compiler detecting a pattern that is to be replaced. The compiler includes multiple predetermined instructions in a program to be optimized, and replaces the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced.
The compiler has: a target partial program detecting unit for detecting, from among partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced, as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; and an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with the target instruction sequence determined in accordance with the pattern to be replaced. Thus, the present invention allows architecture-specific instructions to be used effectively.
The foregoing and other aspects of these teachings are made more evident in the following detailed description of the invention, when read in conjunction with the attached drawing figures, wherein:
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- 10 . . . Compiler
- 20 . . . Pattern to be replaced
- 30 . . . Target instruction template
- 40 . . . Partial program to be optimized
- 50 . . . Partial program to be optimized
- 60 . . . Resultant partial program
- 100 . . . Optimization candidate detecting unit
- 110 . . . Target partial program detecting unit
- 120 . . . Instruction sequence transforming unit
- 130 . . . Instruction sequence replacing unit
The present invention provides a compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized, and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, the compiler having a target partial program detecting unit for detecting, from among partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced, as a partial program to be optimized, an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced, and an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with the target instruction sequence determined in accordance with the pattern to be replaced.
It is noted that not all the necessary features of the invention are listed. Subcombinations of the features can also constitute the present invention. The present invention allows architecture-specific instructions to be used effectively.
ADVANTAGEOUS EMBODIMENTSThe present invention will be described with respect to embodiments thereof. The embodiment described below, however, is not limited the invention set forth in the appended claims, and all combinations of features described in the description of the embodiment are not necessarily indispensable to the solution according to the present invention.
The compiler 10 has an optimization candidate detecting unit 100, a target partial program detecting unit 110, an instruction sequence transforming unit 120, and an instruction sequence replacing unit 130. The optimization candidate detecting unit 100 detects a candidate for a partial program which is an object to be optimized. For example, the optimization candidate detecting unit 100 detects, in a program to be optimized, a partial program including a memory access instruction to access the same type of data as data to be accessed according to a memory access instruction included in the pattern to be replaced. The partial program may be a processing unit of the program called a method, a function or a procedure, or may be an instruction sequence such as loop processing determined on the basis of a characteristic of a control flow.
The partial program detecting unit 110 detects as a partial program 40 to be optimized a partial program similar to a pattern 20 to be replaced in multiple partial programs detected by the optimization candidate detecting unit 100. For example, the partial program detecting unit 110 detects as partial program 40 a partial program including instructions corresponding to all instructions included in the pattern 20. More specifically, the partial program detecting unit 110 determines, with respect to two instructions, that the instructions correspond to each other if the processing details according to the instructions are identical to each other, if the number of control flows output from the instructions are equal to each other, and if instructions at transition destinations of the control flows are identical to each other.
The instruction sequence transforming unit 120 transforms, in the partial program 40, instructions other than those instructions corresponding to instructions included in the pattern 20 and those instructions having execution dependencies different from the pattern to be replaced so that dependencies between instructions included in the partial program 40 match the pattern 20. The instruction sequence transforming unit 120 may transform other instructions if necessary. The transformed partial program to be optimized is set as a partial program 50 to be optimized.
The instruction sequence replacing unit 130 replaces the partial program 50 transformed by the instruction sequence transforming unit 120 with a target instruction sequence determined in accordance with the pattern 20. For example, the compiler 10 generates a target instruction sequence by replacing each variable in a target instruction template 30 showing the structure of the target instruction sequence with a corresponding variable in the partial program 50. As a result, the compiler 10 outputs as a resultant partial program 60 the program to be optimized including the target instruction sequence.
The pattern 20 may alternatively determine control dependences or data dependences between instructions. Also, the pattern 20 may be a PDG (program dependence graph) which is a dependence graph determining both control dependences and data dependences. That is, the pattern 20 may be a dependence graph having as a node each of multiple instructions included in the pattern 20 and having directed edges representing execution dependences between multiple instructions.
In this case, the instruction sequence replacing unit 130 replaces the partial program 40 with the target instruction sequence, without the partial program 40 being transformed by the instruction sequence transforming unit 120. The target partial program detecting unit 110 may detect, as well as this example of instruction sequence, as the partial program 40 to be optimized, an instruction sequence having dependences which are the same as those determined by the pattern 20 and which appear in the same recurrence phase (a completely matching sequence). Also in this case, the instruction sequence replacing unit 130 replaces the partial program 40 with the target instruction sequence, without the partial program 40 being transformed by the instruction sequence transforming unit 120.
In this case, the instruction sequence transforming unit 120 changes the order of execution of the instructions in the partial program 40 on the basis of the dependences on condition that the results of processing by the partial program 40 are not changed after changing the order of execution of the instructions in the partial program 40. More specifically, the instruction sequence transforming unit 120 interchanges the positions of the instruction B and the instruction C in the execution order if the instruction B does not depend on the result of processing according to the instruction C. The partial program 50 is thereby produced. The instruction sequence replacing unit 130 replaces the partial program 50 changed in instruction execution order, with the target instruction sequence.
In this case, the instruction sequence transforming unit 120 makes a transformation such that the additional instruction is executed out of the loop processing, on condition that the result of execution of the additional instruction included in the loop processing of the partial program 40 is constant independently of repetition of the loop processing. Alternatively, the instruction sequence transforming unit 120 may divide the loop processing of the partial program 40 into two loop processings in which the additional instruction and the instruction sequence other than the additional instruction are respectively executed. Division of loop processing will not be described since it is well known from Non-Patent Document 2. The instruction sequence replacing unit 130 replaces the loop processing from which the additional instruction has been removed with the target instruction sequence.
For example, the instruction sequence transforming unit 120 generates as instruction C−1before a save instruction to save, before the instruction C, the value in a storage area in which the result of processing according to the instruction C is stored. The instruction sequence transforming unit 120 also generates as instruction C−1after a recovery instruction to recover the value in the storage area after execution of the instruction C.
Preferably, the target partial program detecting unit 110 computes, with respect to each of partial programs, an estimate of the processing time increased in a case where an absent instruction and a save instruction or the like to the partial program. The target partial program detecting unit 110 also computes an estimate of the reduced processing time in a case where the partial program is replaced with the target instruction sequence by the instruction sequence replacing unit 130. The target partial program detecting unit 110 then detects the partial program as the partial program to be optimized, if the increased processing time is shorter than the reduced processing time, thus optimizing only the portion transformable to improve the efficiency.
Further, for example, in a case where a comparison instruction included in the pattern 20 and a comparison instruction included in the partial program 40 differ only in a variable to be compared, the instruction sequence transforming unit 120 may change only a constant, with which the variable is to be compared, in the comparison instruction included in the partial program 40. For example, in a case where the pattern 20 includes an instruction “switch(ch)” and the partial program 40 includes an instruction “switch(ch+1)”, the instruction sequence transforming unit 120 makes a transformation by reducing 1 from a constant of a case statement in the partial program 40. The instruction sequence transforming unit 120 transforms the instruction “switch(ch+1)” in the partial program 40 into the instruction “switch(ch)”. Consequently, the instruction sequence replacing unit 130 can match the instruction included in the partial program 40 to the pattern 20.
For example, in a case where the pattern 20 includes a load instruction, the optimization candidate detecting unit 100 determines that a partial program is a candidate to be optimized, on condition that the partial program includes the load instruction. Similarly, in a case where the pattern 20 includes a store instruction, the optimization candidate detecting unit 100 determines that a partial program is a candidate to be optimized, on condition that the partial program includes the store instruction. Types of data to be accessed include types indicating kinds of data (an array variable, an instance variable, and a class variable) as well as “byte”, “int”, “float” and “double” which are types indicating ranges of data expression.
In a case where the pattern 20 includes loop processing, the optimization candidate detecting unit 100 detects a partial program including loop processing as a candidate for a partial program to be optimized. The loop processing is an instruction sequence corresponding to strongly connected components in a case where the program is expressed as a control flow graph. Also, the optimization candidate detecting unit 100 detects a partial program as a candidate to be optimized, further on condition that the partial program includes loop processing having the same increment in a loop induction variable as that in the loop processing included in the pattern 20.
Also, the optimization candidate detecting unit 100 may detect a partial program as a candidate to be optimized, further on condition that the loop processing is repeated a number of times equal to or larger than a predetermined reference number of times. The above-described processing narrows down the range in which optimization is tried, thus reducing the processing time required for compilation. As a result, the facility with which the technique described with respect to this embodiment is applied to a dynamic compiler such as a just-in-time compiler.
Preferably, in a case where an optimization level indicating the degree of optimization needed by a user is set, the optimization candidate detecting unit 100 changes, according to the optimization level, a criterion for detection of a candidate to be optimized. For example, in a case where a higher optimization level is set, the optimization candidate detecting unit 100 detects a larger number of partial programs as a candidate to be optimized in comparison with that in a case where a lower optimization level is set. Further, the optimization candidate detecting unit 100 may omit processing in S400, for example, depending on a setting made by the user.
Subsequently, the target partial program detecting unit 110 detects, as a partial program to be optimized, a partial program including instructions corresponding to all the instructions included in the pattern 20 in the partial programs detected as a candidate to be optimized (S410). A concrete example of this processing will be described with respect to a case where the pattern 20 includes loop processing. The target partial program detecting unit 110 determines the correspondence between instructions with respect to instructions in the loop processing and makes no determination as to coincidence between dependences. On the other hand, the target partial program detecting unit 110 determines not only the correspondence between instructions but also the coincidence between dependences with respect to instructions out of the loop processing.
That is, if the target partial program detecting unit 110 determines, with respect to each of the partial programs, that the partial program includes in the loop processing the instructions corresponding to all the instructions included in the loop processing, and that all the instructions out of the loop processing in the partial program conform to the dependences determined by the pattern 20, it detects the partial program as a program to be optimized. In this way, loops etc. having the same dependences but differing in recurrence phase can be suitably detected.
Description will be made of further details. The target partial program detecting unit 110 first generates a dependence graph in which each of multiple instructions included in each of the partial programs is set as a node and execution dependences between multiple instructions are represented by directed edges. The target partial program detecting unit 110 then makes a determination as to correspondence in the form between the generated dependence graph and the dependence graph indicating the pattern 20, by means of an algorithm for determination as to graph form correspondence.
The target partial program detecting unit 110 may detect the same type of dependence graph as the pattern 20, for example, by the topological embedding technique described in Non-Patent Document 1. Alternatively, the target partial program detecting unit 110 may detect the dependence graph corresponding in form to the pattern 20, by detecting a piece of program having the largest common portion in common with the pattern 20 on the basis of the method described in Non-Patent Document 2. Each of these techniques allows determination of correspondence in the form even in a case where an arbitrary node is included between the nodes in the dependence graph of the pattern 20. Therefore, the instruction sequence shown in
Also, the dependence graph with respect to loop processing is handled as a tree structure extending infinitely. Then, with respect to (b), A->B->C->D->A->B->C-> . . . is determined to find correspondence in the form. With respect to (c), the loop is developed to obtain A->C->B->D->A->C->B->D->A . . . . This algorithm allows an arbitrary node to be included between the nodes, as mentioned above. Thus, the underlined portions are connected to A->B->C->D. Therefore, correspondence in the form to the pattern is also determined with respect to this structure.
Thus, when the target partial program detecting unit 110 determines, with respect each of the partial programs, that the instructions in the partial program corresponding to all the instructions included in the pattern 20 are executed in the execution order designated by the execution dependences between the instructions in the pattern 20, it can detect the partial program as a partial program to be optimized. In this way, each of the instruction sequences shown in
The topological embedding technique may be extended by a method described below to enable the target partial program detecting unit 110 to detect the instruction sequence shown in
Each time the absence of one of the nodes is detected, the target partial program detecting unit 110 records information for identification of the node to obtain a set of absent nodes. As a result, the target partial program detecting unit 110 can compute the proportion of the instructions in the partial program corresponding to the other instructions included in the pattern 20 in all the instructions included in the pattern 20. Further, by means of this algorithm, the target partial program detecting unit 110 can detect an instruction sequence having two or more of the characteristics shown in
Subsequently, the instruction sequence transforming unit 120 transforms, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern 20 and those instructions having execution dependencies different from the pattern 20 so that dependencies between instructions included in the partial program 40 match the pattern 20 S420). The instruction sequence replacing unit 130 replaces the transformed partial pattern 50 with the target instruction sequence determined in accordance with the pattern to be replaced (S430). It is not necessarily possible that all instruction sequences detected by the target partial program detecting unit 110 will be replaced with target instruction sequences. That is, in some cases, the instruction sequence transforming unit 120 fails to transform the partial program 40 and the instruction sequence replacing unit 130 fails to replace the instruction sequence.
Four examples of a process in which the compiler 10 is supplied with a program to be optimized and optimizes the program will be described successively.
FIRST EXAMPLEThe pattern 20 is a pattern to be replaced for detection of an instruction sequence shown in
Then, the target partial program detecting unit 110 detects partial programs to be optimized by using the illustrated pattern 20. This pattern 20 has, with respect to a multiple-branch instruction (e.g., switch instruction (2)) to hand over control to an external instruction out of the pattern 20 in a case where one of multiple conditions is satisfied, a representative edge representative of multiple control flows through which control is handed over from the multiple-branch instruction to the external instruction.
The target partial program detecting unit 110 determines that a partial program includes the corresponding multiple-branch instruction, if the dependence graph showing control flows of the partial program has an edge corresponding to the representative edge. That is, the target partial program detecting unit 110 determines that the multiple-branch instructions correspond to each other, on condition that the number of edges of the multiple-branch instruction of the partial program is larger than the number of edges of the multiple-branch instruction of the pattern 20.
In the target instruction sequence template 30, a variable “bytearray” represents an address in a storage area in which a value with which comparison is made is stored by a TRT instruction. A variable “i” represents an index for scanning the storage area. The instruction sequence replacing unit 130 secures the storage area for storing a number of values equal to the value of the variable “bytearray”, and stores in a variable “table” the address stored in the storage area. For example, when the value of index i in the “bytearray” storage area satisfies a condition for termination of the loop, the value of index i in the “table” storage area is a non-zero value.
As is apparent from comparison between this figure and
In contrast, the compiler 10 in this embodiment is capable of detecting correspondence between instruction (1) in
The instruction sequence transforming unit 120 obtains a detection result showing that instruction (b) and instruction (c) are successively executed and that instructions (b) and (c) are transformable into instruction (2) in
As is apparent from this processing, the instruction sequence replacing unit 130 can optimize the instruction sequence if determination as to whether or not the loop processing is terminated is made on the basis of the value of index i. Therefore, the target partial program detecting unit 110 may detect a partial program as the partial program 40, on condition that determination as to whether or not the loop processing is terminated is made on the basis of the value of index i, even in a case where the partial program and the pattern 20 have different switch instruction references. For example, in a case where a partial program includes an instruction “switch” (map1 [ch]), the target partial program detecting unit 110 may detect the partial program as the partial program 40, on condition that the array variable map1 corresponds to a constant array.
Processing in accordance with the resultant partial program 60 will be described. According to a while instruction (3) and a TRT instruction (5) in the resultant partial program 60, the computer scans on a 256 byte basis the storage area determined by the variable “data”. The TRT instruction (5) can be executed at an extremely high speed in comparison with the process in which loop processing is repeated 256 times. Therefore, the speed of scanning of the storage area determined by the variable “data” can be increased. For example, in a case where 0 or GREATERTHAN is stored within initial 256 bytes in the storage area, instructions (1) to (9) are executed in this order. Thus, loop processing is not executed and, therefore, the efficiency is markedly high.
According to the first example, as described above, the instruction sequence replacing unit 130 can replace processing realized by two or more instructions such as a while instruction and a switch instruction with a TRT instruction which is one instruction for performing the same processing as that performed by multiple instructions.
As a modification of the first example, a case is conceivable in which the pattern 20 includes a nullcheck instruction for determining whether or not the value of the variable “bytearray” is null. For example, the nullcheck instruction is ordinarily used immediately before execution of instruction (1) each time instruction (1) is executed. The nullcheck instruction is used for the purpose of preventing readout of the value from an invalid address by instruction (1).
The value of byte array is constant independently of repetition of the loop. Therefore the result of execution of the nullcheck instruction is the same independently of repetition of the loop. In such a case, the instruction sequence transforming unit 120 executes the nullcheck instruction out of the loop processing and, therefore, the instruction sequence replacing unit 130 can replace the loop processing from which the nullcheck instruction has been removed with a target instruction sequence.
SECOND EXAMPLEIn the partial program 40, loop processing has two induction variables: the variable “offset” and a variable “count”. That is, the partial program 40 and the pattern 20 shown in
According to the compiler 10 in this embodiment, the target partial program detecting unit 110 can detect a partial program as the partial program 40 even if the partial program has an additional instruction in comparison with the pattern 20. More specifically, the target partial program detecting unit 10 can obtain a detection result showing that instruction (1) in
In this case, the instruction sequence transforming unit 120 generates new loop processing to execute an additional instruction. Consequently, the instruction sequence replacing unit 130 can replace instructions other than the additional instruction in the program to be optimized with a target instruction sequence. The compiler 10 may further optimize the newly generated loop processing. That is, the compiler 10 can optimize the newly generated loop processing into processing for computing the value of the variable “count” from the value of the variable “offset”.
Processing in accordance with the resultant partial program 60 will be described. According to a while instruction (3) and a TRT instruction (5) in the resultant partial program 60, the computer scans on a 256 byte basis the storage area determined by the variable “bytes”. The TRT instruction (5) can be executed at an extremely high speed in comparison with the process in which loop processing is repeated 256 times. Therefore, the speed of scanning of the storage area determined by the variable “bytes” can be increased. For example, in a case where a negative value is stored within initial 256 bytes in the storage area, instructions (1) to (9) are executed in this order. Thus, loop processing is not executed and, therefore, the efficiency is markedly high.
THIRD EXAMPLEIn the partial program 40, loop processing has two induction variables: the variable “offset” and a variable “count”. That is, the partial program 40 and the pattern 20 shown in
According to the compiler 10 in this embodiment, the target partial program detecting unit 110 can detect a partial program as the partial program 40 even if the partial program has an additional instruction in comparison with the pattern 20. Accordingly, the instruction sequence transforming unit 120 divides the loop processing of the partial program 40 into two loop processings in which the additional instruction and the instruction sequence other than the additional instruction are respectively executed.
The XC instruction is capable of initializing a storage area of a size designated by a constant operand. For example, instruction (1) is an XC instruction for initializing a storage area of a constant size of 256 bytes. Further, according to the EXECUTE instruction in accordance with S/390 provided by IBM Corporation, a value designated by a constant operand can be changed during execution of a program (see pp. 7-108 of Non-Patent Document 4). Thus, the XC instruction is substantially capable of initializing a storage area of a size designated by a register. For example, instruction (3) in this figure represents an XC instruction such that a constant operand which designates the size of a storage area to be initialized is changed to the value of a variable T_inccount by the EXECUTE instruction.
FOURTH EXAMPLEIt can be understood that, as shown in the figure, the efficiency of execution of the program can be improved by optimization in a case where eight or more data items on average are scanned. That is, for example, the compiler 10 may select and optimize only loop processing highly probable to scan eight or more data items to improve the efficiency of execution of the entire program.
The host controller 1082 connects the RAM 1020, and the CPU 1000 and the graphic controller 1075, which access the RAM 1020 at a high transfer rate. The CPU 1000 operates on the basis of programs stored in the BIOS 1010 and the RAM 1020, and controls each component. The graphic controller 1075 obtains image data generated, for example, by the CPU 1000 on a frame buffer provided in the RAM 1020, and displays the image data on a display device 1080. Alternatively, the graphic controller 1075 may contain therein a frame buffer for storing image data generated by the CPU 1000 for example.
The input/output controller 1084 connects the host controller 1082, the communication interface 1030, which is an input/output device of a comparatively high speed, the hard disk drive 1040 and the CD-ROM drive 1060. The communication interface 1030 performs communication with an external unit via a network. The hard disk drive 1040 stores programs and data used by the computer 500. The CD-ROM drive 1060 reads a program or data from a CD-ROM 1095 and provides the read program or data to the input/output chip 1070 via the RAM 1020.
To the input/output controller 1084, the BIOS 1010 and input/output devices of a comparatively low speed, i.e., the flexible disk drive 1050 and the input/output chip 1070 or the like are also connected. The BIOS 1010 stores programs including a boot program executed by the CPU 1000 at the time of startup of the computer 500 and programs dependent on the hardware of the computer 500. The flexible disk drive 1050 reads a program or data from a flexible disk 1090 and provides the read program or data to the input/output chip 1070 via the RAM 1020. The input/output chip 1070 connects the flexible disk 1090 and various input/output devices, for example, through a parallel port, a serial port, a keyboard port, a mouse port, etc.
A program provided to the computer 500 is provided by a user in a state of being stored on a recording medium, such as the flexible disk 1090, the CD-ROM 1095, or an IC card. The program is read out from the recording medium, installed in the computer 500 via the input/output chip 1070 and/or the input/output controller 1084, and executed in the computer 500. Operations which the computer 500 is made by the this program, e.g., the compiler program to perform are the same as the operations in the computer 500 described above with reference to
The above-described program may be stored on an external storage medium. As the recording medium, an optical recording medium such as a DVD or a PD, a magneto-optic recording medium such as an MD, a tape medium, a semiconductor memory such as an IC card, or the like can be used as well the flexible disk 1090 and the CD-ROM 1095. Also, a storage device such as a hard disk, a RAM or the like provided in a server system connected to a special-purpose communication network or the Internet may be used as the recording medium to provide the program to the computer 500 via the network.
While the present invention has been described with respect to the embodiment thereof, the technical scope of the present invention is not limited to the scope described above with respect to the embodiment. It is apparent to those skilled in the art that various changes and medications can be made in the above-described embodiment. It is apparent from the description in the appended claims that other embodiments of the invention provided by making such changes and modifications are also included in the technical scope of the present invention.
Variations described for the present invention can be realized in any combination desirable for each particular application. Thus particular limitations, and/or embodiment enhancements described herein, which may have particular advantages to a particular application need not be used for all applications. Also, not all limitations need be implemented in methods, systems and/or apparatus including one or more concepts of the present invention.
The present invention can be realized in hardware, software, or a combination of hardware and software. A visualization tool according to the present invention can be realized in a centralized fashion in one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system—or other apparatus adapted for carrying out the methods and/or functions described herein—is suitable. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which—when loaded in a computer system—is able to carry out these methods.
Computer program means or computer program in the present context include any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after conversion to another language, code or notation, and/or reproduction in a different material form.
Thus the invention includes an article of manufacture which comprises a computer usable medium having computer readable program code means embodied therein for causing a function described above. The computer readable program code means in the article of manufacture comprises computer readable program code means for causing a computer to effect the steps of a method of this invention. Similarly, the present invention may be implemented as a computer program product comprising a computer usable medium having computer readable program code means embodied therein for causing a function described above. The computer readable program code means in the computer program product comprising computer readable program code means for causing a computer to effect one or more functions of this invention. Furthermore, the present invention may be implemented as a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for causing one or more functions of this invention.
It is noted that the foregoing has outlined some of the more pertinent objects and embodiments of the present invention. This invention may be used for many applications. Thus, although the description is made for particular arrangements and methods, the intent and concept of the invention is suitable and applicable to other arrangements and applications. It will be clear to those skilled in the art that modifications to the disclosed embodiments can be effected without departing from the spirit and scope of the invention. The described embodiments ought to be construed to be merely illustrative of some of the more prominent features and applications of the invention. Other beneficial results can be realized by applying the disclosed invention in a different manner or modifying the invention in ways known to those familiar with the art.
Claims
1) An optimizing compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the pattern to be replaced, comprising:
- a target partial program detecting unit for detecting, from among a partial programs of said program to be optimized, a partial program including instructions corresponding to all instructions included in said pattern to be replaced as a partial program to be optimized;
- an instruction sequence transforming unit for transforming, in said partial program to be optimized, instructions other than those instructions corresponding to instructions included in said pattern to be replaced and those instructions having execution dependencies different from said pattern to be replaced, so that dependencies between instructions included in said partial program to be optimized match said pattern to be replaced; and
- an instruction sequence replacing unit for replacing said partial program to be optimized transformed by said instruction sequence transforming unit with a target instruction sequence determined in accordance with said pattern to be replaced.
2) The compiler according to claim 1, wherein said target partial program detecting unit detects each of the partial programs as the partial program to be optimized, if the instructions in the partial program corresponding to all the instructions included in said pattern to be replaced are executed in the order designated by the execution dependencies between the instructions in said pattern to be replaced.
3) The compiler according to claim 2, wherein in a case where said pattern to be replaced includes loop processing, said target partial program detecting unit detects each of the partial programs as the partial program to be optimized, if the partial program includes in loop processing the instructions corresponding to all the instructions included in said loop processing, and if all the instructions out of the loop processing in the partial program conform to the dependencies determined by said pattern to be replaced.
4) The compiler according to claim 1, wherein said pattern to be replaced is a dependence graph having as a node each of multiple instructions included in the said pattern to be replaced and having directed edges representing the execution dependencies between multiple instructions, and
- wherein said target partial program detecting unit generates, with respect to each of the partial programs, a dependence graph having as a node each of multiple instructions included in the partial program and having directed edges representing the execution dependencies between multiple instructions, and makes a determination on the basis of the dependence graph and a dependence graph representing said pattern to be replaced as to whether or not the partial program should be detected as the partial program to be optimized.
5) The compiler according to claim 4, wherein said pattern to be replaced indicate control flows between the instructions,
- wherein the dependence graph of said pattern to be replaced has, with respect to a multiple-branch instruction to hand over control to an external instruction out of said pattern to be replaced in a case where one of multiple conditions is satisfied, a representative edge representative of multiple control flows through which control is handed over from the multiple-branch instruction to the external instruction, and
- wherein said target partial program detecting unit determines, with respect to each of multiple partial programs, that the partial program includes the corresponding multiple-branch instruction, if the dependence graph showing control flows of the partial program has an edge corresponding to the representative edge.
6) The compiler according to claim 1, further comprising an optimization candidate detecting unit which detects, in the program to be optimized, as a candidate for the partial program to be optimized, the partial program including a memory access instruction to access the same type of data as data to be accessed according to a memory access instruction included in said pattern to be replaced,
- wherein said target partial program detecting unit detects the partial program to be optimized in the partial programs detected by said optimization candidate detecting unit.
7) The compiler according to claim 1, further comprising an optimization candidate detecting unit which detects, in the program to be optimized, as a candidate for the partial program to be optimized, the partial program including loop processing having the same increment in a loop induction variable as that in loop processing included in said pattern to be replaced,
- wherein said target partial program detecting unit detects the partial program to be optimized in the partial programs detected by said optimization candidate detecting unit.
8) The compiler according to claim 1, further comprising an
- optimization candidate detecting unit which detects, in the program to be optimized, as a candidate for the partial program to be optimized, the partial program including loop processing repeatedly performed a number of times equal to or larger than a predetermined reference number of times,
- wherein said target partial program detecting unit detects the partial program to be optimized in the partial programs detected by said optimization candidate detecting unit.
9) The compiler according to claim 1, wherein said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including in loop processing an additional instruction which does not correspond to any of the instructions included in said pattern to be replaced,
- wherein said instruction sequence transforming unit executes the additional instruction out of the loop processing of the partial program to be optimized, on condition that the result of execution of the additional instruction included in the loop processing is constant independently of repetition of the loop processing, and
- wherein said instruction sequence replacing unit replaces the loop processing from which the additional instruction has been removed with the target instruction sequence.
10) The compiler according to claim 1, wherein said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including in loop processing an additional instruction which does not correspond to any of the instructions included in said pattern to be replaced,
- wherein said instruction sequence transforming unit divides the loop processing of the partial program to be optimized into two loop processes in which the additional instruction and the instruction sequence other than the additional instruction are respectively executed, and
- wherein said instruction sequence replacing unit replaces the instruction sequence other than the additional instruction with the target instruction sequence.
11) The compiler according to claim 1, wherein said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including an instruction sequence executed in an order different from that of the execution dependencies in said pattern to be replaced,
- wherein said instruction sequence transforming unit changes, on the basis of the execution dependencies, the order of execution of the instruction in the partial program to be optimized, on condition that the result of processing of the partial program to be optimized is not changed even if the order of execution of the instructions in the partial program to be optimized is changed, and
- wherein said instruction sequence replacing unit replaces the partial program to be optimized in which the instruction execution order has been changed with the target instruction sequence.
12) The compiler according to claim 1, wherein if one of the partial programs lacks some of the instructions included in said pattern to be replaced, said target partial program detecting unit detects the partial program as the partial program to be optimized, on condition that the proportion of the instructions in the partial program corresponding to the other instructions included in said pattern to be replaced in all the instructions included in said pattern to be replaced is equal to or higher than a predetermined reference proportion.
13) The compiler according to claim 12, wherein said instruction sequence transforming unit adds to the partial program to be optimized the absent instruction absent in the instructions in the partial program to be optimized corresponding to all the instructions included in said pattern to be replaced, generates a cancel instruction to return the result of processing of the program to be optimized changed by the addition of the absent instruction to the processing result obtained in the case where the absent instruction is not added, and executes the cancel instruction out of the partial program to be optimized, and
- wherein said instruction sequence replacing unit replaces the partial program to be optimized including the added instruction that has been absent with the target instruction sequence.
14) The compiler according to claim 13, wherein said instruction sequence transforming unit generates as the cancel instruction a save instruction to save, before the absent instruction, the value in a storage area in which the result of processing according to the absent instruction is stored, and a recovery instruction to recover the value saved in the storage area after execution of the absent instruction, and executes the save instruction and the recovery instruction out of the partial program to be optimized.
15) The compiler according to claim 12, wherein said target partial program detecting unit detects each of the partial programs as the partial program to be optimized, if the processing time increased in a case where the instruction absent in the partial program in comparison with said pattern to be replaced is added to the partial program is shorter than the reduced processing time in a case where the partial program is replaced with the target instruction sequence by said instruction sequence transforming unit.
16) The compiler according to claim 1, wherein said instruction sequence replacing unit comprises a limitation selected from a group of limitations consisting of:
- said instruction sequence replacing unit generates the target instruction sequence by replacing each of variables in the target instruction template showing the structure of the target instruction with a variable in the partial program to be optimized corresponding to the variable in the target instruction template;
- said instruction sequence replacing unit replaces two or more of the instructions of the partial program to be optimized with one instruction for performing the same processing as that according to the two or more instructions;
- said instruction sequence replacing unit replaces an instruction sequence for processing based on an algorithm requiring a longer processing time with an instruction sequence for processing based on a different algorithm requiring a shorter processing time; and
- any combination of these limitations.
17) A computer program product comprising a computer usable medium having computer readable program code means embodied therein for causing functions of an optimizing compiler, the computer readable program code means in said computer program product comprising computer readable program code means for causing a computer to effect the functions of claim 1.
18) An optimization method for optimizing a program to be optimized detecting, from a program to be optimized, a pattern that is to be replaced and includes multiple predetermined instructions and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with said instruction sequence to be replaced, comprising:
- a target partial program detecting step of detecting a partial program as said target partial program to be optimized if it is determined that instructions in said partial program that correspond to all instructions included in said pattern to be replaced are executed in an execution order indicated by execution dependencies between instructions in said pattern to be replaced; and
- an instruction sequence replacing step of replacing said partial program to be optimized with a target instruction sequence determined in accordance with said pattern to be replaced.
19) A compiler detecting, from a program to be optimized, a pattern that is to be replaced and includes multiple predetermined instructions and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with said pattern to be replaced, comprising:
- a target partial program detecting unit for detecting a partial program as said target partial program to be optimized if it is determined that instructions in said partial program that correspond to all instructions included in said pattern to be replaced are executed in an execution order indicated by execution dependencies between instructions in said pattern to be replaced; and
- an instruction sequence replacing unit for replacing said partial program to be optimized with a target instruction sequence determined in accordance with said pattern to be replaced.
20) The compiler according to claim 19, wherein in a case where said pattern to be replaced determines dependencies recurring among the instructions, said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including an instruction sequence having the same dependencies as those determined by said pattern to be replaced but differing in recurrence phase, and
- wherein said instruction sequence replacing unit replaces the partial program to be optimized with the target instruction sequence.
21) An optimization method for detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, comprising:
- a target partial program detecting step of detecting, from among a partial programs of said program to be optimized, a partial program including instructions corresponding to all instructions included in said pattern to be replaced as a partial program to be optimized;
- an instruction sequence transforming step of transforming, in said partial program to be optimized, instructions other than those instructions corresponding to instructions included in said pattern to be replaced and those instructions having execution dependencies different from said pattern to be replaced, so that dependencies between instructions included in said partial program to be optimized match said pattern to be replaced;
- an instruction replacing step of replacing said partial program to be optimized transformed by said instruction sequence transforming unit with a target instruction sequence determined in accordance with said pattern to be replaced.
22) An article of manufacture comprising a computer usable medium having computer readable program code means embodied therein for causing detection by a compiler, the computer readable program code means in said article of manufacture comprising computer readable program code means for causing a computer to effect the steps of claim 19.
23) A compiler program for causing a computer to function as a compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, said compiler program causing said computer as:
- a target partial program detecting unit for detecting, from among a partial programs of said program to be optimized, a partial program including instructions corresponding to all instructions included in said pattern to be replaced as a partial program to be optimized;
- an instruction sequence transforming unit for transforming, in said partial program to be optimized, instructions other than those instructions corresponding to instructions included in said pattern to be replaced and those instructions having execution dependencies different from said pattern to be replaced, so that dependencies between instructions included in said partial program to be optimized match said pattern to be replaced;
- an instruction sequence replacing unit for replacing said partial program to be optimized transformed by said instruction sequence transforming unit with a target instruction sequence determined in accordance with said pattern to be replaced.
24) A compiler program for causing a computer to function as a compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, said compiler program causing said computer as:
- a target partial program detecting unit for detecting a partial program as said target partial program to be optimized if it is determined that instructions in said partial program that correspond to all instructions included in said pattern to be replaced are executed in an execution order indicated by execution dependencies between instructions in said pattern to be replaced; and
- an instruction sequence replacing unit for replacing said partial program to be optimized with a target instruction sequence determined in accordance with said pattern to be replaced.
25) A recording medium on which the compiler program according to claim 23 is recorded.
Type: Application
Filed: Jul 3, 2008
Publication Date: Jan 1, 2009
Inventors: Motohiro Kawahito (Sagamihara-shi), Hideaki Komatsu (Yokohama-shi)
Application Number: 12/167,421
International Classification: G06F 9/45 (20060101);