Abstract: Reducing power consumption in an electronic device can include analyzing device usage data associated with the device to predict an extended period of user inactivity, the usage data including at least one of historical usage data and present usage signals and entering an enhanced reduced power state by implementing one or more power saving optimizations for at least a portion the extended period of extended user inactivity, the one or more power saving optimizations slowing, delaying, or interrupting one or more normal activities normally performed by the device. The method can further include exiting the enhanced reduced power state by suspending the one or more power saving optimizations. Exiting the enhanced reduced power state can be performed in response to at least one of: user activity; a specified user routine; or a time predicted by the analyzing device usage data.

Abstract: Disclosed are a graph instruction processing method and apparatus, which relates to the field of computer technologies One example method includes: detecting whether a first graph instruction has a conditional instruction element; and when the first graph instruction has the conditional instruction element, determining that the first graph instruction is a conditional execution instruction, and processing the first graph instruction when both data flow information and control flow information of the first graph instruction are in a ready state; or when the first graph instruction does not have a conditional instruction element, determining that the first graph instruction is a non-conditional execution instruction, and processing the first graph instruction when data flow information of the first graph instruction is in a ready state.

Abstract: Apparatuses, systems, and techniques to receive, by a processor of a computer system, one or more operations for a kernel; automatically generate, by the processor, one or more operators that perform the one or more operations on elements of one or more input data structures; and automatically generate, by the processor, the kernel that comprises the one or more operators.

Abstract: A multi-core architecture in some examples may have hundreds of “cores”, each core comprising a digital signal processor (DSP) and various functional computing units. A method of implementing a multi-core graph compiler for a system-on-chip (SOC) having a data processing engine (DPE) array is disclosed herein. An Adaptive Intelligence Engine (AIE) compiler is one example of a multi-core graph compiler. An compiler is used to mitigate performance degradation due to memory stalls (collisions) when executing an AIE compiler-accelerated application on an AI Engine. The method disclosed here addresses phase order issues to mitigate the memory collisions.

Abstract: Systems and methods are disclosed for selecting parameters for use by a system. The parameters can describe a behavior of the system, which can be represented by a model having an input and an output. The model can include an operation representable by a matrix. The parameters can include the input and output ranges of the operation, the dimensions of the matrix, a noise value for the system, an overflow probability, a regularization parameter, and a desired number of accurate digits. A design environment can be configured to determine values or ranges of values for one or more of the parameters based on values or ranges of values of the remaining parameters. In some embodiments, the design environment can select, recommend, or validate a choice of datatype, minimum system noise, or the dimensions of the matrix. The model can be used to generate code, which can be used to configure the system to perform the operation.

Abstract: According to some embodiments, methods and systems may include a package manager chart file repository storing charts associated with a container orchestration system. A package manager platform, coupled to the package manager chart file repository, may access a first parent chart from the package manager chart file repository and determine that the first parent chart includes a dependency manifest. The package manager platform may then construct a Directed Acyclic Graph (“DAG”) based on the dependency manifest. Container orchestration system objects, including those associated with sub-charts of the first parent chart, may then be deployed in accordance with a topological ordering of the DAG.

Abstract: Compilation is supported and improved by varying the order of invocation of register allocation heuristics during code generation. A particular invocation order may be chosen based on one or more compilation scenario properties, such as a target processor architecture, a target operating system, a kind of source code being compiled, or optimization targets for the compiler or the generated code, or a mix thereof. Suitable heuristics invocation orders may be produced efficiently and effectively using a genetic algorithm that is adapted to make a population of invocation orders, select parents, create offspring, and assess invocation order fitness, until the population converges on optimal orders. Invocation order fitness assessments may be based on actual performance or simulated performance.

Abstract: Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected.

Abstract: An embodiment searches source for callable units, and scans the contents of the callable units, and generates a set of unit groups that each include one or more of the callable units. The embodiment preprocesses the callable units and then generates hashes of each of the callable units. The embodiment generates a data structure comprising unit identifiers associated with the hashes and their corresponding callable units. The embodiment generates statistical data using a callable-unit metric and updates the data structure by prioritizing the callable units based on the statistical data. The embodiment compares hashes of the callable units and identifies first and second callable units as redundant callable units. The embodiment updates the data structure by identifying the second callable unit as being redundant to the first callable unit. The embodiment generates a report of redundant callable units based on the data structure.

Abstract: Provided are systems and methods for creating and managing an interactive process graphs which expedite performance of a multi-user enterprise process between user interfaces and the underlying systems. In one example, a method may include generating a process graph of a user interface process, wherein the process graph comprises nodes corresponding to activities and vertices between the nodes identifying dependencies among the activities, embedding input fields in the nodes of the process graph, embedding, via the process graph, an identifier of a current location of a data object within an instance within the user interface process, and displaying an instance of the process graph corresponding to the instance of the user interface process which includes the embedded input fields in the nodes and the identifier of the current location of the data object within the instance of the user interface process.

Abstract: Provided is a non-transitory computer-readable recording medium storing a function generation program that causes a computer to execute a process, the process including referring to a storage unit that stores instruction information about an instruction to generate a first function that corresponds to the instruction and receives one or more arguments representing one or more operands of the instruction, generating first code inside the first function, where the first code calls a second function that returns machine language representing a process executed by the instruction for the one or more operands represented by the one or more arguments, and generating second code inside the first function, where the second code writes the machine language in a memory.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a memory access command; determining a physical address associated with the memory access command; determining a plane of a die on the memory device that is referenced by the physical address; inserting the memory access command into a queue associated with the plane; and processing the memory access command from the queue.

Abstract: A method including transmitting, by a network device to a security device, an initial security instruction set including a plurality of initial security instructions associated with operation of the security device; transmitting, by the network device to the security device, an event signal associated with the security device carrying out the network-facing operation; receiving, by the network device from the security device based on transmitting the event signal, a security instruction associated with the security device carrying out the network-facing operation, the security instruction being from among the plurality of initial security instructions; translating, by the network device, the security instruction into a host instruction to be executed by the network device; and transmitting, by the network device to the security device based on executing the translated host instruction, communication information to enable the security device to carry out the network-facing operation is disclosed.

Abstract: The present disclosure relates to a non-transitory computer-readable recording medium storing an analysis program that causes a computer to execute a process. The process includes sampling an instruction address of one of instructions included in a program during execution of the program, identifying a first function that includes the sampled instruction address in an address range, rewriting mark information associated with the identified first function, identifying first information corresponding to the instruction address of the first function among a plurality of first information based on the rewritten mark information, identifying second information corresponding to the instruction address of the first function among a plurality of second information based on the rewritten mark information, storing the first information and the second information in a memory, and analyzing performance of the program based on the first information and the second information stored in the memory.

Abstract: An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.

Abstract: A computer-based method of an application startup includes: in response to an instruction to perform a reading processing configured to load an application program, determining whether an analysis result of an annotation included in a source code of the application program is stored in a storage device being non-volatile; and in response to a determination that the analysis result is stored in the storage device, starting the application program by using the analysis result stored in the storage device without executing an analysis processing of the annotation.

Abstract: A method is disclosed to ensure that components in a complex system are correctly connected together. In one embodiment, such a method provides a library of previous configurations of a system. The system includes multiple components connected together with cables. The method generates, from the library, instructions for assembling the system by connecting components of the system together with cables. The method receives feedback generated in the course of using the instructions to assemble the system and uses the feedback to refine the instructions. In certain embodiments, a configuration associated with the assembled system is then added to the library. This process may be repeated to further refine the instructions and increase a number of configurations in the library. A corresponding apparatus and computer program product are also disclosed.

Abstract: A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.

Abstract: The disclosed technology is generally directed to network security for processors. In one example of the technology, a device includes: a memory that is adapted to store run-time data for the device, and a processor. The processor is adapted to execute processor-executable code including a first binary that includes at least one application and a kernel, and a second binary. The second binary is configured to perform networking functions exclusively, including networking functions of one more of layers three through seven of the Open Systems Interconnection (OSI) model.

Abstract: Techniques are described for compiling source code to generate graph-optimized intermediate representation instructions of the source code that implement techniques for optimizing algorithms for graph analysis. A compiler, executing on a computing device, receives source code instructions for a program to be compiled. The compiler identifies a target expression, within the source code instructions, that invokes a particular method call on a particular object type. The target expression contains a target block of code to be translated into an intermediate representation using graph-optimized compilation techniques. The compiler generates a block of graph-specific intermediate representation instructions to replace the target expression. The compiler compiles the source code instructions to generate intermediate representation instructions, where the intermediate representation instructions include the block of graph-specific intermediate representation instructions in place of the target expression.

Abstract: The invention provides a computer-implemented method (and corresponding system) for generating a blockchain transaction (Tx). This may be a transaction for the Bitcoin blockchain or another blockchain protocol. The method comprises the step of using a software resource to receive, generate or otherwise derive at least one data item; and then insert, at least once, at least one portion of code into a script associated the transaction. Upon execution of the script, the portion of code provides the functionality of a control flow mechanism, the behaviour of the control flow mechanism being controlled or influenced by the at least one data item. In one embodiment, the code is copied/inserted into the script more than once. The control flow mechanism can be a loop, such as a while or for loop, or a selection control mechanism such as a switch statement. Thus, the invention allows the generation of a more complex blockchain script and controls how the script will execute when implemented on the blockchain.

Abstract: Systems, apparatuses and methods may provide for technology to identify in user code, a nested loop which would result in cache memory misses when executed. The technology further reverses an order of iterations of a first inner loop in the nested loop to obtain a modified nested loop. Reversing the order of iterations increases a number of times that cache memory hits occur when the modified nested loop is executed.

Abstract: A software code optimizer automatically detects inefficiencies in software code and corrects them. Generally, the software code optimizer converts software code into a graph representing the workflows and relationships in the software code. The graph is then converted into vectors that represent each workflow in the software code. The vectors are assembled into a matrix that represents the software code. The matrix may be stored in a cluster in a database as an example of optimized software code or be compared with other matrices stored as clusters in the database to determine whether the software code is optimized. The software code optimizer can change the software code to be more efficient if a matrix for an optimized version of the software code is found in the database.

Abstract: Disclosed herein are systems and method for collecting an optimal set of log files for generating error reports. In one aspect, a method may comprise detecting an error in a software component and retrieving a function call trace associated with the software component. The method may comprise comparing the retrieved function call trace with a plurality of known call traces, wherein each respective known call trace of the plurality of known call traces is associated with a respective set of log files to be collected for error analysis. The method may comprise identifying, based on the comparison, a known call trace for which a similarity value with the retrieved function call trace is greater than a threshold similarity value. The method may comprise collecting a set of log files for the error based on an associated set of log files for the known call trace and generating an error report.

Abstract: An information processing device includes: a processor coupled to a memory and configured to: obtain a source code including loop operations, statements being included in the loop operations; split each of the loop operations into a plurality of loop operations to maintain dependency relationships among statements in the source code; and in a case where the two statements each included in corresponding one of the two loop operations after the split have a plurality of data structures including elements including contiguous addresses, when the total number of the data structures included in the two statements does not exceed a number of memory fetch streams, perform a fusion of the two loop operations to maintain a dependency relationship between the two statements, and when the total number of the data structures included in the two statements exceeds the number of memory fetch streams, not perform the fusion.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

Abstract: According to aspects of the disclosure a method is provided, comprising: generating a live execution trace log corresponding to a live execution of a computer program, the live execution being performed by using both hardware emulation and hardware acceleration; generating a first trace entry corresponding to a replay execution of the computer program, the replay execution being performed by using hardware emulation without hardware acceleration, the replay execution being performed based on a set of events that are recorded during the live execution of the computer program; detecting whether the first trace entry is valid based on the live execution trace log; and in response to detecting that the first trace entry is not valid, transitioning into a safe state.

Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.

Abstract: An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.

Abstract: A method comprises receiving, by a media pipeline framework, a plurality of copies of each block of a media pipeline, wherein a first copy of the plurality of copies is a high-level representation of the respective block and wherein the second copy of the plurality of copies is a machine-readable copy. The method further comprises generating, by a processing device, a run-time-optimized media pipeline using the first copy and the second copy.

Abstract: An industrial integrated development environment (IDE) supports a testing framework that verifies operation of all aspects of the project (e.g., controller code, HMI screens or other visualizations, panel layouts, wiring schedules, etc.). As part of this testing framework, automation objects supported by the industrial IDE include associated test scripts designed to execute one or more test scenarios appropriate to the type of automation object or project being tested. Test scripts can also be associated with portions of the system project. The testing platform applies testing to the automation project as a whole in a holistic manner rather than to specific portions of a control program, verifying linkages across design platforms (e.g., control code, visualization, panel layouts, wiring, piping, etc.) that may otherwise not be tested.

Abstract: Techniques for assessing the completeness of a graphical display configuration of a process plant include receiving or obtaining a list of expected display views to be included in the draft of the process plant's graphical configuration or a portion thereof. For each expected display view, a graphical display configuration application obtains a list of expected control references corresponding to the display view and determines whether the control references are included in the display view, whether the control references are configured and stored in a control configuration database, and/or whether related display views corresponding to the control references are configured.

Abstract: Described herein includes an information transport system that optimizes the import of information systems to efficiently and speedily complete the transport. The system may include a transport processor for receiving a request to transport data; generating a dependency table comprising a plurality of procedures for executing the request; generating a dependency tree based on the dependency table, the dependency tree comprising at least one independent string of procedures from the plurality of procedures, the dependency tree indicating the order that the plurality of procedures will be executed by the transport processor; and executing the dependency tree.

Abstract: A method for buffer overflow detection involves obtaining a program code configured to access memory locations in a loop using a buffer index variable, obtaining an assertion template configured to capture a dependency between the buffer index variable and a loop index variable of the loop in the program code, generating an assertion using the assertion template, verifying that the assertion holds using a k-induction; and determining whether a buffer overflow exists using the assertion.

Abstract: Various technologies described herein pertain to enforcing control flow integrity by adding instrumentation when source code is compiled or binary code is rewritten. An indirect call to a control transfer target (e.g., in the source code, in the binary code, etc.) can be identified. Moreover, the instrumentation can be inserted prior to the indirect call. The instrumentation can use a bit from a bitmap maintained by a runtime to verify whether the control transfer target is valid. When an executable image that includes the inserted instrumentation runs, execution can be terminated and/or other appropriate actions can be taken when the control transfer target is determined to be invalid; alternatively, execution can continue when the control transfer target is determined to be valid.

Abstract: An explicit type for a construct is not necessarily specified by a set of code. Where an explicit type is not specified for a particular construct, a compiler performs type inference for the particular construct. If the compiler infers a denotable type is associated with the construct, the compiler proceeds to perform quality checking for the particular construct by evaluating quality conditions with respect to the inferred denotable type. However, if the compiler determines that a non-denotable type is associated with the construct, then the compiler selects a target type determination process based on an attribute of the inferred non-denotable type associated with the particular construct. The compiler determines one or more target types using the selected target type determination process. The compiler performs quality checking for the particular construct by evaluating quality conditions with respect to the target types.

Abstract: A system architecture, a method, and a computer program product are disclosed for attaching remote physical devices. In one embodiment, the system architecture comprises a compute server and a device server. The compute server includes a system memory, and one or more remote device drivers; and the device server includes a system memory and one or more physical devices, and each of the physical devices includes an associated device memory. The compute server and the device server are connected through an existing network fabric that provides remote direct memory access (RDMA) services. A system mapping function logically connects one or more of the physical devices on the device server to the compute server, including mapping between the system memories and the device memories and keeping the system memories and the device memories in synchronization using the RDMA.

Abstract: Methods and Systems for verifying a software program in an integrated-development environment are disclosed. In one embodiment, a method of verifying the software program in the integrated-development environment includes generating a source code of a software program in comprising logging statements based on a specification of the software program. Furthermore, the method includes executing the source code with the logging statements and generating one or more log files during execution of the source code based on the logging statements. Moreover, the method includes generating a representation of the source code in a modeling language based on the one or more log files. The method includes verifying compliance of the source code with the specification by comparing the representation of the source code in the modeling language with the specification in the modeling language.

Abstract: Techniques for lazy copying of runtime-managed stack frames are disclosed. A runtime environment generates a runtime-managed stack including multiple frames. A topmost subset of frames includes data associated with particular instructions and a return address. A lower subset of frames includes data associated with different instructions. The runtime environment stores a copy of the topmost subset of frames in an OS-managed stack, without copying the lower subset. The particular instructions execute using the copy of the topmost subset of frames in the OS-managed stack. The runtime environment replaces, in the copy, the return address with a return barrier address. When execution of the instructions terminates, control passes to return barrier instructions, which store a copy of the lower subset of frames in the OS-managed stack and pass control to the different instructions. The different instructions execute using the copy of the lower subset of frames in the OS-managed stack.

Abstract: An aspect of the present disclosure facilitates deployment of patches in computing systems. In an embodiment, specific objects of a software application that have been used for processing of commands are identified. A set of objects of the specific objects having patches available to be applied are then determined. The available patches may be retrieved and applied. As a result, patches may not be applied to objects that are not used. According to another aspect, usage data indicating usage of each object when the object is invoked for processing of corresponding command, is maintained. An administrator is also provided the ability to configure a set of rules indicating conditions under which existence of patches is to be checked for used objects, and the usage data is examined according to the set of rules.

Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.

Abstract: A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses to the tiered memory system by an action of a computing device in a first time interval are monitored to determine a first measure of bandwidth utilization, from which it is determined if the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value. It is further determined, from confidence counters, if a monitored access is consistent with respect to the first instructions or with respect to a memory address of the access. Data associated with the access is moved from the lower bandwidth memory to the higher bandwidth memory when the action is in a high bandwidth phase, the access is consistent, and bandwidth utilization of the higher bandwidth memory is below a threshold.

Abstract: Systems and methods for backing up and restoring serverless applications are provided. A serverless application is queried to identify the functions and services used. These functions and services are transformed into a manifest or graph that allows the relationships of the serverless application to be identified in an automated manner. The serverless application can be backed up and/or restored using the manifest.

Abstract: A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Abstract: Techniques for implementing preemptive crash data capture are provided. According to one set of embodiments, a computer system can determine that a failure has occurred with respect to an application running on the computer system and, in response to the failure, collect context information pertaining to the application's state at the time of the failure. If the failure subsequently causes the application to crash, the computer system can generate a crash dump that includes the collected context information.

Abstract: A method for recovering data for a file system includes a journal-less recovery process that detects one or more inconsistencies for file system blocks upon a system failure based on one or more comparisons of information for the file system blocks.

Abstract: A plugin for a website browser can enable a user to deploy software onto a computing device quickly and easily. For example, the plugin can automatically detect that a user is visiting a website on which program code for a software application is shared or hosted. The website may be an open-source website, a program-code repository, or a program-code review platform. The plugin can automatically analyze the program code, an installation file provided with the program code, software and hardware characteristics of the specific computing device on which the software application is to be deployed, and other data to determine how to deploy the software application on the specific computing device. The plugin can then deploy the software application on the computing device in response to the user clicking a button, allowing for the software application to be easily deployed on the computing device with minimal user interaction or skill.

Abstract: A blockchain-based secure customized catalog system includes a catalog customization system that receives a request to customize a first software catalog, and modifies the first software catalog to create a second software catalog that is customized for computing devices in a computing system. The catalog customization system then generates and broadcasts a first blockchain transaction that includes a smart contract having a second software catalog hash created from the second software catalog. A blockchain device receives the first blockchain transaction and, in response, provides the smart contract on a blockchain. When the blockchain device receives a second blockchain transaction broadcast by the computing system and including a hash value, it executes the smart contract. If the blockchain device determines that the execution of the smart contract indicates that the hash value matches the second software catalog hash, it transmits a second software catalog verification to the computing system.

Abstract: Optimizations are provided for sibling calls. A sibling caller is marked to indicate that it may call a sibling routine or that it may call an external sibling routine. Based on the marking, certain processing is performed to facilitate use of sibling calls, particularly when the sibling routine being called is external to the caller.

Abstract: A software development system is described that enables a user that is debugging source code to select for unoptimizing a function within the source code and to cause an edit and continue operation to be performed that produces a compiled version of the source code in which the selected function is unoptimized, while other functions remain optimized. Embodiments also enable a user to select a previously unoptimized function within the source code for re-optimizing and to cause an edit and continue operation to be performed that produces a compiled version of the source code in which the function is re-optimized. Still further embodiments enable a user to select within source code that is being developed a function for which optimization should be prevented and to cause a compiled representation of the source code to be built in which the selected function is unoptimized, while other functions are optimized.