Including Analysis Of Program Patents (Class 717/154)
  • Patent number: 11126437
    Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas Andrew Sartorius, Thomas Philip Speier, Michael Scott McIlvaine, James Norris Dieffenderfer
  • Patent number: 11113059
    Abstract: An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 7, 2021
    Assignee: Next Silicon Ltd
    Inventors: Elad Raz, Ilan Tayari
  • Patent number: 11087429
    Abstract: A method comprises receiving, by a media pipeline framework, a plurality of copies of each block of a media pipeline, wherein a first copy of the plurality of copies is a high-level representation of the respective block and wherein the second copy of the plurality of copies is a machine-readable copy. The method further comprises generating, by a processing device, a run-time-optimized media pipeline using the first copy and the second copy.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 10, 2021
    Assignee: Red Hat, Inc.
    Inventors: Debarshi Ray, Arjun Shankar
  • Patent number: 11080176
    Abstract: An industrial integrated development environment (IDE) supports a testing framework that verifies operation of all aspects of the project (e.g., controller code, HMI screens or other visualizations, panel layouts, wiring schedules, etc.). As part of this testing framework, automation objects supported by the industrial IDE include associated test scripts designed to execute one or more test scenarios appropriate to the type of automation object or project being tested. Test scripts can also be associated with portions of the system project. The testing platform applies testing to the automation project as a whole in a holistic manner rather than to specific portions of a control program, verifying linkages across design platforms (e.g., control code, visualization, panel layouts, wiring, piping, etc.) that may otherwise not be tested.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 3, 2021
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Andrew R Stump, Anthony Carrara, Eashwer Srinivasan, Christopher W Como, Sharon M Billi-Duran
  • Patent number: 11054974
    Abstract: Techniques for assessing the completeness of a graphical display configuration of a process plant include receiving or obtaining a list of expected display views to be included in the draft of the process plant's graphical configuration or a portion thereof. For each expected display view, a graphical display configuration application obtains a list of expected control references corresponding to the display view and determines whether the control references are included in the display view, whether the control references are configured and stored in a control configuration database, and/or whether related display views corresponding to the control references are configured.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 6, 2021
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Julian K. Naidoo, Daniel R. Strinden, Cristopher Ian Sarmiento Uy, Camilo Fadul, Jon Westbrock, Stephen G. Hammack, Drew T. Noah
  • Patent number: 11030168
    Abstract: Described herein includes an information transport system that optimizes the import of information systems to efficiently and speedily complete the transport. The system may include a transport processor for receiving a request to transport data; generating a dependency table comprising a plurality of procedures for executing the request; generating a dependency tree based on the dependency table, the dependency tree comprising at least one independent string of procedures from the plurality of procedures, the dependency tree indicating the order that the plurality of procedures will be executed by the transport processor; and executing the dependency tree.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 8, 2021
    Assignee: SAP SE
    Inventors: Barbara Freund, Wulf Kruempelmann
  • Patent number: 11030304
    Abstract: A method for buffer overflow detection involves obtaining a program code configured to access memory locations in a loop using a buffer index variable, obtaining an assertion template configured to capture a dependency between the buffer index variable and a loop index variable of the loop in the program code, generating an assertion using the assertion template, verifying that the assertion holds using a k-induction; and determining whether a buffer overflow exists using the assertion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 8, 2021
    Assignee: Oracle International Corporation
    Inventors: Francois Gauthier, Nathan Keynes, Padmanabhan Krishnan, Cristina Cifuentes, Trung Quang Ta
  • Patent number: 11003464
    Abstract: Various technologies described herein pertain to enforcing control flow integrity by adding instrumentation when source code is compiled or binary code is rewritten. An indirect call to a control transfer target (e.g., in the source code, in the binary code, etc.) can be identified. Moreover, the instrumentation can be inserted prior to the indirect call. The instrumentation can use a bit from a bitmap maintained by a runtime to verify whether the control transfer target is valid. When an executable image that includes the inserted instrumentation runs, execution can be terminated and/or other appropriate actions can be taken when the control transfer target is determined to be invalid; alternatively, execution can continue when the control transfer target is determined to be valid.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: May 11, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Richard John Black, Timothy William Burrell, Miguel Oom Temudo de Castro, Manuel Silverio da Silva Costa, Kenneth Johnson, Matthew Ryan Miller
  • Patent number: 10983771
    Abstract: An explicit type for a construct is not necessarily specified by a set of code. Where an explicit type is not specified for a particular construct, a compiler performs type inference for the particular construct. If the compiler infers a denotable type is associated with the construct, the compiler proceeds to perform quality checking for the particular construct by evaluating quality conditions with respect to the inferred denotable type. However, if the compiler determines that a non-denotable type is associated with the construct, then the compiler selects a target type determination process based on an attribute of the inferred non-denotable type associated with the particular construct. The compiler determines one or more target types using the selected target type determination process. The compiler performs quality checking for the particular construct by evaluating quality conditions with respect to the target types.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 20, 2021
    Assignee: Oracle International Corporation
    Inventors: Chris Hegarty, Maurizio Cimadamore
  • Patent number: 10936535
    Abstract: A system architecture, a method, and a computer program product are disclosed for attaching remote physical devices. In one embodiment, the system architecture comprises a compute server and a device server. The compute server includes a system memory, and one or more remote device drivers; and the device server includes a system memory and one or more physical devices, and each of the physical devices includes an associated device memory. The compute server and the device server are connected through an existing network fabric that provides remote direct memory access (RDMA) services. A system mapping function logically connects one or more of the physical devices on the device server to the compute server, including mapping between the system memories and the device memories and keeping the system memories and the device memories in synchronization using the RDMA.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hubertus Franke, Davide Pasetto, Hartmut Penner
  • Patent number: 10929108
    Abstract: Methods and Systems for verifying a software program in an integrated-development environment are disclosed. In one embodiment, a method of verifying the software program in the integrated-development environment includes generating a source code of a software program in comprising logging statements based on a specification of the software program. Furthermore, the method includes executing the source code with the logging statements and generating one or more log files during execution of the source code based on the logging statements. Moreover, the method includes generating a representation of the source code in a modeling language based on the one or more log files. The method includes verifying compliance of the source code with the specification by comparing the representation of the source code in the modeling language with the specification in the modeling language.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 23, 2021
    Assignee: SIEMENS INDUSTRY SOFTWARE NV
    Inventor: Sanjit Mishra
  • Patent number: 10908910
    Abstract: Techniques for lazy copying of runtime-managed stack frames are disclosed. A runtime environment generates a runtime-managed stack including multiple frames. A topmost subset of frames includes data associated with particular instructions and a return address. A lower subset of frames includes data associated with different instructions. The runtime environment stores a copy of the topmost subset of frames in an OS-managed stack, without copying the lower subset. The particular instructions execute using the copy of the topmost subset of frames in the OS-managed stack. The runtime environment replaces, in the copy, the return address with a return barrier address. When execution of the instructions terminates, control passes to return barrier instructions, which store a copy of the lower subset of frames in the OS-managed stack and pass control to the different instructions. The different instructions execute using the copy of the lower subset of frames in the OS-managed stack.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 2, 2021
    Assignee: Oracle International Corporation
    Inventors: Erik Duveblad, Ron Pressler
  • Patent number: 10891124
    Abstract: An aspect of the present disclosure facilitates deployment of patches in computing systems. In an embodiment, specific objects of a software application that have been used for processing of commands are identified. A set of objects of the specific objects having patches available to be applied are then determined. The available patches may be retrieved and applied. As a result, patches may not be applied to objects that are not used. According to another aspect, usage data indicating usage of each object when the object is invoked for processing of corresponding command, is maintained. An administrator is also provided the ability to configure a set of rules indicating conditions under which existence of patches is to be checked for used objects, and the usage data is examined according to the set of rules.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 12, 2021
    Assignee: Oracle International Corporation
    Inventors: Satish Oruganti, Shreyas Ravindranath
  • Patent number: 10885985
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10866899
    Abstract: A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses to the tiered memory system by an action of a computing device in a first time interval are monitored to determine a first measure of bandwidth utilization, from which it is determined if the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value. It is further determined, from confidence counters, if a monitored access is consistent with respect to the first instructions or with respect to a memory address of the access. Data associated with the access is moved from the lower bandwidth memory to the higher bandwidth memory when the action is in a high bandwidth phase, the access is consistent, and bandwidth utilization of the higher bandwidth memory is below a threshold.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: December 15, 2020
    Assignee: ARM LTD
    Inventors: Prakash S. Ramrakhyani, Joshua Randall, Wendy Arnott Elsasser
  • Patent number: 10853183
    Abstract: Systems and methods for backing up and restoring serverless applications are provided. A serverless application is queried to identify the functions and services used. These functions and services are transformed into a manifest or graph that allows the relationships of the serverless application to be identified in an automated manner. The serverless application can be backed up and/or restored using the manifest.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 1, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Assaf Natanzon, Amit Lieberman
  • Patent number: 10831493
    Abstract: A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus Buehler, Burkhard Steinmacher-Burow, Arni Ingimundarson, Thilo Maurer, Benedikt Rombach
  • Patent number: 10783027
    Abstract: Techniques for implementing preemptive crash data capture are provided. According to one set of embodiments, a computer system can determine that a failure has occurred with respect to an application running on the computer system and, in response to the failure, collect context information pertaining to the application's state at the time of the failure. If the failure subsequently causes the application to crash, the computer system can generate a crash dump that includes the collected context information.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Manodasan Wignarajah, Avneet Singh
  • Patent number: 10740184
    Abstract: A method for recovering data for a file system includes a journal-less recovery process that detects one or more inconsistencies for file system blocks upon a system failure based on one or more comparisons of information for the file system blocks.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Prasenjit Sarkar, Mohit Saxena
  • Patent number: 10684839
    Abstract: A plugin for a website browser can enable a user to deploy software onto a computing device quickly and easily. For example, the plugin can automatically detect that a user is visiting a website on which program code for a software application is shared or hosted. The website may be an open-source website, a program-code repository, or a program-code review platform. The plugin can automatically analyze the program code, an installation file provided with the program code, software and hardware characteristics of the specific computing device on which the software application is to be deployed, and other data to determine how to deploy the software application on the specific computing device. The plugin can then deploy the software application on the computing device in response to the user clicking a button, allowing for the software application to be easily deployed on the computing device with minimal user interaction or skill.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: June 16, 2020
    Assignee: Red Hat Israel, Ltd.
    Inventors: Boaz Shuster, Oded Ramraz
  • Patent number: 10671372
    Abstract: A blockchain-based secure customized catalog system includes a catalog customization system that receives a request to customize a first software catalog, and modifies the first software catalog to create a second software catalog that is customized for computing devices in a computing system. The catalog customization system then generates and broadcasts a first blockchain transaction that includes a smart contract having a second software catalog hash created from the second software catalog. A blockchain device receives the first blockchain transaction and, in response, provides the smart contract on a blockchain. When the blockchain device receives a second blockchain transaction broadcast by the computing system and including a hash value, it executes the smart contract. If the blockchain device determines that the execution of the smart contract indicates that the hash value matches the second software catalog hash, it transmits a second software catalog verification to the computing system.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 2, 2020
    Assignee: Dell Products L.P.
    Inventors: Kevin T. Marks, Viswanath Ponnuru, Raveendra Babu Madala
  • Patent number: 10558438
    Abstract: Optimizations are provided for sibling calls. A sibling caller is marked to indicate that it may call a sibling routine or that it may call an external sibling routine. Based on the marking, certain processing is performed to facilitate use of sibling calls, particularly when the sibling routine being called is external to the caller.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10540262
    Abstract: A software development system is described that enables a user that is debugging source code to select for unoptimizing a function within the source code and to cause an edit and continue operation to be performed that produces a compiled version of the source code in which the selected function is unoptimized, while other functions remain optimized. Embodiments also enable a user to select a previously unoptimized function within the source code for re-optimizing and to cause an edit and continue operation to be performed that produces a compiled version of the source code in which the function is re-optimized. Still further embodiments enable a user to select within source code that is being developed a function for which optimization should be prevented and to cause a compiled representation of the source code to be built in which the selected function is unoptimized, while other functions are optimized.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: January 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ramkumar Ramesh, Changqing Fu, Ankit Asthana, Andrew B. Hall
  • Patent number: 10503634
    Abstract: Techniques are described for semantically comparing machine code traces generated by compilers that compile computer software code. For example, a trace of machine code generated by a compiler can be obtained. The trace can be transformed into a set of expressions in a uniform expression format (e.g., by performing translation of the trace instructions into corresponding expressions and/or by performing other transformations). The set of expressions in the uniform expression format can be compared to other sets of expressions in the uniform expression format (e.g., other sets of expressions created from traces of machine code from other compilers). Results of the comparison can comprise indications of whether the sets of expressions match.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 10, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xiang Li, Ivan Nevraev, David McCarthy Peixotto, Marcelo Lopez Ruiz
  • Patent number: 10503485
    Abstract: A method for generating program code based on one or more blocks of a block diagram in a technical computing environment, an identifier being assigned to at least one, preferably each, of the one or more blocks of the block diagram. A processor opens the block diagram in the model editor, converts the block diagram to an intermediate representation using the code generator, wherein the conversion comprises checking if a replacement condition is fulfilled for a current block in the block diagram. Checking the replacement condition includes verifying that a predefined functional code unit is assigned to the identifier of the current block, in that case changing the block to a placeholder containing input/output-definitions but no functionality. The processor then converts the intermediate representation to program code, the conversion comprising adding a predefined functional code unit from the data definition tool to the definition code corresponding to the placeholder block.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 10, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Andreas Hoffmann, Wolfgang Trautmann, Frank Luenstroth, Volker Straetgen
  • Patent number: 10440154
    Abstract: A method for predictive loading of software resources in a web application includes predicting a future state of the web application, determining the software resources required by the first predicted future state, and loading the software resources required by the first predicted future state. Determining that future predicated state further includes determining an associated probability for each possible future state in the first set of possible future states, identifying, from the first set of possible future states, a first predicted future state with the highest associated probability, and predicting a first set of possible future states based on a current state, run-time application context, and either use case data or historical application usage data.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 8, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Chaithanya Lekkalapudi
  • Patent number: 10437885
    Abstract: Implementations of the disclosure provide for graph modeling of applications for detection of duplicate modules. In one embodiment, an apparatus comprising: a memory to store graphs; and a processing device, operatively coupled to the memory is provided. The processing device identify a first executable code module of a plurality of executable code modules associated with an application represented by a graph data structure. The graph data structure is updated with an indicator for each of the executable code modules matching the first module. The indicator references the first executable code module. One or more corresponding modules associated with the graph data structure are selected in view of the indicator. Using the graph data structure, an amount of a computing resource to allocate for a migration of the corresponding modules of the application is determined in view of a selection criterion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 8, 2019
    Assignee: Red Hat, Inc.
    Inventors: Ondrej Zizka, Jesse Daniel Sightler
  • Patent number: 10417119
    Abstract: A method for automated software testing may include mapping test cases to lines in files in a codebase. Each test case covers one or more lines in one or more files and has corresponding test results. The method may further include obtaining a change list including one or more changes. Each change specifies a changed line in a changed file. The method may further include determining impacted test cases, based on the mapping and the change list, prioritizing the impacted test cases based, in part, on test results corresponding to each impacted test case, executing, based on the prioritization, one or more impacted test cases to obtain executed test cases, and obtaining, for each executed test case, new test results.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 17, 2019
    Assignee: INTUIT INC.
    Inventors: Sachin Francis, Divya Gupta, Ayush Datta, Vijay Thomas
  • Patent number: 10379886
    Abstract: A non-transitory computer-readable medium stores computer-executable instructions that, when executed by a computer, cause the computer to perform operations including generating a changed optimization file by changing an original optimization file, the original optimization file being an optimization file created at a point in time at which an intermediate language file for an application is loaded; storing the changed optimization file; creating and storing verification information for verifying whether the intermediate language file is changed; determining whether the intermediate language file is changed based on the stored verification information in response to reloading of the intermediate language file; and creating a new optimization file by deleting the changed optimization file or recovering the original optimization file based on the changed optimization file and reusing the original optimization file, based on whether the intermediate language file is changed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: August 13, 2019
    Assignee: LINE CORPORATION
    Inventors: Sang Min Chung, SangHun Jeon, Myungju Chung, Wang Jin Oh, Sungbeom Ahn, Dongpil Seo, Kwang-Hee Han, Tae Woo Kim, Seong Yeol Lim, Joo Hyeon Ryu
  • Patent number: 10353679
    Abstract: A PGO compiler can instrument an executable to collect profile data from which global variables that were modified during the execution of a training executable can be identified. PGO optimization using a list of modified global variables identified from the profile data can be used to optimize a program in a second compilation phase. The global variables that were modified during the training run are identified by capturing a current snapshot of global variables and comparing their state to a baseline snapshot to ascertain the addresses of global variables that were modified. The addresses that changed can be mapped to global variable names to create a list of global variables that were modified during execution of the training executable. The list of global variables that have been modified can be to enable the compiler to perform optimizations such as but not limited to co-locate the modified global variables in memory.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 16, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventor: Terry Jack Mahaffey
  • Patent number: 10354064
    Abstract: According to the invention, there is provided a computer implemented method for controlling dynamically the execution of a code by a processing system, said execution being described by a control flow graph comprising a plurality of basic blocks composed of at least an input node and an output node, a transition in the control flow graph corresponding to a link between an output node of origin belonging to a first basic block and an input node of a second basic block, a plurality of initialization vectors being associated to the output nodes at the time of generating the code, an a priori control word being associated to each input node which is linked to the same output node of origin according the control flow graph, said a priori control word being precomputed at the time of generating the code by applying a predefined deterministic function F to the initialization vector associated to its output node of origin, the following steps being applied once the execution of the output node belonging to a first ba
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: July 16, 2019
    Assignee: SECURE-IC SAS
    Inventors: Sylvain Guilley, Thibault Porteboeuf
  • Patent number: 10338906
    Abstract: The disclosure is directed to controlling availability of a feature of an application without having to change a code of the application. A gate application employs a “gate” that facilitates making a feature available to a set of users without having to change the code of the application as the set of users to whom the feature is to be made available change. The gate includes parameters and criteria that can determine whether a particular feature of the application, e.g., a photo tagging feature of a social networking application, is to be made available to a particular user. If the request attributes, e.g., attributes associated with a requesting user, satisfy the criteria defined in the gate, the gate indicates to the host application to make the feature available, which then executes a portion of the code corresponding to the particular feature to make the particular feature available to the user.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 2, 2019
    Assignee: Facebook, Inc.
    Inventors: Richard William Branson, Chenyang Wu
  • Patent number: 10325097
    Abstract: A method for statically analyzing a web application program may include obtaining a control flow graph for the web application program. Each control flow graph node may correspond to a statement in the web application program. The method may further include obtaining a sanitizer sequence including one or more sanitizers followed by an output statement, obtaining a placeholder corresponding to the sanitizer sequence, and generating control flow paths including an output node that corresponds to the output statement. The method may further include generating documents for each control flow path. Each document may include a sanitized value corresponding to the output statement. The method may further include inserting the placeholder into each document at a location of the sanitized value, and reporting a potential cross-site scripting flaw when the sanitizer sequence is insufficient for the output context sequence of the sanitized value.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Oracle International Corporation
    Inventors: Francois Gauthier, Antonin Steinhauser
  • Patent number: 10270886
    Abstract: A method and system for dynamically optimizing a script library are described. A request for a script library is received from a set of client devices. An instrumented version of the script library is transmitted to at least one of the set of client devices. The instrumented version of the script library includes code for tracing execution of the script library. Responsive to execution of the instrumented version of the script library at each one of the at least one of client devices, script library usage feedback indicative of usage of the script library at these client devices is received. An optimized version of the script library, generated based on the script library usage feedback by removing portions of the script library that are unused by the subset of client devices, is transmitted to the client device instead of the script library in response to a second request.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 23, 2019
    Assignee: CLOUDFLARE, INC.
    Inventors: Igor Postelnik, Dane Orion Knecht, Oliver Zi-gang Yu, John Fawcett
  • Patent number: 10255050
    Abstract: A method for disambiguating an executable code file including a symbol table, includes reading a disambiguation configuration including at least one symbol-renaming instruction; renaming symbols from a symbol table according to at least one symbol-renaming instruction of the disambiguation configuration; and saving the file with the code disambiguated according to the disambiguation configuration.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: April 9, 2019
    Inventors: Patrice Martinez, Ga{hacek over (e)}l Lalire, Landry Stéphane Zeng Eyindanga
  • Patent number: 10255159
    Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 9, 2019
    Assignee: VMware, Inc.
    Inventors: James E. Chow, Tal Garfinkel, Peter M. Chen
  • Patent number: 10229045
    Abstract: A method for allocating memory includes an operation that determines whether a prototype of a callee function is within a scope of a caller. The caller is a module containing a function call to the callee function. In addition, the method includes determining whether the function call includes one or more unnamed parameters when a prototype of the callee function is within the scope of the caller. Further, the method may include inserting instructions in the caller to allocate a register save area in a memory when it is determined that the function call includes one or more unnamed parameters.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ronald I. McIntosh, Ulrich Weigand
  • Patent number: 10229044
    Abstract: A method for allocating memory includes an operation that determines whether a prototype of a callee function is within a scope of a caller. The caller is a module containing a function call to the callee function. In addition, the method includes determining whether the function call includes one or more unnamed parameters when a prototype of the callee function is within the scope of the caller. Further, the method may include inserting instructions in the caller to allocate a register save area in a memory when it is determined that the function call includes one or more unnamed parameters.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ronald I. McIntosh, Ulrich Weigand
  • Patent number: 10133560
    Abstract: A method for optimizing source code comprises optimizing the source code of files from a computer program at link-time, and receiving, at a linker, a customized linker script defining output sections for files of an executable version of the files of the computer program. The method comprises adding, to intermediate representation files having global or local symbols, metadata comprising default section assignment information for the symbols and recording, for symbols in machine code files, an origin path and an output section. The method further comprises parsing, by the compiler, the intermediate representation files, recording the symbols and related symbol information comprising default section assignment and dependency information of the intermediate representation files, assigning output sections to the symbols based on the default section assignments and instructions from the customized linker script, and linking optimized code of the files of the computer program based on the assigned output sections.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Innovation Center, Inc.
    Inventors: Sergei Larin, Shankar Kalpathi Easwaran, Hemant Kulkarni, Tobias Edler Von Koch
  • Patent number: 10108536
    Abstract: According to some embodiments, system comprises a communication device operative to communicate with a user to obtain one or more requirements associated with a model for a test case generation module; a translation computer module to receive the model, store the model and generate an intermediate model; a generator computer module to receive the intermediate model, store the intermediate model, generate at least one test case; a memory for storing program instructions; at least one test case generation platform processor, coupled to the memory, and in communication with the translation computer module and the generator computer module, operative to execute program instructions to: transform the model into an intermediate model by executing the translation computer module; identify a model type associated with the intermediate model based on an analysis of the intermediate model by executing the generator computer module; select a test generation method based on analysis of the identified model type by execut
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: October 23, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventor: Meng Li
  • Patent number: 9880923
    Abstract: A model checking device for a distributed-environment-model according to the present invention, includes: a distributed-environment-model search unit that adopts a first state as start point when obtaining information indicating a distributed-environment-model, searches the state attained by the distributed-environment-model by executing straight line movements for moving from the first state to a second state which is an end position, and determines whether the searched state satisfies a predetermined property; a searched state management unit that stores the searched state in the past; a searched-transition-history management unit that stores an order of the transitions of the straight line movements in the past; a searched state transition association information management unit that stores the transition when moving to another state in the past search in such a manner that the transition is associated with each of the searched states.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 30, 2018
    Assignee: NEC CORPORATION
    Inventors: Yutaka Yakuwa, Nobuyuki Tomizawa
  • Patent number: 9870240
    Abstract: Embodiments of the present invention disclose an approach for inserting code into a running thread of execution. A computer sets a first set of bits to a first value, wherein the first value indicates that a first set of instructions should be inserted onto a stack. The computer executes a second set of instructions associated with a first safepoint, wherein the second set of instructions comprises one or more instructions to determine if the first set of bits is set to the first value. The computer determines that the first set of bits is set to the first value, and the computer inserts the first set of instructions onto the stack.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael H. Dawson, Graeme Johnson, San Hong Li
  • Patent number: 9858419
    Abstract: A static analysis for identification of permission-requirements on stack-inspection authorization systems is provided. The analysis employs functional modularity for improved scalability. To enhance precision, the analysis utilizes program slicing to detect the origin of each parameter passed to a security-sensitive function. Furthermore, since strings are essential when defining permissions, the analysis integrates a sophisticated string analysis that models string computations.
    Type: Grant
    Filed: September 22, 2013
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julian Timothy Dolby, Emmanuel Geay, Marco Pistoia, Barbara G. Ryder, Takaaki Tateishi
  • Patent number: 9824419
    Abstract: A method and system are provided for executing, by a processor including a read-only cache, a program having a plurality of variables including a first variable and a second variable. Each variable is for executing a respective read operation or a respective write operation for an object. The method includes providing a first code that uses the read-only cache and a second code that does not use the read-only cache. The method further includes determining, by the processor, whether a first object designated by the first variable is aliased or not aliased with a second object designated by the second variable. The method also includes executing, by the processor, the first code when the first object is not aliased with the second object, and the second code when the first object is aliased with the second object.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 9817706
    Abstract: An information processing device in a parallel computer system, the information processing device includes a processor.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takafumi Nose
  • Patent number: 9811342
    Abstract: A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and performing a dual dispatch of the two half blocks for execution on an execution unit.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 9779133
    Abstract: Various embodiments of systems and methods for validating Structured Query Language (SQL) queries in a database-accessing software application during application development are described herein. In some embodiments, an SQL query can be copied, during debugging of the software application, from a program editor used to define the software application into an SQL console that facilitates modifying and executing the query and displays data resulting from the execution of the query. Upon developer validation of the SQL query, the validated query may be copied back into the software application to substitute the original query. The SQL query may include one or more unresolved parameters that can be resolved by the SQL console via access to memory in which the software application is executed during debugging.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 3, 2017
    Assignee: SAP SE
    Inventor: Raghuvira Bhagavan
  • Patent number: 9772882
    Abstract: The execution of an executable code by a set of processing modules is provided, wherein the executable code is executed by at least one first processing module of the set of processing modules, wherein said executable code comprises a set of parallel executable parts, wherein each parallel executable part of the executable code comprises at least two parallel executable steps, and wherein said executing comprises: detecting by the at least one first processing module a parallel executable part of the set of parallel executable parts of the executable code to be executed; selecting by the at least one first processing module at least two second processing modules of the set of processing modules; and commanding by the at least one first processing module the selected at least two second processing modules to perform the at least two parallel executable steps of the detected parallel executable part of the executable code.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 26, 2017
    Assignee: HYBRIDSERVER TEC IP GMBH
    Inventors: Halis Aslan, Farbod Saremi, Tobias Zielinski, Hendrik Dürkop
  • Patent number: 9710241
    Abstract: Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Egger Bernhard, Soo-jung Ryu, Dong-hoon Yoo, Il-hyun Park
  • Patent number: 9697021
    Abstract: A computer-implemented method includes compiling one or more segments of code during run-time of a process executing at one or more processors of a computer system. The compilation produces a high-level intermediate representation of the one or more segments of the code. The high-level intermediate representation is modifiable by the process, without executing the high-level intermediate representation, to generate a modified high-level intermediate representation that is executable by the process.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: July 4, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Harish Kantamneni, Andrew Cherry, Anders Hauge, Amanda Silver, Nathan Carlson, Anthony Crider, Abhijeet S. Shah, Ming Hong Zhu