Including Analysis Of Program Patents (Class 717/154)
  • Patent number: 10325097
    Abstract: A method for statically analyzing a web application program may include obtaining a control flow graph for the web application program. Each control flow graph node may correspond to a statement in the web application program. The method may further include obtaining a sanitizer sequence including one or more sanitizers followed by an output statement, obtaining a placeholder corresponding to the sanitizer sequence, and generating control flow paths including an output node that corresponds to the output statement. The method may further include generating documents for each control flow path. Each document may include a sanitized value corresponding to the output statement. The method may further include inserting the placeholder into each document at a location of the sanitized value, and reporting a potential cross-site scripting flaw when the sanitizer sequence is insufficient for the output context sequence of the sanitized value.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Oracle International Corporation
    Inventors: Francois Gauthier, Antonin Steinhauser
  • Patent number: 10270886
    Abstract: A method and system for dynamically optimizing a script library are described. A request for a script library is received from a set of client devices. An instrumented version of the script library is transmitted to at least one of the set of client devices. The instrumented version of the script library includes code for tracing execution of the script library. Responsive to execution of the instrumented version of the script library at each one of the at least one of client devices, script library usage feedback indicative of usage of the script library at these client devices is received. An optimized version of the script library, generated based on the script library usage feedback by removing portions of the script library that are unused by the subset of client devices, is transmitted to the client device instead of the script library in response to a second request.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 23, 2019
    Assignee: CLOUDFLARE, INC.
    Inventors: Igor Postelnik, Dane Orion Knecht, Oliver Zi-gang Yu, John Fawcett
  • Patent number: 10255050
    Abstract: A method for disambiguating an executable code file including a symbol table, includes reading a disambiguation configuration including at least one symbol-renaming instruction; renaming symbols from a symbol table according to at least one symbol-renaming instruction of the disambiguation configuration; and saving the file with the code disambiguated according to the disambiguation configuration.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: April 9, 2019
    Inventors: Patrice Martinez, Ga{hacek over (e)}l Lalire, Landry Stéphane Zeng Eyindanga
  • Patent number: 10255159
    Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 9, 2019
    Assignee: VMware, Inc.
    Inventors: James E. Chow, Tal Garfinkel, Peter M. Chen
  • Patent number: 10229045
    Abstract: A method for allocating memory includes an operation that determines whether a prototype of a callee function is within a scope of a caller. The caller is a module containing a function call to the callee function. In addition, the method includes determining whether the function call includes one or more unnamed parameters when a prototype of the callee function is within the scope of the caller. Further, the method may include inserting instructions in the caller to allocate a register save area in a memory when it is determined that the function call includes one or more unnamed parameters.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ronald I. McIntosh, Ulrich Weigand
  • Patent number: 10229044
    Abstract: A method for allocating memory includes an operation that determines whether a prototype of a callee function is within a scope of a caller. The caller is a module containing a function call to the callee function. In addition, the method includes determining whether the function call includes one or more unnamed parameters when a prototype of the callee function is within the scope of the caller. Further, the method may include inserting instructions in the caller to allocate a register save area in a memory when it is determined that the function call includes one or more unnamed parameters.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ronald I. McIntosh, Ulrich Weigand
  • Patent number: 10133560
    Abstract: A method for optimizing source code comprises optimizing the source code of files from a computer program at link-time, and receiving, at a linker, a customized linker script defining output sections for files of an executable version of the files of the computer program. The method comprises adding, to intermediate representation files having global or local symbols, metadata comprising default section assignment information for the symbols and recording, for symbols in machine code files, an origin path and an output section. The method further comprises parsing, by the compiler, the intermediate representation files, recording the symbols and related symbol information comprising default section assignment and dependency information of the intermediate representation files, assigning output sections to the symbols based on the default section assignments and instructions from the customized linker script, and linking optimized code of the files of the computer program based on the assigned output sections.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Innovation Center, Inc.
    Inventors: Sergei Larin, Shankar Kalpathi Easwaran, Hemant Kulkarni, Tobias Edler Von Koch
  • Patent number: 10108536
    Abstract: According to some embodiments, system comprises a communication device operative to communicate with a user to obtain one or more requirements associated with a model for a test case generation module; a translation computer module to receive the model, store the model and generate an intermediate model; a generator computer module to receive the intermediate model, store the intermediate model, generate at least one test case; a memory for storing program instructions; at least one test case generation platform processor, coupled to the memory, and in communication with the translation computer module and the generator computer module, operative to execute program instructions to: transform the model into an intermediate model by executing the translation computer module; identify a model type associated with the intermediate model based on an analysis of the intermediate model by executing the generator computer module; select a test generation method based on analysis of the identified model type by execut
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: October 23, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventor: Meng Li
  • Patent number: 9880923
    Abstract: A model checking device for a distributed-environment-model according to the present invention, includes: a distributed-environment-model search unit that adopts a first state as start point when obtaining information indicating a distributed-environment-model, searches the state attained by the distributed-environment-model by executing straight line movements for moving from the first state to a second state which is an end position, and determines whether the searched state satisfies a predetermined property; a searched state management unit that stores the searched state in the past; a searched-transition-history management unit that stores an order of the transitions of the straight line movements in the past; a searched state transition association information management unit that stores the transition when moving to another state in the past search in such a manner that the transition is associated with each of the searched states.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 30, 2018
    Assignee: NEC CORPORATION
    Inventors: Yutaka Yakuwa, Nobuyuki Tomizawa
  • Patent number: 9870240
    Abstract: Embodiments of the present invention disclose an approach for inserting code into a running thread of execution. A computer sets a first set of bits to a first value, wherein the first value indicates that a first set of instructions should be inserted onto a stack. The computer executes a second set of instructions associated with a first safepoint, wherein the second set of instructions comprises one or more instructions to determine if the first set of bits is set to the first value. The computer determines that the first set of bits is set to the first value, and the computer inserts the first set of instructions onto the stack.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael H. Dawson, Graeme Johnson, San Hong Li
  • Patent number: 9858419
    Abstract: A static analysis for identification of permission-requirements on stack-inspection authorization systems is provided. The analysis employs functional modularity for improved scalability. To enhance precision, the analysis utilizes program slicing to detect the origin of each parameter passed to a security-sensitive function. Furthermore, since strings are essential when defining permissions, the analysis integrates a sophisticated string analysis that models string computations.
    Type: Grant
    Filed: September 22, 2013
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julian Timothy Dolby, Emmanuel Geay, Marco Pistoia, Barbara G. Ryder, Takaaki Tateishi
  • Patent number: 9824419
    Abstract: A method and system are provided for executing, by a processor including a read-only cache, a program having a plurality of variables including a first variable and a second variable. Each variable is for executing a respective read operation or a respective write operation for an object. The method includes providing a first code that uses the read-only cache and a second code that does not use the read-only cache. The method further includes determining, by the processor, whether a first object designated by the first variable is aliased or not aliased with a second object designated by the second variable. The method also includes executing, by the processor, the first code when the first object is not aliased with the second object, and the second code when the first object is aliased with the second object.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 9817706
    Abstract: An information processing device in a parallel computer system, the information processing device includes a processor.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takafumi Nose
  • Patent number: 9811342
    Abstract: A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and performing a dual dispatch of the two half blocks for execution on an execution unit.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 9779133
    Abstract: Various embodiments of systems and methods for validating Structured Query Language (SQL) queries in a database-accessing software application during application development are described herein. In some embodiments, an SQL query can be copied, during debugging of the software application, from a program editor used to define the software application into an SQL console that facilitates modifying and executing the query and displays data resulting from the execution of the query. Upon developer validation of the SQL query, the validated query may be copied back into the software application to substitute the original query. The SQL query may include one or more unresolved parameters that can be resolved by the SQL console via access to memory in which the software application is executed during debugging.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 3, 2017
    Assignee: SAP SE
    Inventor: Raghuvira Bhagavan
  • Patent number: 9772882
    Abstract: The execution of an executable code by a set of processing modules is provided, wherein the executable code is executed by at least one first processing module of the set of processing modules, wherein said executable code comprises a set of parallel executable parts, wherein each parallel executable part of the executable code comprises at least two parallel executable steps, and wherein said executing comprises: detecting by the at least one first processing module a parallel executable part of the set of parallel executable parts of the executable code to be executed; selecting by the at least one first processing module at least two second processing modules of the set of processing modules; and commanding by the at least one first processing module the selected at least two second processing modules to perform the at least two parallel executable steps of the detected parallel executable part of the executable code.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 26, 2017
    Assignee: HYBRIDSERVER TEC IP GMBH
    Inventors: Halis Aslan, Farbod Saremi, Tobias Zielinski, Hendrik Dürkop
  • Patent number: 9710241
    Abstract: Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Egger Bernhard, Soo-jung Ryu, Dong-hoon Yoo, Il-hyun Park
  • Patent number: 9697021
    Abstract: A computer-implemented method includes compiling one or more segments of code during run-time of a process executing at one or more processors of a computer system. The compilation produces a high-level intermediate representation of the one or more segments of the code. The high-level intermediate representation is modifiable by the process, without executing the high-level intermediate representation, to generate a modified high-level intermediate representation that is executable by the process.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: July 4, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Harish Kantamneni, Andrew Cherry, Anders Hauge, Amanda Silver, Nathan Carlson, Anthony Crider, Abhijeet S. Shah, Ming Hong Zhu
  • Patent number: 9542235
    Abstract: In one embodiment, a non-transitory processor-readable medium stores code representing instructions that when executed cause a processor to obtain a first mutual exclusion object. The first mutual exclusion object can be a write mutual exclusion object associated with a shared resource. The code can further represent instructions that when executed cause the processor to obtain a second mutual exclusion object associated with an object manager module and define a read event object with a name conforming to a predetermined format. The code can further represent instructions that when executed cause the processor to release the second mutual exclusion object, release the first mutual exclusion object, read at least a portion of the shared resource, obtain the second mutual exclusion object, destroy the read event object and release the second mutual exclusion object.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: January 10, 2017
    Assignee: AppSense, Limited
    Inventors: Richard Pointon, Richard James Somerfield
  • Patent number: 9529697
    Abstract: An embodiment can include one or more computer-readable media storing executable instructions that when executed on processing logic process variable signals. The media can store one or more instructions for receiving executable code that includes constructs with variable signals for processing the variable signals, and for performing a coverage measurement on the executable code based on information about one or more of the variable signals processed by the executable code. The media can store one or more instructions for producing a coverage result based on the coverage measurement, the coverage result identifying a degree of coverage for the executable code when the executable code processes the variable signals.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 27, 2016
    Assignee: The MathWorks, Inc.
    Inventors: William J. Aldrich, Olga Voronina, Zsolt Kalmar
  • Patent number: 9489214
    Abstract: New code is added to existing object code in order to add new functionality. For example, a call to start a profiler function can be added at the beginning of a Java method and a call to stop the profiler function can be added at the exits of the Java method. A method may have many different exits. To insure that the profiler process is stopped regardless of which exit is performed, the byte code and exception table are modified.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 8, 2016
    Assignee: CA, Inc.
    Inventor: Jeffrey R Cobb
  • Patent number: 9471327
    Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
  • Patent number: 9459878
    Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
  • Patent number: 9417855
    Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Abhay S. Kanhere, Paul Caprioli, Koichi Yamada, Suriya Madras-Subramanian, Suresh Srinivas
  • Patent number: 9411580
    Abstract: A code annotating system includes a code wrapper engine, an annotator engine, and a memory device. The code wrapper engine receives an output stream produced by a source code of a generator. The code wrapper engine also wraps the output stream to produce a copy of the output stream. The annotator engine automatically annotates the copy with source information. The source information maps a relationship between data in the output stream and the source code of the generator. The memory device stores the source information.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 9, 2016
    Assignee: International Business Machines Corporation
    Inventor: Scott B Greer
  • Patent number: 9411567
    Abstract: An optimizing compiler includes a strength reduction mechanism that optimizes a computer program that includes operations that have an unknown stride by analyzing the instructions in the computer program in a single pass, determining whether instruction substitution is profitable for original instructions in the code, and performing instruction substitution for one or more original instructions for which instruction substitution is deemed profitable, including operations with unknown strides. The substituted instructions result in strength reduction in the computer program.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 9, 2016
    Assignee: International Business Machines Corporation
    Inventor: William J. Schmidt
  • Patent number: 9405517
    Abstract: An optimizing compiler includes a strength reduction mechanism that optimizes a computer program that includes operations that have an unknown stride by analyzing the instructions in the computer program in a single pass, determining whether instruction substitution is profitable for original instructions in the code, and performing instruction substitution for one or more original instructions for which instruction substitution is deemed profitable, including operations with unknown strides. The substituted instructions result in strength reduction in the computer program.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventor: William J. Schmidt
  • Patent number: 9389845
    Abstract: In an aspect, a system, non-transitory machine readable medium and method for providing a personalized executable file to a client device is disclosed. A request sent from a client device to obtain a software application is received. The request is processed to identify the client device and a user associated with the client device. The client device profile information associated with the identified client device as well as user profile information associated with the identified user is determined. One or more configuration/core library files are selected from a file database based on the user profile information and the client device profile information. A personalized executable file is generated for the requested software application, wherein the personalized executable file comprises selected core library files and the selected configuration files. The personalized executable file of the requested software application is then sent to the client device.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: July 12, 2016
    Assignee: Infosys Limited
    Inventors: Puneet Gupta, Akshay Darbari, Venkat Kumar Sivaramamurthy, Sudhakar Vusirika
  • Patent number: 9383981
    Abstract: A modulo scheduling method including calculating at least two candidate initiation intervals between adjacent iterations, searching for schedules of the instructions in parallel by using the candidate initiation intervals, and selecting a schedule determined to be valid from among the searched schedules.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-wook Ahn, Won-sub Kim, Tai Song Jin, Seung-won Lee, Jin-seok Lee, Chae-seok Im
  • Patent number: 9342510
    Abstract: State handles mark application data states within a sequence of operations for preservation. Applications can maintain non-linear sets of operations that include multiple sequences of operations between state handles. Applications can determine a sequence of operations between any two state handles, allowing applications to change from the data state associated with one state handle to the data state associated with another state handle. The sequence of operations between any two state handles may include executing operations and/or reversing operations. An application automatically adds new branches in the set of operations to preserve the sequences of operations necessary to reconstruct data states of previously set handles and removes branches that are not needed.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: May 17, 2016
    Assignee: Pixar
    Inventors: Alex Mohr, Tom Lokovic
  • Patent number: 9336128
    Abstract: A method for code analysis includes generating, by a computer processor, an execution path through software code. Generating the execution path includes adding, for an object having an undefined class, a first symbolic type constraint to a path condition of the first execution path based on a first statement in the execution path, and adding, for the object having the undefined class, a second symbolic type constraint to the path condition of the execution path based on a second statement in the first execution path. The method further includes the computer processor making a determination that the path condition of the execution path is infeasible based on the first symbolic type constraint of the object being inconsistent with the second symbolic type constraint of the object, and discarding the execution path based on the determination.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 10, 2016
    Assignee: Oracle International Corporation
    Inventors: Lian Li, Andrew Santosa
  • Patent number: 9336023
    Abstract: Systems, methods and computer program products for mobile device application design are described herein. The method accesses a data model corresponding to a selected mobile platform. The data model is used by a device application designer to generate, model, and debug a mobile application. The data model is used to take into consideration characteristics of the selected platform and a selected mobile device as the application is designed. The application is structured and generated for a selected platform that is independent of the data model, but is cognizant of the selected platform. A simulator models the application user interface (UI) as it will appear on the selected platform. The method performs platform-specific validation and allows for correction of various aspects of a generated application including platform-specific features. The tool generates a graphical image that can guide a developer to either generated code or help files corresponding to framework libraries.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 10, 2016
    Assignee: SYBASE, INC.
    Inventors: Himagiri Mukkamala, Cliff Collins, Stella Yu
  • Patent number: 9329845
    Abstract: A system described herein includes a receiver component that receives source code from a computer-readable medium of a computing device and a static analysis component that executes a points-to analysis algorithm over the source code to cause generation of a points-to graph, wherein the points-to graph is a directed graph that comprises a plurality of nodes and a plurality of edges, wherein nodes of the points-to graph represent pointers in the source code and edges represent inclusion relationships in the source code. The system also includes an inference component that infers target types for generic pointers in the source code based at least in part upon known type definitions and global variables in the source code.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: May 3, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Weidong Cui, Marcus Peinado
  • Patent number: 9298926
    Abstract: Processing a downgrader specification by constructing a set of candidate downgrader placement locations found within a computer software application, where each of the candidate downgrader placement locations corresponds to a transition between a different pair of instructions within the computer software application, and where each of the transitions participates in any of a plurality of data flows in a set of security-sensitive data flows within the computer software application, applying a downgrader specification to the set of candidate downgrader placement locations, and determining that the downgrader specification provides full coverage of the set of security-sensitive data flows within the computer software application if at least one candidate downgrader placement location within each of the security-sensitive data flows is a member of the set of candidate downgrader placement locations.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Omer Tripp
  • Patent number: 9292693
    Abstract: Processing a downgrader specification by constructing a set of candidate downgrader placement locations found within a computer software application, where each of the candidate downgrader placement locations corresponds to a transition between a different pair of instructions within the computer software application, and where each of the transitions participates in any of a plurality of data flows in a set of security-sensitive data flows within the computer software application, applying a downgrader specification to the set of candidate downgrader placement locations, and determining that the downgrader specification provides full coverage of the set of security-sensitive data flows within the computer software application if at least one candidate downgrader placement location within each of the security-sensitive data flows is a member of the set of candidate downgrader placement locations.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: March 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Omer Tripp
  • Patent number: 9286083
    Abstract: A method for satisfying loader dependencies on a running embedded computing device is provided. When a software application is loaded on a running embedded computing device, one or more binary files are identified that need to be loaded in order to run the software application. A determination is made as to whether the identified binary files are stored on the embedded computing device. If one or more of the identified binary files are missing from the embedded computer device, one or more file storage devices are identified that contain the missing binary files. The missing binary files are obtained from the one or more file storage devices during runtime and used to complete the load of the software application.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: March 15, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Oren Winter
  • Patent number: 9280446
    Abstract: Disclosed are methods for finding all valid paths in a COBOL program. These methods are performed in polynomial time, allowing them to be scaled to accommodate large COBOL programs. As the methods find all valid paths in COBOL program code, by traversing and marking the nodes of the program upon being traversed. Accordingly, all usable and reachable code is indicated and marked. This increases safety when working with the code, as removal or alteration of such valid code is indicated, and thus, made unlikely.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Ran Ettinger, Yishai Feldman
  • Patent number: 9250877
    Abstract: A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: February 2, 2016
    Assignee: Cray Inc.
    Inventors: Heidi Poxon, John Levesque, Luiz DeRose, Brian H. Johnson
  • Patent number: 9203625
    Abstract: A method begins by a distributed storage (DS) processing module identifying encoded data slices of stored encoded data slices to transfer, wherein the stored encoded data slices are assigned addresses within a local distributed storage network (DSN) address range, wherein a global DSN address space is divided into a plurality of address sectors, and wherein the local DSN address range is a portion of an address sector. The method continues with the DS processing module determining whether another local DSN address range in the address sector exists and when the other local DSN address range in the address sector exists, determining whether to transfer identified encoded data slices into the other local DSN address range. When the at least some of the identified encoded data slices are to be transferred, the method continues with the DS processing module initiating a data transfer protocol to transfer the identified encoded data slices.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 1, 2015
    Assignee: CLEVERSAFE, INC.
    Inventors: Manish Motwani, Ilya Volvovski
  • Patent number: 9182955
    Abstract: A transformation of software control flow to reduce the number of successor blocks in the control flow as well as the number of flow control elements. The control flow after transformation has more streamline code and less data-dependent control flow, which yields better runtime performance, and at the same time maintain functionally equivalent. Software control flow is improved by, for each data-dependent flow control element in the control flow graph, finding value narrowing points that would be sufficient that the exit control flow selected by that flow control element would be deterministic. The control flow is modified such that the control flow leads (without passing through the flow control element) from that found value narrowing point to the identified control flow that would be selected given the found value narrowing point. This method may be repeated proceeding from one flow control element to the next.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: November 10, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wenlei He, Ten Tzen
  • Patent number: 9174118
    Abstract: Script injection in game clients used to access an online, interactive game may be detected. This detection may be performed on behalf of the entity operating the game in order to reduce cheating by users that relies on client modification through script injection. Detection of script injection may be performed on a recurring basis.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: November 3, 2015
    Assignee: Kabum, Inc.
    Inventors: Mark Vincent Gorospe Alviar, Cuong Le Ngo, Pascal Aschwanden, Kevin Kang So
  • Patent number: 9170830
    Abstract: An execution-target program is executed, via a program-execution control program, by converting a byte code in the execution-target program into a native code based on a predetermined condition. Upon activating the execution-target program, it is determined whether the execution-target program is an optimization-completed program having a past record of having been converted into an optimized state of the execution-target program, based on a profile including information identifying the optimization-completed program and optimized-code information indicating an optimized code for the optimization-completed program, where the profile is updated at a timing of executing the program-execution control program or another program-execution control program, and the optimized code is generated by converting a byte code into a native code.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 27, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Nobuo Shiba, Hiroshi Sasaki, Shinya Suematsu
  • Patent number: 9158664
    Abstract: An embodiment can include one or more computer-readable media storing executable instructions that when executed on processing logic process variable signals. The media can store one or more instructions for receiving executable code that includes constructs with variable signals for processing the variable signals, and for performing a coverage measurement on the executable code based on information about one or more of the variable signals processed by the executable code. The media can store one or more instructions for producing a coverage result based on the coverage measurement, the coverage result identifying a degree of coverage for the executable code when the executable code processes the variable signals.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 13, 2015
    Assignee: The MathWorks, Inc.
    Inventors: William J. Aldrich, Olga Voronina, Zsolt Kalmar
  • Patent number: 9158655
    Abstract: An apparatus of one embodiment assesses standards compliance during computer development and includes an interface, a memory, and a processor. The interface is operable to receive a selection from a user, the selection including an assessment ruleset to be used for evaluating a computer change. The assessment ruleset includes one or more assessment rules, each assessment rule associated with a condition that determines whether the assessment rule is evaluated. The memory operable to store the assessment ruleset. The processor is operable to determine whether the condition associated with each assessment rule is satisfied, to communicate to the user an evaluation question relating to each assessment rule whose associated condition is satisfied, an answer to the evaluation question indicating an extent to which the computer change complies with the assessment rule, and to determine one or more scores based on the answer to each evaluation question.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: October 13, 2015
    Assignee: Bank of America Corporation
    Inventors: Rajat Wadhwani, Kailash C. Poddar, Sameer Leekha
  • Patent number: 9141354
    Abstract: A determination is made regarding whether to merge two symbolic analysis states. A first state corresponds to a first path through a program to a program location and a second state corresponds to a second path through the program to the program location. A set of variables of the program at the program location is determined. For each variable in the set: a) a first value of the variable in the first state is determined; b) a second value of the variable in the second state is determined; and c) a determination is made, based on the first and second values, regarding whether merging the first and second states would be advantageous. A determination is made, responsive to determining that merging the first state and the second state would not be advantageous for at least one variable in the set, not to merge the first state and the second state.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: September 22, 2015
    Assignee: Ecole Polytechnique Fédérale de Lausanne (EPFL)
    Inventors: Volodymyr Kuznetsov, Johannes Kinder, Stefan Bucur, George Candea
  • Patent number: 9134976
    Abstract: In various implementations of a software analysis system, compliance checking is facilitated by analyzing different characteristics of a software system to be developed, and by comparing the information extracted from these analysis. Two or more characteristics may be expressed in different formats or languages, and the descriptions of one or more of these characteristic may be incomplete.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 15, 2015
    Assignee: Reservoir Labs, Inc.
    Inventors: James Ezick, Richard A. Lethin, Jonathan Springer, David E. Wohlford
  • Patent number: 9129040
    Abstract: A source code that includes an operator graph that includes a plurality of processing elements, each processing element having one or more stream operators is received. A metadata tag describing a customization of at least one of the one or more stream operators having a windowing processing operation is parsed from the source code. The source code of the streaming application having the windowing processing operation based on the metadata tag is compiled.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, John M. Santosuosso
  • Patent number: 9104432
    Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joshua S. Auerbach, David F. Bacon, Perry S. Cheng, Stephen Fink, Rodric Rabbah
  • Patent number: 9092369
    Abstract: Methods and systems may track the invocation path of a system or a library call from Java native interface (JNI) in Java applications. A native call of interest having an associated failure condition, an invocation path associated with the native call of interest, and a Java boundary crossover method (Java method invoking a JNI method) within the invocation path may all identified based on failure diagnostic information. The identified information may also be fed to a Java virtual machine (JVM). When the application is re-run, a check can be made prior to execution of the JNI method, as to whether the Java boundary crossover method is being executed. If so, then the execution stack may be compared to the invocation path of interest.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amar Devegowda, Venkataraghavan Lakshminarayanachar, Sathiskumar Palaniappan, Anshu Verma
  • Patent number: 9053068
    Abstract: Systems and methods for RDMA-based state transfer in virtual machine live migration. An example method may comprise: determining, by a first computer system, that a memory block has been modified by a virtual machine undergoing live migration from the first computer system to a second computer system; designating the modified memory block for transfer via a remote direct memory access (RDMA) adapter to the second computer system; selecting, asynchronously with respect to the designating, a memory block from a plurality of memory blocks designated for RDMA transfer to the second computer system, wherein a sum of an amount of pinned physical memory in the first computer system and a size of the selected memory block does not exceed a pre-defined value; registering the selected memory block with the RDMA adapter; and transmitting the selected memory block to the second computer system via the RDMA adapter.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 9, 2015
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Orit Wasserman