Low-Power Integrated-Circuit Signal Processor With Wide Dynamic Range
An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.
This application is a divisional of U.S. application Ser. No. 10/963,275, filed Oct. 12, 2004, which claims priority to provisional application Ser. No. 60/510,491 filed Oct. 10, 2003, the entirety of which are incorporated herein by reference.
FIELD OF THE DISCLOSUREThis disclosure relates to analog and mixed-signal integrated circuits (ICs) that require wide dynamic range while minimizing power consumption and power-supply complexity. More specifically, it relates to analog and mixed-signal ICs that require wide dynamic range while operating from low power-supply voltages, such as those typically encountered in battery-powered devices.
BACKGROUND OF THE DISCLOSUREThe dynamic range of analog information signal-processing circuits is inherently constrained by circuit noise, which obscures the smallest information signals, and power supply limitations, which limit the largest information signals that can be processed accurately. Many applications, especially portable, battery-powered audio products, require wide dynamic range and simultaneously low-power operation from low-voltage power supplies.
A particular class of applications involves conditioning the output voltage from a transducer or sensor. It is often advantageous to amplify the output voltage from such a source prior to further signal processing. It is also often advantageous to terminate such a source with a specific load impedance to maximize its signal-to-noise ratio and/or tailor its frequency response. These functions are typically accomplished by a preamplifier. In systems operating from low power-supply voltages, it is often desirable for the circuit to perform further signal processing on currents representative of the preamplifier output, rather than voltages. As is well known in the art, many current-mode, signal-processing circuits have been developed that minimize signal-related voltage excursions in the circuit. Such circuits, if designed to operate in class AB, also consume little power supply current under quiescent conditions. This makes them particularly desirable for battery-powered applications.
When such a signal-processing system is implemented in integrated circuit form, all sections of the circuitry typically operate from a single pair of power supply terminals. In this case, the power supply voltage of the entire IC must be set to accommodate the maximum preamplifier output voltage necessary to achieve the desired dynamic range. In systems with wide dynamic range requirements, this results in other parts of the circuitry, such as current-mode signal processing circuits, operating at a higher-than-necessary power-supply voltage.
SUMMARY OF THE DISCLOSUREIn accordance with the present approach, at least three separate power supply terminals are provided on an integrated circuit, at least one coupled solely to those portions of the circuit that must accommodate the widest signal-related voltage excursion and at least one coupled solely to those that experience substantially smaller signal-related voltage excursions.
The embodiment in
The embodiment in
The choice between an embodiment similar to
It should be understood that an embodiment which incorporates power supply terminals for both the positive and negative power supply connections of the circuitry requiring large signal voltage swings separate from the power supply connections to the rest of the integrated circuit may be implemented in accordance with teachings of this disclosure. Such an implementation would increase the maximum dynamic range available for voltage signals, at the expense of added power-supply complexity and an additional terminal on the integrated circuit 11.
Wireless microphone systems are one such application where such an integrated circuit, such as described in connection with
The signal-conditioning circuitry between the microphone capsule and an RF modulator in high-quality wireless microphone systems typically comprises a preamplifier, pre-emphasis and band-limiting filters, and a compressor circuit that functions as part of a syllabic companding system. The preamplifier serves to amplify the output voltage from the capsule (the audio signal), and to terminate it with an appropriate load impedance. This preamplifier should preferably have low input-referred noise so as to degrade the signal-to-noise ratio of the capsule output as little as possible. The preamplifier should also provide enough gain so that the noise contributions of subsequent circuitry in the signal path will be negligible. As is well known in the art, the pre-emphasis filters serve to further amplify high-frequency components of the audio signal so that they will be substantially higher in level than the noise added by the RF channel. A complementary de-emphasis filter in the receiver serves to restore flat overall frequency response in the audio bandwidth, and simultaneously attenuate the noise. The syllabic compander is another well-known approach to preserve dynamic range when noise is added to the signal of interest, in this case by the RF channel. Typically, such systems include a compressor circuit ahead of the noisy channel, and a complementary expander at the output of the noisy channel. A typical compressor circuit includes, at a minimum, a variable-gain element and a level detector. The gain of the variable-gain element in the compressor circuit is varied in response to the output of the level detector such that gain is decreased as the level of the signal of interest increases, and the gain is increased as the level of the signal of interest decreases. This serves to keep the signal of interest substantially higher in amplitude than the additive noise of the channel, and to minimize any occasions when the signal of interest may exceed the maximum possible amplitude that the channel can accommodate without excessive distortion. The expander circuit functions in a complementary fashion to restore the original dynamics to the signal of interest.
Current-mode compressor block 3 receives a positive power-supply voltage Vcc via terminal 5. Compressor block 3 has a negative power supply terminal connected to a reference potential, or ground, via terminal 9. Current-mode compressor block 3 comprises at a minimum a variable-gain element and a level detector. The gain of the variable-gain element in the compressor circuit is varied in response to the output of the level detector such that gain is decreased as the level of the signal of interest increases, and the gain is increased as the level of the signal of interest decreases. The output voltage from preamplifier 2 is coupled to the input of current-mode compressor block 3 via current-to-voltage conversion resistor R1 and ac coupling capacitor C1. AC coupling capacitor C1 blocks dc currents that would result from the differing dc bias potentials at terminals 4 and 7. The variable-gain element in compressor 3 receives an input current via terminal 7. Input terminal 7 is preferably a low-impedance virtual ground with a dc bias voltage between Vcc and ground. The output voltage from preamplifier 2 is coupled to the input of current-mode compressor block 3 via current-to-voltage conversion resistor R1 and ac coupling capacitor C1. Ac coupling capacitor C1 blocks dc currents that would result from the differing dc bias potentials at terminals 4 and 7. Resistor R2 and capacitor C2 forms a type of preemphasis network that increases the level of input currents in the variable gain block of compressor 3 at high frequencies.
The output current of the variable gain element in current-mode compressor block 3 is coupled to the inverting input of current-to-voltage conversion opamp 11, which is externally accessible through terminal 10. The output of the opamp 11 is externally accessible through the terminal 12. The non-inverting input of opamp 11 is internally connected to a reference voltage, Vref. The latter is preferably between positive supply voltage Vcc and ground. The external current-to-voltage conversion resistor R3 is connected between the terminal 10 and the terminal 12, thus forming a feedback resistor for the opamp 11, and determines the scaling of the output voltage produced in response to and as a function of the output current from compressor block 3. As is well known in the art, this configuration of feedback through the resistor R3 around opamp 11 creates a low-impedance virtual ground at the inverting input of opamp 11. Note that since the output voltage produced by opamp 11 is compressed due to the action of compressor block 3, the output voltage swing may be substantially less than that at the output of preamplifier 2 without loss of dynamic range. Thus, in this embodiment, opamp 11 can operate between supply voltage Vcc and ground.
The output of opamp 11 is coupled to the detector input of current-mode compressor block 3 at the terminal 16 via voltage-to-current conversion resistor R4 and ac coupling capacitor C4. Detector input terminal 16 is preferably a low-impedance virtual ground with a dc bias potential between Vcc and ground. Resistor R4 and capacitor C4 function similarly to resistor R1 and capacitor C1. As is well known in the art, the level detectors utilized in syllabic companders respond to a time-weighted average of some measure of the magnitude of the signal of interest. Capacitor C3, connected between compressor block 3 and ground via terminal 15, along with internal circuitry, implements the large averaging time constant for the detector as is well known. For syllabic companding of audio-band signals, the time constant is preferably on the order of several 10's of milliseconds, which can require capacitances that are impracticably large for integration. Alternatively, for other applications it may be possible to include these capacitances and resistances as a part of the integration.
In the embodiment of
Current-output expander 18 receives a positive power-supply voltage Vcc via terminal 5. Current-output expander 18 preferably has a negative power supply terminal connected to a reference potential, or ground, via terminal 9. Current-output expander 18 comprises at a minimum a variable-gain element and a level detector. The gain of the variable-gain element in the expander circuit is varied in response to the output of the level detector such that gain is increased as the level of the signal of interest increases, and the gain is decreased as the level of the signal of interest decreases. Current-output expander 18 receives an input signal at terminal 1. This input signal could be in either current or voltage form, since the input signal will be expanded, and thus will require substantially less total excursion than the expanded output voltage at terminal 14.
As is well known in the art, the level detectors utilized in syllabic expanders respond to a time-weighted average of some measure of the magnitude of the signal of interest. Capacitor C3, connected between current-output expander 18 and ground via terminal 15, along with internal circuitry, implements the large averaging time constant for the detector as is well known. For syllabic expanding of audio-band signals, the time constant is preferably on the order of several 10's of milliseconds, which can require capacitances that are impracticably large for integration. Alternatively, for other applications it may be possible to include these capacitances and resistances as a part of the integration.
The embodiments and practices described in this specification have been presented by way of illustration rather than limitation, and various modifications, combinations and substitutions may be effected by those skilled in the are without departure either in spirit or scope from this disclosure in its broader aspects and as set forth in the appended claims.
Claims
1. An integrated circuit containing at least one analog circuitry section for producing a final analog output information signal in response to a first analog input information signal, comprising:
- a first analog circuitry subsection that produces an intermediate analog output voltage in response to said first analog input information signal;
- a second analog circuitry subsection that accepts an intermediate analog input current proportional to said intermediate output voltage and produces said final output information signal in response to said intermediate analog input current;
- a first power-supply-voltage terminal coupled to said first analog circuitry subsection;
- a second power-supply-voltage terminal coupled to said second analog circuitry subsection; and
- a third power-supply-voltage terminal coupled to said first analog circuitry subsection and said second analog circuitry subsection;
- wherein the available dynamic range of said intermediate analog output voltage is designed to exceed the difference in voltage applied between said second and third power-supply terminals.
2. An integrated circuit according to claim 1, wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a negative voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a negative voltage is applied to the second power-supply terminal with respect to said third power-supply terminal.
3. An integrated circuit according to claim 2, including a capacitive voltage inverter for producing a negative power supply voltage in response to a positive power supply voltage applied to said third power-supply-voltage terminal wherein said negative power supply voltage is connected to said first power-supply-voltage terminal.
4. An integrated circuit according to claim 1, wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a positive voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a positive voltage is applied to the second power-supply terminal with respect to said third power-supply terminal.
5. An integrated circuit according to claim 4, including a charge pump means producing a first positive power supply voltage in response to a second positive power supply applied to said second power-supply-voltage terminal wherein said first power supply voltage is connected to said first power-supply-voltage terminal, and where said first positive power supply voltage is greater than said second power supply voltage.
6. An integrated circuit according to claim 1, wherein said second analog subsection is configured so as to produce an analog output current in response to said intermediate analog input current.
7. An integrated circuit according to claim 1, wherein said second analog subsection is configured so as to produce a final analog output voltage in response to said intermediate analog input current, and said final analog output voltage is substantially less in total excursion than said intermediate output voltage.
8. An integrated circuit according to claim 1, wherein said second analog subsection produces a final analog voltage or current that is a syllabically compressed version of said intermediate output voltage.
9. An integrated circuit according to claim 8, wherein said second analog subsection includes:
- a variable gain means for producing said final analog output voltage in response to said intermediate input current; and
- a level detector means for producing a gain control signal in response to said final analog output voltage;
- wherein the gain of said variable gain means responds to said gain control signal such that said gain is decreased in response to an increase in said final analog output voltage or current and said gain is increased in response to a decrease in said final analog output voltage or current.
10. An integrated circuit according to claim 8, wherein said second analog subsection includes:
- a variable gain stage for producing said final analog output voltage in response to said intermediate input current; and
- a level detector for producing a gain control signal in response to said final analog output voltage;
- wherein the gain of said variable gain stage responds to said gain control signal such that said gain is decreased in response to an increase in said intermediate input current and said gain is increased in response to a decrease in said intermediate input current.
11. An integrated circuit containing at least one analog circuitry section for producing a final analog output information signal in response to a first analog input information signal, comprising:
- a first analog circuitry subsection that produces an intermediate analog output voltage in response to said first analog input information signal;
- a second analog circuitry subsection that accepts an intermediate analog input current proportional to said intermediate output voltage and produces said final output information signal in response to said intermediate analog input current;
- a first positive power-supply-voltage terminal coupled to said first analog circuitry subsection;
- a second positive power-supply-voltage terminal coupled to said second analog circuitry subsection;
- a first negative power-supply-voltage terminal coupled to said first analog circuitry subsection; and
- a second negative power-supply-voltage terminal coupled to said second analog circuitry subsection;
- wherein the available dynamic range of said intermediate output voltage is designed to exceed the difference in voltage between said second positive and second negative power-supply terminals.
12. An integrated circuit according to claim 11, wherein said second analog subsection is configured so as to produce an analog output current in response to said intermediate analog input current.
13. An integrated circuit according to claim 11, wherein said second analog subsection is configured so as to produce a final analog output voltage in response to said intermediate analog input current, and said final analog output voltage is substantially less in total excursion than said intermediate output voltage.
14. An integrated circuit according to claim 13, wherein said second analog subsection is configured so as to produce an analog output current in response to said intermediate analog input current.
15. An integrated circuit according to claim 13, wherein said second analog subsection is configured so as to produce a final analog output voltage in response to said intermediate analog input current, wherein said final analog output voltage is substantially less in total excursion than said intermediate output voltage.
16. An integrated circuit according to claim 11, wherein said second analog subsection is configured so as to produce a final analog voltage or current that is a syllabically compressed version of said intermediate output voltage.
17. An integrated circuit according to claim 16, wherein said second analog subsection includes:
- a variable gain stage for producing said final analog output voltage in response to said intermediate input current; and
- a level detector for producing a gain control signal in response to said final analog output voltage;
- wherein the gain of said variable gain stage responds to said gain control signal such that said gain is decreased in response to an increase in said final analog output voltage or current and said gain is increased in response to a decrease in said final analog output voltage or current.
18. An integrated circuit according to claim 16, wherein said second analog subsection includes:
- a variable gain stage for producing said final analog output voltage in response to said intermediate input current; and
- a level detector for producing a gain control signal in response to said final analog output voltage;
- wherein the gain of said variable gain stage responds to said gain control signal such that said gain is decreased in response to an increase in said intermediate input current and said gain is increased in response to a decrease in said intermediate input current.
19. An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.
20. An integrated circuit containing at least one analog circuitry section for producing a final analog output voltage in response to a first analog input information signal, comprising:
- a first analog circuitry subsection that produces an intermediate analog output current in response to said first analog input information signal;
- a second analog circuitry subsection that accepts an intermediate analog input current proportional to said intermediate output current and produces said final output voltage in response to said intermediate analog input current;
- a first power-supply-voltage terminal coupled to said first analog circuitry subsection;
- a second power-supply-voltage terminal coupled to said second analog circuitry subsection; and
- a third power-supply-voltage terminal coupled to said first analog circuitry subsection and said second analog circuitry subsection;
- wherein the available dynamic range of said final analog output voltage is designed to exceed the difference in voltage applied between said first and third power-supply terminals.
21. An integrated circuit according to claim 20, wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a negative voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a negative voltage is applied to the second power-supply terminal with respect to said third power-supply terminal.
22. An integrated circuit according to claim 21, including a capacitive voltage inverter for producing a negative power supply voltage in response to a positive power supply voltage applied to said third power-supply-voltage terminal wherein said negative power supply voltage is connected to said second power-supply-voltage terminal.
23. An integrated circuit according to claim 20, wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a positive voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a positive voltage is applied to the second power-supply terminal with respect to said third power-supply terminal.
24. An integrated circuit according to claim 23, including a charge pump means producing a second positive power supply voltage in response to a first positive power supply applied to said first power-supply-voltage terminal wherein said second power supply voltage is connected to said second power-supply-voltage terminal, and where said second positive power supply voltage is greater than said first power supply voltage.
25. An integrated circuit according to claim 20, wherein said first analog subsection produces an intermediate analog current that is a syllabically expanded version of said first analog input information signal.
26. An integrated circuit according to claim 25, wherein said first analog subsection includes:
- a variable gain means for producing said intermediate analog current in response to first analog input information signal; and
- a level detector means for producing a gain control signal in response to said first analog input information signal;
- wherein the gain of said variable gain means responds to said gain control signal such that said gain is increased in response to an increase in said first analog input information signal and said gain is decreased in response to a decrease in said first analog input information signal.
Type: Application
Filed: Aug 12, 2008
Publication Date: Jan 22, 2009
Inventors: Gary Hebert (Shrewsbury, MA), Frank Thomas (Lunenburg, MA)
Application Number: 12/190,334
International Classification: H03L 5/00 (20060101);