Abstract: A semiconductor device according to an embodiment includes: a logic control circuit to which a signal is input; a timing information storage circuit configured to store timing information related to a start timing of correction processing that corrects a duty cycle of the signal; and a sequencer configured to start execution of the correction processing based on the timing information when a command related to the execution of the correction processing is received.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first circuit that includes a level shift transistor, a transmission line through which the signal output from the first circuit propagates, a second circuit that is connected the transmission line to receive the signal propagating through the transmission line, and a third circuit that is connected to the transmission line. The first circuit is connected to a power supply line to which a first voltage is supplied, and outputs, to the transmission line, a signal having an amplitude lower than the first voltage by a threshold voltage of the level shift transistor. The third circuit allows a current to flow from the transmission line when a voltage of the transmission line exceeds a set voltage.

Abstract: This disclosure relates to multi-phase oscillators for electronic systems. An example system includes multiple level translator circuits and a ring oscillator circuit that includes multiple outputs. Each level translator circuit includes a first input transistor, a second input transistor, and an output. The ring oscillator circuit includes multiple outputs, and each output of the ring oscillator has a different phase. An output of the ring oscillator is coupled to only one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit.

Abstract: An output driving circuit includes: a plurality of bias voltage generating circuits configured to generate a plurality of bias voltages; a switching control circuit; and an output voltage generating circuit. The switching control circuit is configured to selectively connect one bias voltage generating circuit of the plurality of bias voltage generating circuits to the output voltage generating circuit based on an output voltage. The output voltage generating circuit is configured to transmit and receive a parasitic current generated due to transition of the output voltage to and from the one bias voltage generating circuit selectively connected to the output voltage generating circuit through the switching control circuit.

Abstract: An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.

Abstract: The present disclosure relates to a high-side transistor drive circuit, a switching circuit and a controller of a DC/DC converter. A pulse generator generates a first pulse that becomes high level for a certain period of time in response to a first edge of an input signal and a second pulse that becomes high level for a certain period of time in response to a second edge of the input signal. An open drain circuit has a first output node that becomes low level in response to the first pulse and a second output node that becomes low level in response to the second pulse. A first current mirror circuit folds back a first current flowing through the first output node of the open drain circuit. A second current mirror circuit folds back a second current flowing through the second output node of the open drain circuit.

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

Abstract: A level shifter circuit is disclosed. The level shifter includes an input circuit configured to receive an input signal generated using a first power supply voltage level and generate, using the first power supply voltage level, a first control signal and a second control signal using the input signal. The level shifter further includes a shifter circuit configured to generate a first shifted signal and a second shifted signal using the first control signal, the second control signal, and second power supply voltage level different than the first power supply voltage level, and a selection circuit configured to select, using a value of a previous output signal and the second power supply voltage level, one of the first shifted signal or the second shifted signal to generate a current output signal.

Abstract: Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.

Abstract: An input/output circuit including: a pull-up driving circuit including at least one internal node coupled to a pad, the pull-up driving circuit configured to pull up a voltage of the pad to a Tx power supply voltage; and a pull-down driving circuit configured to pull down the voltage of the pad to a ground voltage. The pull-up driving circuit is configured to set a voltage level of the at least one internal node to a voltage level of a power supply voltage on the basis of a fixed voltage, when a voltage difference between the Tx power supply voltage and the voltage of the pad is greater than the voltage level of the power supply voltage.

Abstract: The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.

Abstract: Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.

Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.

Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

Abstract: In an optocoupler circuit, a first direction path, which transmits signals from a first to a second terminal, includes a first level shifter, a second level shifter, and a first optocoupler. The first level shifter receives a first input signal at the first terminal, and shifts a voltage level of the first input signal to a first shifted voltage level with respect to a first ground level in a first power domain, to provide a first shifted signal. The first optocoupler receives the first shifted signal, and generates a first optocoupler signal in response to the first shifted signal. The second level shifter receives the first optocoupler signal, and shifts a voltage level of the first optocoupler signal to a second shifted voltage level with respect to a second ground level in a second power domain, to provide a second shifted signal at the second terminal.

Abstract: A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.

Abstract: A voltage conversion circuit is provided. The circuit includes a first input module and a second input module. The first input module is connected to a first voltage and has a first input terminal for receiving an input signal and outputting a conversion signal, a high level of the input signal is a second voltage which is less than the first voltage; The second input module is connected to the first input module and has a second input terminal and an output terminal, the second input terminal is configured to receive a sampling signal, and the second input module is configured to sample the conversion signal according to the sampling signal and output an output signal via the output terminal.

Abstract: Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Abstract: Disclosed is a circuit for shifting a fixed ground level to a floating ground level in a motor drive system, including a floating ground high level line, a floating ground output level line, a floating ground low level line, a normal input level line, and a normal ground line that are used for characterizing an application detail. The circuit includes a controlled switching current source, a first upper current rectifier, a second upper current rectifier, a lower current rectifier, and an amplifying and shaping circuit that are integrated on a same substrate.

Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

Abstract: A method for measuring a received signal includes receiving a differential pair of signals by a differential pair of input nodes of a differential circuit. The method includes attempting to match a first current through a first node of the differential circuit corresponding to the differential pair of signals to a second current through a second node of the differential circuit corresponding to a feedback signal. The method includes generating an output measurement signal based on the first current and the second current. The output measurement signal has a level corresponding to an average amplitude of the differential pair of signals.

Abstract: An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

Abstract: A drive circuit and a memory chip are provided. The drive circuit includes: an amplification module, working under a first voltage domain; an output module, working under a second voltage domain, a power supply voltage of the second voltage domain being greater than a power supply voltage of the first voltage domain, and an output terminal of the output module being an output terminal of the drive circuit; a connection module, connected to an output terminal of the amplification module and an input terminal of the output module; and a feedback module, an input terminal of the feedback module being connected to the output terminal of the output module, and an output terminal of the feedback module being connected to an input terminal of the amplification module.

Abstract: There is described a pulse-triggered level shifter circuit comprising: i) a command circuit configured to shift a command input signal of a first voltage domain to a command output signal of a second voltage domain, the command circuit comprising: a) a command input stage for receiving the command input signal, and b) a command output stage for providing the command output signal; and ii) a feedback circuit coupled to the command circuit and configured to shift a feedback input signal of a third voltage domain to a feedback output signal of a forth voltage domain, the feedback circuit comprising: c) a feedback input stage for receiving the command output signal as the feedback input signal, and d) a feedback output stage for providing the feedback output signal. The command circuit and the feedback circuit are hereby integrated into one single level shifter circuit.

Abstract: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

Abstract: A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.

Abstract: According to one embodiment, a level shift circuit includes a first input terminal, a second input terminal, an output terminal, a first level shift unit, a first inverter, a second level shift unit, a second inverter, and first to fourth switching elements. The first level shift unit outputs a first output voltage and a reference voltage. The second level shift unit outputs the reference voltage and a second output voltage.

Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a cell array. The cell array includes an array of a plurality of string blocks. Among the plurality of local string blocks, one local string block includes a block selection transistor and remaining local string blocks do not include a block selection transistor. A gate terminal of the block selection transistor of the one local string block is connected to a block selection line. Signals of two word lines connected to two adjacent string blocks in the bit line direction are common signals. Signals of two block selection lines connected to the two adjacent string blocks are independent of each other.

Abstract: A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.

Abstract: A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.

Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

Abstract: An active pull-up circuit which is operated between an upper voltage and a lower voltage and which pulls up an intermediate node to the upper voltage in reaction to an input voltage of the pull-up circuit falling from the upper voltage to an intermediate voltage is described. The pull-up circuit comprises a first transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to the input voltage. The pull-up circuit comprises a second transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to a control node. In addition, the pull-up circuit comprises control circuitry configured to pull the control node to a voltage level of the intermediate node, subject to the input voltage falling from the upper voltage to the intermediate voltage.

Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.

Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

Abstract: A gate driving circuit includes: a plurality of driving stages, each driving stage configured to provide a gate signal to a corresponding gate line among a plurality of gate lines, wherein each of the plurality of driving stages includes: a first transistor electrically connected between a first clock terminal and a gate output terminal, the first transistor including a gate electrode electrically connected to a first node, the first clock terminal to receive a first clock signal; a second transistor configured to transmit a first carry signal to the first node; and a third transistor electrically connected between the first node and a first voltage terminal, the third transistor including a gate electrode electrically connected to the first voltage terminal, the first voltage terminal to receive a first voltage, wherein the gate output terminal is electrically connected to the corresponding gate line.

Abstract: A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M?1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M?1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M?1) reference voltages, At least two sense amplifiers of the (M?1) sense amplifiers have different sensing characteristics.

Abstract: An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

Abstract: There is provided an apparatus and method, the apparatus comprising a power input and a switch isolation circuit to provide isolation between the power input and a protected switch responsive to a timing signal. The switch isolation circuit comprises a switch isolation charge store, and a buffer circuit to receive power from the switch isolation charge store and coupled between the timing signal and the protected switch. The switch isolation circuit is configured to, in response to the timing signal having the first value, operate in a powered mode in which the switch isolation charge store receives power from the power input; and, in response to the timing signal having the second value, operate in an isolation mode in which the switch isolation charge store is isolated from the power input.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: A low voltage differential driver includes a first driver, a second driver, and an output driver. The output driver is configured to provide an output between a first output node and a second output node, and includes a current source, a first branch, and a second branch. The current source is configured to provide a source current. The current source is connected with a parallel arrangement of the first branch and the second branch. The first switch and the second switch are respectively controlled by a first switch circuit and a second switch circuit which together comprise the first driver. The third switch and the fourth switch are respectively controlled by a third switch circuit and a fourth switch circuit which together comprise the second driver. Each of the first to fourth switch circuits is connected between the upper node and the lower node.

Abstract: There is provide a current detection circuit including: a current detection unit that detects a control current flowing between a control terminal of a semiconductor element of voltage-controlled type having a current detection terminal, and a drive circuit; an overcurrent detection unit that detects an overcurrent in response to a sense current exceeding an overcurrent threshold value, the sense current flowing through the current detection terminal; and an adjustment unit that sets, based on a detection result of the current detection unit, the overcurrent threshold value in a transient period during turn on and turn off of the semiconductor element to be higher than the overcurrent threshold value in a period other than the transient period.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: Examples include a driver circuit for driving a voltage controlled electro-optical modulator. The driver circuit includes a supply input and an input for receiving the input voltage. The driving circuit further includes a level shifter circuit, which includes first and second capacitors and is electrically connected to the input, and a voltage distribution circuit, which is electrically connected between the level shifter circuit and an output of the driver circuit for providing the output voltage. The level shifter circuit is configured to generate, based on the input voltage and using the first capacitor, a first voltage varying between the positive supply voltage level and a positive first level that is greater than the positive supply voltage level. The level shifter circuit is also configured to generate, based on the input voltage and using the second capacitor, a second voltage varying between ground and a negative second level.

Abstract: Embodiments of this application disclose a control method for a photovoltaic power generation system and a photovoltaic power generation system, to reduce a photovoltaic energy loss. The method includes: presetting, by the photovoltaic power generation system, an upper limit value for each converter in the photovoltaic power generation system, where the upper limit value is a maximum voltage value of an output voltage to ground of the converter, and the output voltage to ground is a voltage difference between a positive output end of the converter and a ground point of the photovoltaic power generation system; and limiting, by the photovoltaic power generation system, an output voltage to ground of a target converter based on an upper limit value corresponding to the target converter, where the target converter may be any converter in the photovoltaic power generation system.

Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.

Abstract: A ferroelectric computation unit includes a first ferroelectric switching device that includes a first ferroelectric material portion and generates a digital output signal, and a second ferroelectric switching device that includes a second ferroelectric material portion and generates an analog output signal. An output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to a gate electrode of another of the first ferroelectric switching device and the second ferroelectric switching device to provide hybrid response characteristics of stochastic digital switching and analog switching.

Abstract: An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.