Interstage Coupling (e.g., Level Shift, Etc.) Patents (Class 327/333)
  • Patent number: 11121711
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 11121713
    Abstract: An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: ANALOG DEVICES, INC.
    Inventors: Scott G. Bardsley, Huseyin Dinc
  • Patent number: 11107806
    Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 31, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, Mariano Dissegna
  • Patent number: 11094280
    Abstract: The present disclosure relates to a level shifter and a display device using the same, and the level shifter includes a first transistor configured to increase a voltage of an output signal, a second transistor configured to lower a voltage of the output signal, a first driver configured to vary a gate voltage of the first transistor in response to a first Vgs signal being varied within a transition time of the output signal, and a second driver configured to vary a gate voltage of the second transistor in response to a second Vgs signal being varied within a transition time of the output signal.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 17, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Hoon Jang, Juno Hur, Dong Ju Kim, Soon Dong Cho
  • Patent number: 11082045
    Abstract: A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 3, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jun Yang, Jian Liu
  • Patent number: 11075618
    Abstract: A plus width modulation (PWM) signal generator is disclosed. The PWM signal generator includes a first signal generator providing a first signal, an output terminal, a first voltage generating circuit including connected to the first voltage generating circuit for providing a first present voltage according to the first signal, and a second voltage generating circuit connected to the first signal generator for providing a second present voltage according to the first signal. The first present voltage is earlier supplied to the output terminal than the second preset voltage, and after the first preset voltage continuously is provided for a period of preset time, the first voltage generating circuit stops providing the first preset voltage.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 27, 2021
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Chih-Lien Chang, Chia-Chien Li
  • Patent number: 11063510
    Abstract: The feedback loop of a switching power converter controller is provided with an averaging circuit that averages either an output voltage, an error signal, or a control voltage. Regardless of which feedback signal is averaged, the averaging occurs over a first cycle of a rectified input voltage to form an averaged signal that is used by the feedback loop in a subsequent cycle of the rectified input voltage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 13, 2021
    Assignee: DIALOG SEMICONDUCTOR INC.
    Inventors: Laiqing Ping, Xiaoyan Wang, Nan Shi
  • Patent number: 11063578
    Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Patent number: 10992290
    Abstract: A level shifter for outputting an output voltage having a voltage level range different from a voltage level range of a received input voltage is disclosed. The level shifter includes: a current mirror configured to copy a reference current flowing through a first mirror transistor to a second mirror transistor; a current mirror control circuit electrically connected to the current mirror by a sink node and including a plurality of control transistors configured to control the current mirror; and an output circuit configured to output an output voltage based on a voltage level of the sink node, wherein a first control transistor of the plurality of control transistors receives the output voltage fed back to a gate terminal of the first control transistor, and a second control transistor of the plurality of control transistors receives an inverted output voltage fed back to a gate terminal of the second control transistor.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-min Kim, Kyung-hoon Lee, Eun-seok Shin, Michael Choi
  • Patent number: 10984748
    Abstract: This disclosure provides a gate driving circuit, which comprises: first P-channel, second P-channel, first N-channel and second N-channel transistors, each has a gate, a source, a drain, and a base connected to the source; an output terminal electrically connected to the drains of the second N-channel and P-channel transistors; wherein the source of the first P-channel transistor is connected to a first voltage source, and a first voltage is applied to its gate; the source of the first N-channel transistor is connected to a second voltage source, and a second voltage is applied to its gate; the source of the second P-channel transistor is connected to the drain of the first P-channel transistor, and a third voltage is applied to its gate; the source of the second N-channel transistor is connected to the drain of the first N-channel transistor, and a control voltage is applied to its gate.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 20, 2021
    Assignee: SITRONIX TECHNOLOGY CORPORATION
    Inventor: Hung-Yu Lu
  • Patent number: 10985738
    Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement of transistors is opposite the second series arrangement of transistors. The output of the first series arrangement of transistors is coupled to a first node and selectively couples the first node to a first voltage based on an input signal. The output of the second series arrangement of transistors is coupled to a second node and couples the second node to the first voltage based on an input signal. The first node and the second node are coupled to the first voltage at different times. The series arrangements of transistors enables faster level shifting over conventional level shifters.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 10930981
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Patent number: 10911049
    Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hari Giduturi
  • Patent number: 10879921
    Abstract: An integrated circuit is provided that includes an output stage circuit. The output stage circuit includes an input node for receiving a digital input signal, a supply voltage node for receiving a supply voltage signal, a digital to analog convertor for converting the digital signal, an amplifier for amplifying the converted signal, a first/second and optionally third voltage regulator generating a first/second and optionally third voltage signal, and a greatest-voltage selector circuit for providing power to the amplifier. Two different voltages are provided to the DAC. The output signal can be a SENT signal. The circuit is highly robust against power-interruptions and EMI.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Melexis Technologies SA
    Inventors: Matthijs Pardoen, Cesare Ghezzi, Kevin Fahrni
  • Patent number: 10879884
    Abstract: A buffer circuit includes a current mode circuit configured to generate output signals by converting a current path depending on input signals and configured to correct a swing width of the output signals by adjusting a current amount depending on a level of a compensation signal. The buffer circuit also includes a compensation signal generation circuit configured to detect a swing width variation of the output signals and configured to generate the compensation signal for correcting a swing width of the output signals to conform to a target value, depending on a detected swing width.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Gi Moon Hong
  • Patent number: 10862484
    Abstract: A voltage level translator translates signals between first and second voltage domains. An output buffer for a channel thereof includes a first plurality of PFETs and a first plurality of NFETS that are coupled to provide staggering of the output signal. A supply difference sensing circuit can disable staggering when an input voltage supply is greater than or equal to a VCCI trigger for the output voltage supply.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 8, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Amar Kanteti
  • Patent number: 10855281
    Abstract: A wide supply range digital level shifter circuit shifts between a variable desired output voltage ranging from a first voltage level and a second voltage level. The wide supply range digital level shifter circuit includes a latch circuit, a first bleeder circuit, and a second bleeder circuit. The latch circuit receives the first voltage level and the second voltage level, and includes first and second clocked differential switches. The first bleeder circuit is connected between the second voltage rail and the first differential switch and is configured to receive a first digital input voltage. The second bleeder circuit is connected between the second voltage rail and the second differential switch and is configured to receive a second digital input voltage. The first and second bleeder circuits isolate the first and second digital input voltages from the variable desired output voltage.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 1, 2020
    Assignee: RAYTHEON COMPANY
    Inventor: Christian M. Boemler
  • Patent number: 10848156
    Abstract: A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Reddy Mudimela Venkata, Sneha Shetty, Sankar Debnath
  • Patent number: 10833584
    Abstract: Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: November 10, 2020
    Assignee: Empower Semiconductor, Inc.
    Inventors: Parag Oak, Timothy A. Phillips
  • Patent number: 10833678
    Abstract: In a first example a voltage level-shifting device includes a level-shifting stage circuit. The level-shifting stage circuit includes a first level-shifting inverter circuit to invert a buffered input signal to drive a first internal node, a second level-shifting inverter circuit to invert a buffered inverted input signal to drive a second internal node, a first pre-drive circuit that receives the buffered inverted input signal, and drives the second internal node based on the state of the buffered inverted input signal, and a second pre-drive circuit that receives the buffered input signal, and drives the first internal node based on the state of the buffered input signal.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 10, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Paul Armstrong
  • Patent number: 10823765
    Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chow Peng, Chung-Peng Hsieh
  • Patent number: 10790826
    Abstract: A level shifter is disclosed. The level shifter comprises a pulse generating circuit, configured to receive an input signal, and generate a plurality of first-level pulses having a pulse width shorter than a pulse width of the input signal, wherein the input signal swings over a first voltage domain; a pulse transforming circuit, coupled to the pulse generating circuit, configured to generate a plurality of second-level pulses corresponding to the plurality of first-level pulses; and a latching circuit, coupled to the pulse transforming circuit, configured to generate an output signal by latching a status of the output signal in response to the plurality of second-level pulses, wherein the output signal swings over a second voltage domain.
    Type: Grant
    Filed: May 19, 2019
    Date of Patent: September 29, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Hsiang-Yi Chiu
  • Patent number: 10790025
    Abstract: According to one embodiment, a semiconductor memory includes: a memory cell array provided in a first layer above a semiconductor substrate and including a plurality of memory cells; a first word line coupled to a first memory cell of the plurality of memory cells; a driver generating a voltage applied to the first word line; a first transistor including one end coupled to the first word line and the other end coupled to the driver; a first transfer gate line coupled to a gate of the first transistor and including a portion passing through the first layer, a second layer between the semiconductor substrate and the first layer, and a third layer above the first layer; and a first level shifter applying a voltage to the first transfer gate line.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Masashi Yamaoka
  • Patent number: 10784842
    Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 22, 2020
    Assignee: Arm Limited
    Inventors: Seshagiri Rao Bogi, Vinay Chenani, Biswanath Nayak, Vijaya Kumar Vinukonda
  • Patent number: 10756644
    Abstract: Controlling gate-source voltage with a gate driver in a secondary-side controller in a secondary-controlled converter is described. In one embodiment, an apparatus includes a provider field effect transistor (FET) coupled to a transformer and the secondary-side controller coupled to the transformer. The gate driver is integrated on the secondary-side controller and is configured to control the gate-source voltage and slew rate of the secondary-side FET.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 25, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventor: Pulkit Shah
  • Patent number: 10715146
    Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Ernest Finn
  • Patent number: 10715364
    Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 10705148
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 7, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Patent number: 10693301
    Abstract: A semiconductor device including a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 23, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Patent number: 10686411
    Abstract: Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.
    Type: Grant
    Filed: June 22, 2019
    Date of Patent: June 16, 2020
    Inventors: Zhanming Li, Yue Fu, Yan-Fei Liu
  • Patent number: 10686436
    Abstract: Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 16, 2020
    Inventors: Zhanming Li, Yue Fu, Yan-Fei Liu
  • Patent number: 10685727
    Abstract: A level shifter includes a first output terminal and a second output terminal. After an output signal in a high level state is outputted from the first output terminal and an inverted output signal in a low level state is outputted from the second output terminal, a weak driving circuit is connected between the first output terminal and a power supply voltage, and a strong driving circuit is connected between the second output terminal and the power supply voltage. After the output signal in the low level state is outputted from the first output terminal and the inverted output signal in the high level state is outputted from the second output terminal, the strong driving circuit is connected between the first output terminal and the power supply voltage, and the weak driving circuit is connected between the second output terminal and the power supply voltage.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 16, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Tzu-Neng Lai
  • Patent number: 10673660
    Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pier Andrea Francese, Ilter Oezkaya, Alessandro Cevrero
  • Patent number: 10666259
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Patent number: 10667342
    Abstract: A configurable light source driver device includes circuitry that detects the presence of a resistor when connected to a terminal of the device and automatically configures the device to operate as a differential driver circuit with low EMI emission and a level of circuit stability that is selected on the basis of parasitic impedance conditions of the differential driver circuit. When the terminal is left unconnected, the configurable light source driver device automatically configures itself to operate as a single ended driver circuit with low power consumption and a different level of circuit stability that is selected on the basis of parasitic impedance conditions of the single ended driver circuit. Furthermore, the configurable light source driver device can include a pulse width adjustment circuit for modifying certain operating characteristics of each of the differential driver circuit and the single ended driver circuit.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 26, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Milos Davidovic, Robert Swoboda
  • Patent number: 10644679
    Abstract: A level shift circuit includes a pulse signal generation unit generating first and second pulse signals with respect to an input signal, a first level conversion unit converting the first pulse signal at a first voltage to a third pulse signal at a second voltage, a second level conversion unit converting the second pulse signal at the first voltage to a fourth pulse signal at the second voltage, and a flip flop circuit making an output signal at the second voltage rise according to the third pulse signal, and making the output signal at the second voltage fall according to the fourth pulse signal. The pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal when the input signal rises and the second pulse signal when the input signal falls, based on a non-matching comparison result.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koichi Takeda
  • Patent number: 10630268
    Abstract: A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: April 21, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsin-Cheng Hsu, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 10622975
    Abstract: A voltage translation device is disclosed. The voltage translation device includes an input circuit, operating in a first voltage domain, that is configured to receive an input signal. The voltage translation device also includes an output circuit, operating in a second voltage domain, that includes a latch circuit. The voltage translation device also includes a driver circuit that is controlled by the input circuit to pass a voltage from the first voltage domain to the latch circuit in order to trigger the latch circuit to output an output signal in the second voltage domain according to the input signal in the first voltage domain.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 14, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Lei Huang
  • Patent number: 10622994
    Abstract: A driver for a semiconductor switching device can be configured to step down a supply voltage to generate a first drive voltage. The driver can also generate a second drive voltage equal to the potential difference between the supply voltage and the first drive voltage. The driver can supply the first drive voltage to a control gate of the semiconductor switching device during a first state of a control signal, and a reverse polarity of the second drive voltage during a second state of the control signal.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 14, 2020
    Assignee: Vishay-Siliconix, LLC
    Inventor: Sanjay Havanur
  • Patent number: 10615796
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for level shifting an input signal ranging between certain voltage levels to generate an output signal ranging between other voltage levels with low power, high speed, and immunity to noise. One example level-shifting circuit generally includes a node for receiving an input signal ranging between a first voltage level and a second voltage level, a first circuit path coupled to the node and configured to level shift the input signal to generate an output signal ranging between a third voltage level and a fourth voltage level, a pulse generator coupled to the node and configured to generate a pulse based on a transition in the input signal between the first and second voltage levels, and a second circuit path connected in parallel with the first path and configured to temporarily short the first path based on the generated pulse.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhiqing Zhang, Brett Walker, Chi Fan Yung, Justin Philpott, Joseph Duncan
  • Patent number: 10608630
    Abstract: A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 31, 2020
    Assignee: XILINX, INC.
    Inventors: Ionut C. Cical, Diarmuid Collins, John K. Jennings
  • Patent number: 10593410
    Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 17, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carmelo Paolino, Antonino Conte, Anna Rita Maria Lipani
  • Patent number: 10566355
    Abstract: A semiconductor device with reduced power consumption and a display device including the semiconductor are provided. The semiconductor device generates a bias voltage that is to be supplied to a buffer amplifier. When the display device displays a still image, a data signal for updating the image need not be supplied from the buffer amplifier to a pixel array in the next frame; therefore, the circuit is configured so that the buffer amplifier is brought into a standby state (temporarily stopped). Specifically, input of a reference current from a BGR circuit to the semiconductor is stopped and a bias voltage is applied from the semiconductor device to the buffer amplifier to temporarily stop the operation of the buffer amplifier.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 10560084
    Abstract: According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Toshihiro Yagi
  • Patent number: 10536148
    Abstract: Some demonstrative embodiments include a level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first voltage domain to a high logic level and a low logic level of a second voltage domain, respectively.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 14, 2020
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Valentin Lerner, Dan Pollak
  • Patent number: 10498315
    Abstract: A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Eduardas Jodka, Julian Becker
  • Patent number: 10497698
    Abstract: An object is to provide a technique for enhancing the breakdown voltage of a semiconductor device. A semiconductor circuit includes a first resistor, a second resistor, a third resistor, a MOSFET, and an inverter. The first resistor, the second resistor, and the third resistor are connected in series between a power supply and a ground corresponding to the reference voltage of a low-side circuit. The MOSFET is connected to the third resistor in parallel between the second resistor and the ground, and has a gate electrically connected to the low-side circuit. The inverter is electrically connected between a connection point and the high-side circuit, the connection point being located between the first resistor and the second resistor.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: December 3, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Manabu Yoshino
  • Patent number: 10490263
    Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yangsyu Lin, Chiting Cheng
  • Patent number: 10483950
    Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Patent number: 10483975
    Abstract: An integrated circuitry includes a first circuit, a second circuit, and a voltage conversion circuit. A first power supply positive terminal of the first circuit is electrically coupled to a power source. The second circuit is electrically coupled in series with the first circuit and the power source. A second power supply positive terminal of the second circuit is electrically coupled to a first power supply negative terminal of the first circuit. The voltage conversion circuit is electrically coupled between the first circuit and the second circuit so as to receive a signal from the first circuit or the second circuit. The voltage conversion circuit converts a voltage value of the signal according to a first low potential signal of the first power supply negative terminal and a second low potential signal of a second power supply negative terminal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 19, 2019
    Assignee: DigWise Technology Corporation, LTD
    Inventors: Jingjie Wu, Chih-Wen Yang, Chung-Ting Yeh