Interstage Coupling (e.g., Level Shift, Etc.) Patents (Class 327/333)
  • Patent number: 11558043
    Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: January 17, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
  • Patent number: 11552639
    Abstract: A low voltage differential driver includes a first driver, a second driver, and an output driver. The output driver is configured to provide an output between a first output node and a second output node, and includes a current source, a first branch, and a second branch. The current source is configured to provide a source current. The current source is connected with a parallel arrangement of the first branch and the second branch. The first switch and the second switch are respectively controlled by a first switch circuit and a second switch circuit which together comprise the first driver. The third switch and the fourth switch are respectively controlled by a third switch circuit and a fourth switch circuit which together comprise the second driver. Each of the first to fourth switch circuits is connected between the upper node and the lower node.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: January 10, 2023
    Assignee: NXP USA, INC.
    Inventors: Yongqin Liang, Lei Tian, Xiaowen Wu, Jingjian Zhang
  • Patent number: 11545970
    Abstract: There is provide a current detection circuit including: a current detection unit that detects a control current flowing between a control terminal of a semiconductor element of voltage-controlled type having a current detection terminal, and a drive circuit; an overcurrent detection unit that detects an overcurrent in response to a sense current exceeding an overcurrent threshold value, the sense current flowing through the current detection terminal; and an adjustment unit that sets, based on a detection result of the current detection unit, the overcurrent threshold value in a transient period during turn on and turn off of the semiconductor element to be higher than the overcurrent threshold value in a period other than the transient period.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 3, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kazumi Takagiwa
  • Patent number: 11545105
    Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Atsushi Umezaki
  • Patent number: 11536990
    Abstract: Examples include a driver circuit for driving a voltage controlled electro-optical modulator. The driver circuit includes a supply input and an input for receiving the input voltage. The driving circuit further includes a level shifter circuit, which includes first and second capacitors and is electrically connected to the input, and a voltage distribution circuit, which is electrically connected between the level shifter circuit and an output of the driver circuit for providing the output voltage. The level shifter circuit is configured to generate, based on the input voltage and using the first capacitor, a first voltage varying between the positive supply voltage level and a positive first level that is greater than the positive supply voltage level. The level shifter circuit is also configured to generate, based on the input voltage and using the second capacitor, a second voltage varying between ground and a negative second level.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: December 27, 2022
    Assignee: IMEC VZW
    Inventor: Davide Guermandi
  • Patent number: 11527892
    Abstract: Embodiments of this application disclose a control method for a photovoltaic power generation system and a photovoltaic power generation system, to reduce a photovoltaic energy loss. The method includes: presetting, by the photovoltaic power generation system, an upper limit value for each converter in the photovoltaic power generation system, where the upper limit value is a maximum voltage value of an output voltage to ground of the converter, and the output voltage to ground is a voltage difference between a positive output end of the converter and a ground point of the photovoltaic power generation system; and limiting, by the photovoltaic power generation system, an output voltage to ground of a target converter based on an upper limit value corresponding to the target converter, where the target converter may be any converter in the photovoltaic power generation system.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 13, 2022
    Assignee: HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD.
    Inventors: Yongbing Gao, Guilei Gu
  • Patent number: 11522541
    Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 6, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Joi Okugi, Daisuke Katori, Satoru Suzuki, Satoshi Kamiya
  • Patent number: 11514982
    Abstract: A ferroelectric computation unit includes a first ferroelectric switching device that includes a first ferroelectric material portion and generates a digital output signal, and a second ferroelectric switching device that includes a second ferroelectric material portion and generates an analog output signal. An output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to a gate electrode of another of the first ferroelectric switching device and the second ferroelectric switching device to provide hybrid response characteristics of stochastic digital switching and analog switching.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11474964
    Abstract: A configurable input/output device includes a plurality of input/output terminals, a routing module, and a first universal input/output channel. The input/output terminals are connected a plurality of field devices. The input/output terminals receive a plurality of input signals from the field devices, and output a plurality of output signals to the field devices. At least two of the input signals are different, at least two of the output signals are different, and at least two the field devices are different. The routing module is connected to the input/output terminals. The first universal input/output channel is connected to the routing module. The routing module controls connections between the first universal input/output channel and the input/output terminals. The routing module also controls the transceiving sequence for the input signals and the output signals.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 18, 2022
    Assignee: MOXA INC.
    Inventor: Kun-Nan Wu
  • Patent number: 11476847
    Abstract: An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 18, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Jun Fukudome, Kazuya Hokazono, Mitsutaka Hano
  • Patent number: 11463084
    Abstract: A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: October 4, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thanapandi Ganesan, Prateek Mishra, Jagadeesh Anathahalli Singrigowda, Dhruvin Devangbhai Shah, Animesh Jain, Girish Anathahalli Singrigowda
  • Patent number: 11444608
    Abstract: A level shifter includes: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state; a first NMOS sensing transistor and a second NMOS sensing transistor; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 11437996
    Abstract: The present disclosure relates to a dynamic control conversion circuit, which includes: a dynamic control unit configured to generate a dynamic control signal according to a received input signal; a first semiconductor switch, a control terminal of the first semiconductor switch is connected with a first signal output terminal of the dynamic control unit, and a first terminal of the first semiconductor switch is connected with a first voltage terminal; a second semiconductor switch, a control terminal of the second semiconductor switch is connected with a second signal output terminal of the dynamic control unit; and a circuit output unit having a first control terminal connected with a second terminal of the first semiconductor switch and a first terminal of the second semiconductor switch, and a second control terminal connected with a second terminal of the second semiconductor switch and a third signal output terminal of the dynamic control unit.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 6, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: WeiBing Shang, Sungsoo Chi, Ying Wang
  • Patent number: 11437997
    Abstract: A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 6, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Abhijit Kumar Das
  • Patent number: 11423824
    Abstract: The present application discloses a gate driver circuit of a display panel, a driving method therefor and a display circuit. The gate driver circuit of a display panel includes a multi-stage cascaded shift register, where an any-stage shift register includes: a charging circuit, a pull-down circuit for controlling to pull down a potential of an output terminal of the charging circuit to a low level in a non-scanning time, and an output control circuit electrically coupled to the output terminal of the charging circuit for receiving an initial gate scanning signal; the output control circuit is connected to an enable signal and controls the output of the gate scanning signal according to the enable signal.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: August 23, 2022
    Assignees: CHUZHOU HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: Yunqin Hu, Lidan Ye
  • Patent number: 11405039
    Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first NMOS transistor and a first PMOS transistor in series with a first input node and a negative amplified voltage, and the second leg includes a second NMOS transistor and a second PMOS transistor in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: August 2, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hiroki Yabe
  • Patent number: 11405038
    Abstract: The present disclosure discloses a level shifter circuit and a display panel. The level shifter circuit includes a level shifter module, a compare module connected to the level shifter module. The level shifter module includes a level shifter unit, a control unit connected to the level shifter unit. The level shifter unit receives a first voltage signal and a second voltage signal and generates a level shifter result signal according to the first voltage signal and the second voltage signal. The compare module is configured to compare a voltage corresponding to the level shifter result signal with a reference voltage at a predetermined time and generate a comparison result. The control unit stops the shifter unit when the voltage corresponding to the level shifter result signal is less than the reference voltage. The present disclosure prevents the display panel from being damaged by short circuiting.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 2, 2022
    Inventors: Wenfang Li, Xianming Zhang
  • Patent number: 11405037
    Abstract: A driver circuit of a voltage translator includes a bias voltage generator, a drive voltage generator, an output voltage generator, and a filter circuit. The bias voltage generator is configured to receive a supply voltage, a first input voltage, and a feedback voltage, and generate a bias voltage. The feedback voltage controls an amplitude of the bias voltage. The drive voltage generator is configured to receive the supply voltage, the first input voltage, and the bias voltage, and generate a drive voltage. The output voltage generator is configured to receive the supply voltage, a second input voltage, and the drive voltage, and generate an output voltage. The drive voltage controls a slew rate of the output voltage. The filter circuit is configured to receive the output voltage, and generates and provides the feedback voltage to the bias voltage generator.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 2, 2022
    Assignee: NXP B.V.
    Inventor: Chandra Prakash Tiwari
  • Patent number: 11387829
    Abstract: An integrated circuit and a signal transmission method thereof are provided. The integrated circuit includes a first power domain, a second power domain, and a weakly pull circuit. The first power domain is powered by a first power source, the second power domain is powered by a second power source, and the second power domain transmits a signal to the first power domain through a transmission path. The weakly pull circuit is signally connected to the transmission path. When the second power domain is in a power-off mode, the weakly pull circuit maintains the transmission path stably at a logic level to prevent unknown signals from entering the first power domain from the second power domain and disturbing the normal operation of the first power domain.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Lien-Hsiang Sung
  • Patent number: 11387818
    Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Patent number: 11368155
    Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: June 21, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Dzung T. Tran, Shibly S. Ahmed
  • Patent number: 11368152
    Abstract: The present disclosure discloses a source signal output circuit and an inverter thereof. The inverter is configured to provide a multiplexer with a control signal having a full range for selecting a source signal and to output the control signal having the full range by using elements operating in a low voltage range. Therefore, the present disclosure has an advantage in that it can fabricate a driving circuit having a small area at a low process cost.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: June 21, 2022
    Inventors: Young Tae Kim, Young Bok Kim, Taiming Piao, Dong Hun Lee
  • Patent number: 11368112
    Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ganapathi Shankar Krishnamurthy, Venkata Naresh Kotikelapudi
  • Patent number: 11355495
    Abstract: A semiconductor device includes first to sixth transistors of enhancement type. The first and fourth transistors are of p-channel type. The second, third, fifth and sixth transistors are of n-channel type. A breakdown voltage of the third transistor is lower than a breakdown voltage of the second transistor. A breakdown voltage of the sixth transistor is lower than a breakdown voltage of the fifth transistor. The first to third transistors are connected in series between a first power supply potential and a second power supply potential lower than the first power supply potential. The fourth to sixth transistors are connected in series between the first power supply potential and the second power supply potential.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 7, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hidekazu Inoto, Osamu Takata, Naozumi Terada, Hiroyoshi Kitahara
  • Patent number: 11322951
    Abstract: A battery management system may include: a plurality of voltage detection integrated circuits; and a battery controller configured to control charge and discharge of a high voltage battery based on a cell voltage detection result received from the voltage detection integrated circuits, and each of the detection integrated circuits includes: a cell voltage detection circuit configured to detect a voltage of at least one corresponding cell among a plurality of cells constituting the high voltage battery; first and second interfaces configured to communicate between different voltage detection integrated circuits in the detection integrated circuits; a plurality of first terminals connected with a first power source which supplies an operation voltage of the cell voltage detection circuit and the first interface; a plurality of second terminals configured to receive an operation voltage of a different voltage detection integrated circuit connected therewith through the second interface; and a level shifter confi
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: May 3, 2022
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Wonkyoung Cho, Yongchun Kim
  • Patent number: 11315496
    Abstract: A shift register unit and a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, connected to a pull-up node, and configured to charge the pull-up node according to an input signal; an output circuit, connected to the pull-up node and an output terminal, and configured to output an output signal to the output terminal under control of a voltage of the pull-up node; a reset circuit, connected to the pull-up node, and configured to reset the pull-up node; and a reset signal control circuit, connected to a first reset terminal and the reset circuit, and configured to generate and output a reset control signal according to a reset control input signal and a reset signal provided by the first reset terminal; the reset control signal is configured to control the reset circuit to perform a reset operation.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 26, 2022
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lijun Xiao, Zhenguo Tian, Yanan Zhao, Shaohong Gao, Zhiyou Liu, Ming Deng
  • Patent number: 11309891
    Abstract: The present application is directed to a level shifting circuit. In one form, a level shifting circuit includes a first inverter, a level shifting unit, and a fast driving unit. The first inverter is configured to invert an input signal received at an input node and to output an inverted input signal to a second input node. The level shifting unit is configured to perform amplitude up-shifting processing on a received input signal. The fast driving unit is configured to pull up an output signal of an output node of the level shifting unit by increasing a discharge current of the level shifting unit when receiving the input signal.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Guo Zhen Ye
  • Patent number: 11287452
    Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chow Peng, Chung-Peng Hsieh
  • Patent number: 11283444
    Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Chuanzhao Yu, Stephan Leuschner, David Newman
  • Patent number: 11277133
    Abstract: Various implementations described herein are related to a device having level shifter circuitry configured to receive isolation control signals in a first voltage domain and provide an output signal in a second voltage domain that is different than the first voltage domain. The device may include isolation logic circuitry configured to receive a data input signal in the first voltage domain and then provide the isolation control signals to the level shifter circuitry in the first voltage domain based on the data input signal. The isolation logic circuitry may include control passgates that enable the data input signal to propagate to the level shifter circuitry via the isolation control signals.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: March 15, 2022
    Assignee: Arm Limited
    Inventors: Lalit Gupta, El Mehdi Boujamaa, Tirdad Anthony Takeshian
  • Patent number: 11271664
    Abstract: Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 8, 2022
    Assignee: XILINX, INC.
    Inventors: Frantz Stephane Florent Ngankem Ngankem, Kevin Geary
  • Patent number: 11240456
    Abstract: An amplifier circuit for use in an image sensor includes a common source amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An auto-zero switch is coupled between an input of the common source amplifier and an output of the common source amplifier. A feedback capacitor is coupled to the input of the common source amplifier. An offset switch is coupled to the feedback capacitor and is further coupled to a reset voltage and an output of the amplifier circuit. The auto-zero switch and the offset switch are configured to couple the feedback capacitor to the reset voltage during a reset of the amplifier circuit. The offset switch is configured to couple the feedback capacitor to the output of the amplifier circuit after the reset of the amplifier circuit.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 1, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Hiroaki Ebihara, Zheng Yang
  • Patent number: 11239842
    Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: February 1, 2022
    Assignee: Arm Limited
    Inventors: Seshagiri Rao Bogi, Gayathri Gandhi, Vinay Chenani, Fabrice Blanc
  • Patent number: 11223338
    Abstract: In one embodiment, an amplifier circuit may be configured with an output transistor that forms an output current and an output voltage at an output. The amplifier circuit may also include a reference circuit that may be configured to form a reference current that is substantially proportional to the output current. An embodiment of the reference circuit may also be configured to control a transistor to sink current from the output in response changes in the reference current.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: January 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Martin Podzemny
  • Patent number: 11213747
    Abstract: A system of stacking interlocking blocks can be configured into a series of states in order to capture and display both physical and virtual events or content. In some examples, the system includes the stacking interlocking blocks, a grid base having the stacking interlocking blocks stacked on top of the grid base in a physical configuration, and a user system. Each stacking interlocking block includes a block circuit. The grid base includes an embedded computing system configured, by virtue of communicating with each of the block circuits, to determine a position of each stacking interlocking block with respect to the grid base and in some cases both the grid base and the other blocks which have been detected by the grid base.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 4, 2022
    Assignee: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA
    Inventors: Rahul Mangharam, Matthew Edward O'Kelly, Vincent Scott Pacelli, Matthew Anthony Brady
  • Patent number: 11206023
    Abstract: Various implementations described herein are related to a device having a level shifting circuit that shifts an input voltage in a first domain to an output voltage in a second domain, and also, the level shifting circuit may shift the input voltage to the output voltage based on a first level shifting response. The device may also include a boost circuit that increases the input voltage and provides a boosted input voltage to the level shifting circuit so that the level shifting circuit shifts the input voltage to the output voltage based on the boosted input voltage.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: December 21, 2021
    Assignee: Arm Limited
    Inventors: Seshagiri Rao Bogi, Gayathri Gandhi
  • Patent number: 11201536
    Abstract: A semiconductor device having a first switching device and a second switching device respectively on a power supply side and a ground side of the semiconductor device, for driving a load of the semiconductor device, and a switching control circuit that controls switching of the first and second switching devices. The switching control circuit includes a signal output circuit that outputs a set signal and a reset signal for turning on and off the first switching device, respectively, in response to an input signal of the semiconductor device, a level shift circuit that shifts a level of each of the set and reset signals, a drive circuit that drives the first switching device in response to an output from the level shift circuit, and a power supply circuit including a plurality of transistors that are Darlington-coupled, and are configured to generate a power supply voltage of the signal output circuit.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 14, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 11196335
    Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 7, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Chao Chen, Jun Yang, Xinning Liu
  • Patent number: 11196420
    Abstract: A level shifter includes main and auxiliary level shifters, a switch circuit and a hold circuit. The main level shifter includes NMOS and PMOS transistors in a Differential to Single Ended (D2S) structure. The auxiliary level shifter is connected to an output of the main level shifter and includes NMOS and PMOS transistors. Each of the main and auxiliary level shifters includes internal nodes. The switch circuit settles first nodes of the internal nodes to values to support high speed data transmission, and the hold circuit holds second nodes of the internal nodes to a certain value during low frequency operation. The level shifter receives a serial stream of binary values of core supply voltage, converts the serial stream of binary values from the core supply voltage to an input/output (I/O) voltage, and outputs the serial stream of binary values of the input/output (I/O) voltage.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tamal Das, Ankur Ghosh
  • Patent number: 11171649
    Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 9, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Aliasgar Presswala, Wilson Jianbo Chen, Chiew-Guan Tan, Reza Jalilizeinali
  • Patent number: 11152917
    Abstract: Multi-level buffers for biasing of radio frequency (RF) switches are provided. An RF switching circuit that includes a field-effect transistor (FET) switch, an impedance, and a multi-level buffer that provides a switch control voltage to a gate of the FET through the impedance is disclosed. The multi-level buffer receives a control signal to turn on or off the FET switch. Additionally, the multi-level buffer is implemented with stacked inverters that operate using different clock signal phases to pulse the switch control voltage in response to a transition of the control signal to thereby shorten a delay in switching the FET switch.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: October 19, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Mehmet A. Akkaya, Atilim Ergul
  • Patent number: 11152924
    Abstract: A level shifter including an input block that receives an input voltage swinging between a first ground voltage and a first power supply voltage and that connects one node of a first node and a second node to a first ground node, in response to the input voltage, a shifting block that mutually exchanges the voltage levels of third and fourth nodes in response to a current flowing through the one node, a pulse generator that generates a first pulse and a second pulse in response to the input voltage, a first transistor that directly connects the third node to the first ground node in response to the first pulse, and a second transistor that directly connects the fourth node to the first ground node in response to the second pulse.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Chan Lee, Hyoungseok Oh, Jungwook Heo
  • Patent number: 11121711
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 11121713
    Abstract: An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: ANALOG DEVICES, INC.
    Inventors: Scott G. Bardsley, Huseyin Dinc
  • Patent number: 11107806
    Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 31, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, Mariano Dissegna
  • Patent number: 11094280
    Abstract: The present disclosure relates to a level shifter and a display device using the same, and the level shifter includes a first transistor configured to increase a voltage of an output signal, a second transistor configured to lower a voltage of the output signal, a first driver configured to vary a gate voltage of the first transistor in response to a first Vgs signal being varied within a transition time of the output signal, and a second driver configured to vary a gate voltage of the second transistor in response to a second Vgs signal being varied within a transition time of the output signal.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 17, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Hoon Jang, Juno Hur, Dong Ju Kim, Soon Dong Cho
  • Patent number: 11082045
    Abstract: A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 3, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jun Yang, Jian Liu
  • Patent number: 11075618
    Abstract: A plus width modulation (PWM) signal generator is disclosed. The PWM signal generator includes a first signal generator providing a first signal, an output terminal, a first voltage generating circuit including connected to the first voltage generating circuit for providing a first present voltage according to the first signal, and a second voltage generating circuit connected to the first signal generator for providing a second present voltage according to the first signal. The first present voltage is earlier supplied to the output terminal than the second preset voltage, and after the first preset voltage continuously is provided for a period of preset time, the first voltage generating circuit stops providing the first preset voltage.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 27, 2021
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Chih-Lien Chang, Chia-Chien Li
  • Patent number: 11063510
    Abstract: The feedback loop of a switching power converter controller is provided with an averaging circuit that averages either an output voltage, an error signal, or a control voltage. Regardless of which feedback signal is averaged, the averaging occurs over a first cycle of a rectified input voltage to form an averaged signal that is used by the feedback loop in a subsequent cycle of the rectified input voltage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 13, 2021
    Assignee: DIALOG SEMICONDUCTOR INC.
    Inventors: Laiqing Ping, Xiaoyan Wang, Nan Shi
  • Patent number: 11063578
    Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh