The present application claims priority of U.S. Provisional Patent Application No. 60/957,791 filed Aug. 24, 2007, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a through-hole interconnection structure. More particularly, the present invention relates to a through-hole interconnection structure for a semiconductor wafer suitably used in a semiconductor device which includes plural wafers stacked together.
2. Background Art
A three-dimensional semiconductor integrated circuit device has been known which includes two or more wafers stacked together and electrically connected via penetrating wiring. For example, a semiconductor device manufactured in the following method is disclosed in Japanese Unexamined Patent Application, First Publication No. H11-261000.
First, a trench (i.e., a deep groove) is formed on one of the wafers to be stacked together, the inside of the trench is thermally-oxidized, and then Poly-Si is buried as a conductor to form a penetrating wiring. Then, the thickness of the wafer is reduced so as to expose the penetrating wiring. Backside micro bumps are formed on a back surface of the wafer at a position in which the penetrating wiring is formed. The wafers are stacked with the backside micro bumps on one wafer and surface bumps provided on a surface of the other wafer are joined. Then, an insulating adhesive is injected between the wafers to provide a three-dimensional semiconductor integrated circuit device.
An exemplary semiconductor device is disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-59769, in which a desired semiconductor circuit is provided by plural wafers bonded together and semiconductor circuit portions provided on each of the wafers electrically connected to each other. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-59769, the upper and lower substrates are electrically connected via a through-hole interconnecting section protruding from the back surface of the upper substrate and a bump protruding from the principal surface of the lower substrate.
However, in a conventional semiconductor device with plural wafers bonded together, an electric resistance value may be large at the electric connection between the wafers, or variation in the electric resistance may be large. Thus, a reliable electric connection may not be provided between the wafers. In a conventional semiconductor device with plural wafers bonded together, connecting strength at a connecting section for electrically connecting the wafers may be insufficient. Thus, a stable electric connection may not be provided between the wafers.
It is therefore required to provide a reliable and stable electric connection between the wafers in a conventional semiconductor device with plural wafers bonded together Especially when a transverse cross sectional area of the connecting section which electrically connects the wafers is reduced to provide a compact semiconductor device, there arises a problem that reliability and stability in the electric connection of the wafers easily become insufficient.
The present invention has been made in view of the aforementioned problems. An object of the invention is to provide a through-hole interconnection structure for a semiconductor wafer with which a semiconductor device with a highly reliable and stable electric connection of the wafers can be obtained even if a transverse cross sectional area of a connecting section which electrically connects the wafers is reduced.
SUMMARY OF THE INVENTION In order to achieve the object, the present inventors intensively studied on a contact state of a connecting section which electrically connects the wafers. As a result, they have successfully found a through-hole interconnection structure for a semiconductor wafer according to the invention in which the contact area in a connecting section which electrically connects the wafers can be increased.
In order to solve the above problems, the present invention adopted the followings.
Namely, a through-hole interconnection structure for a semiconductor wafer according to the present invention is a through-hole interconnection structure for a semiconductor wafer in which plural wafers are bonded together each having a substrate with devices provided thereon, an electrical signal connecting section is provided on a bonding surface of each wafer, the bonding surface being for bonding with other wafers, and the electrical signal connecting section is electrically connected to an electrical signal connecting section provided on another of the oppositely-facing wafers to form a desired semiconductor circuit, the through-hole interconnection structure for a semiconductor wafer including: a through-hole interconnection section which has a through-hole protruding section which protrudes from the bonding surface to conduct the opposite surfaces of the wafer, the through-hole interconnection section being one of the oppositely-facing electrical signal connecting sections; and a bump which is the other of the oppositely-facing electrical signal connecting sections, wherein: the through-hole protruding section has an oppositely-placed pair of wiring side walls which extend from the bonding surface toward the another wafer, an end of the through-hole interconnection section is extended to reach an inside of the bump; and the bump is placed between the pair of wiring side walls.
According to the through-hole interconnection structure of the semiconductor wafer of the invention, one of the oppositely-placed electrical signal connecting sections is the through-hole interconnection section which has the through-hole protruding section protruding from the bonding surface to conduct the both surfaces of the wafer, and the other of the oppositely-placed electrical signal connecting sections is the bump. The end of the through-hole interconnection section is extended to reach the inside of the bump. With this configuration, the end of the through-hole interconnection section is surrounded by the conductive member which is a part of the bump. Accordingly, even if the transverse cross sectional area of the through-hole interconnection section is significantly reduced, a contact area between the through-hole interconnection section and the bump can be increased in the depth direction of the bump. The through-hole interconnection section and the bump are thus reliably surface-contacted.
Accordingly, in the through-hole interconnection structure of the semiconductor wafer according to the invention, the wafers are electrically connected to each other by the surface contact of the through-hole interconnection section and the bump. In addition, an electric resistance value in the inter-wafer electric connection is sufficiently low, and variation in electric resistance value is small. Connection strength in the connecting section formed by the through-hole interconnection section and the bump is sufficiently high. For this reason, the through-hole interconnection structure has a highly reliable and stable inter-wafer electric connection, and thus can be manufactured with high yield.
In the invention, a sufficient contact area of the through-hole interconnection section and the bump is obtained. Accordingly, in a semiconductor device with plural connecting sections of the through-hole interconnection section and the bump, the number of the connecting sections can be decreased. As a result, a compact semiconductor device can be obtained.
In addition, a through-hole interconnection structure for a semiconductor wafer in which plural wafers are bonded together each having a substrate with devices provided thereon, an electrical signal connecting section is provided on a bonding surface of each wafer, the bonding surface being for bonding with other wafers, and the electrical signal connecting section is electrically connected to an electrical signal connecting section provided on another of the oppositely-facing wafers to form a desired semiconductor circuit, the through-hole interconnection structure for a semiconductor wafer including: a through-hole interconnection section which has a through-hole protruding section which protrudes from the bonding surface to conduct the opposite surfaces of the wafer, the through-hole interconnection section being one of the oppositely-facing electrical signal connecting sections; a bump which is the other of the oppositely-facing electrical signal connecting sections; and a separating section provided on the bonding surface and protruding from the bonding surface, the separating section surrounding the through-hole interconnection section, wherein: the through-hole interconnection section and the separating section are integrally formed; an end of the through-hole interconnection section is provided to protrude from an end of the separating section; and an end of the through-hole interconnection section is extended to reach an inside of the bump and the separating section is extended to reach the inside of the bump.
Further, a through-hole interconnection structure for a semiconductor wafer according to the invention is a through-hole interconnection structure for a semiconductor wafer in which plural wafers are bonded together each having a substrate with devices provided thereon, an electrical signal connecting section is provided on a bonding surface of each wafer, the bonding surface being for bonding with other wafers, and the electrical signal connecting section is electrically connected to an electrical signal connecting section provided on another of the oppositely-facing wafers to form a desired semiconductor circuit, the through-hole interconnection structure including: a through-hole interconnection section which has a through-hole protruding section which protrudes from the bonding surface to conduct the opposite surfaces of the wafer, the through-hole interconnection section being one of the oppositely-facing electrical signal connecting sections; a bump which is the other of the oppositely-facing electrical signal connecting sections; and a separating section which has an oppositely-placed pair of separating side walls extending from the bonding surface toward the another wafer, the separating section being provided on the bonding surface and protruding from the bonding surface to surround the through-hole interconnection section; an end of the through-hole interconnection section is extended to reach an inside of the bump; the through-hole interconnection section and the separating section are separately disposed; and the bump is placed between the pair of separating side walls.
The through-hole protruding section may have an oppositely-placed pair of wiring side walls which extend from the bonding surface toward the another wafer; and the bump may be placed between the pair of wiring side walls.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the invention, showing a configuration of an electrical signal connecting section which is a part of a semiconductor device.
FIG. 2A shows a configuration of the electrical signal connecting section which is a part of the semiconductor device.
FIG. 2B shows a configuration of the electrical signal connecting section which is a part of the semiconductor device.
FIG. 2C shows a configuration of the electrical signal connecting section which is a part of the semiconductor device.
FIG. 2D shows a configuration of the electrical signal connecting section which is a part of the semiconductor device.
FIG. 3 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 4 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 5 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 6 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 7 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 8 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 9 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 10 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 11 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 12 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 13 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 14 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 15 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 16 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 17 shows a manufacturing process of a semiconductor device shown in FIG. 18.
FIG. 18 is a cross-sectional view of main part showing another example of the semiconductor device according to the invention.
FIG. 19 is a flow chart showing a manufacturing process of the semiconductor device shown in FIG. 18.
FIG. 20 is a cross-sectional view of main part showing another example of the semiconductor device.
FIG. 21 shows a configuration of an electrical signal connecting section which is a part of the semiconductor device of FIG. 20.
FIG. 22A shows another example of the semiconductor device.
FIG. 22B is a longitudinal cross-sectional view showing another example of the semiconductor device.
FIG. 23A is a longitudinal cross-sectional view showing another example of the semiconductor device.
FIG. 23B is s transverse cross-sectional view showing another example of the semiconductor device in the longitudinal cross-sectional view of FIG. 23A.
FIG. 23C is a transverse cross-sectional view showing another example of the semiconductor device.
FIG. 24 shows another example of the semiconductor device according to the invention.
FIG. 25A is a transverse cross-sectional view showing another example of the semiconductor device according to the invention.
FIG. 25B shows another example of the semiconductor device of the invention corresponding to FIG. 2B.
FIG. 25C shows another example of the semiconductor device of the invention corresponding to FIG. 2C.
FIG. 25D shows another example of the semiconductor device of the invention corresponding to FIG. 2D.
FIG. 25E shows another example of the semiconductor device according to the invention.
FIG. 26 is a plan view showing a test piece used in an experiment.
FIG. 27 is a graph showing electric resistance values in an electric connection between an upper wafer and middle wafer which together constitute a wafer shown in FIG. 26, and variation in the electric resistance values.
PREFERRED EMBODIMENTS Referring now to the drawings, the invention will be described in detail.
First Embodiment FIGS. 1 to 19 illustrate a through-hole interconnection structure for a semiconductor wafer according to the invention. FIGS. 1 to 2D illustrate configurations of an electrical signal connecting section which is a part of the through-hole interconnection structure according to the invention. FIG. 18 is a cross-sectional view of main part of an exemplary semiconductor device which includes the through-hole interconnection structure for a semiconductor wafer according to the invention. FIGS. 3 to 17 describe a manufacturing process of a semiconductor device shown in FIG. 18. FIG. 19 is a flowchart of the manufacturing process of the semiconductor device shown in FIG. 18.
The semiconductor device shown in FIG. 18 according to the present embodiment includes an upper wafer 1WA and a lower wafer 1WB which are bonded together. An electrical signal connecting section which includes a through-hole interconnecting section 92 is provided on a bonding surface 30a of the upper wafer 1WA which faces the lower wafer 1WB. The through-hole interconnecting section 92 is formed to penetrate a substrate 1SA which is a part of the upper wafer 1WA. The through-hole interconnecting section 92 makes a principal surface (one surface, the upper one in FIG. 18) and an opposite back surface (the other surface, the lower one in FIG. 18) of the wafer 1WA in the thickness direction interconnect to each other. An electrical signal connecting section which includes a bump 26 is provided on a bonding surface 30b of the lower wafer 1WB which faces the upper wafer 1WA. In the semiconductor device shown in FIG. 18, oppositely disposed end 92c of the through-hole interconnecting section 92 of the upper wafer 1WA and the bump 26 of the lower wafer 1WB are electrically connected to each other to form a desired semiconductor circuit. The semiconductor circuit includes a MOS-FET 6 provided on the substrates 1SA and 1SB which are parts of the wafers 1WA and 1WB.
As shown in FIG. 18, an insulating adhesive 30 is placed between the bonding surfaces 30a and 30b of the upper and lower wafers 1WA and 1WB. The adhesive 30 ensures mechanical strength between the upper and lower wafers 1WA and 1WB. In the present embodiment, the adhesive 30 enters the range of the through-hole separating section 51. Since the adhesive 30 has an insulating property, the adhesive 30 never disturbs the performance of the semiconductor circuit.
Reference numeral 51 in the semiconductor device shown in FIG. 18 denotes a through-hole separating section (separating section) which penetrates the substrate 1AS and includes an insulating layer. As shown in FIG. 18, the through-hole separating section 51 is provided to protrude from the bonding surface 30a. The through-hole separating section 51 surrounds each through-hole interconnecting section 92 which is the electrical signal connecting section. The through-hole separating section 51 and the through-hole interconnection section 92 are integrally formed.
The through-hole interconnecting section 92 is electrically connected to a bonding pad BP or the MOS-FET 6 via wires 15a, 15b and 15c. The bump 26 is provided to protrude from the bonding surface 30b of the lower wafer 1WB.
The bump 26 includes a conductive material, and as shown in FIG. 18, is electrically connected to an uppermost wiring layer 15c of the lower wafer 1WB.
The bump 26 preferably has hardness lower than that of the through-hole interconnection section 92. When the bump 26 has hardness lower than that of the through-hole interconnection section 92, the wafers 1WA and 1WB can be bonded together with low pressing force. Thus, breakage of the through-hole interconnection section 92 due to the pressing force for bonding the wafers 1WA and 1WB can be prevented. The end 92c of the through-hole interconnection section 92 can be extended to reliably reach the inside of the bump 26.
To reduce the hardness of the bump 26 with respect to that of the through-hole interconnection section 92, the bump 26 may preferably be made from a conductive material including indium (In), gold added to an indium surface (In/Au) or tin (Sn). The through-hole interconnection section 92 is preferably made from a conductive material including copper and tungsten.
Next, configurations of the through-hole separating section 51 and the through-hole interconnection section 92 shown in FIG. 18 will be described with reference to FIGS. 1 and 2. FIG. 1 is an enlarged vertical longitudinal sectional view showing only a neighborhood of a bonding surface 30a of the upper wafer 1WA which is a part of the semiconductor device shown in FIG. 18. FIG. 2A is an enlarged transverse cross-sectional view showing only the through-hole interconnection section 92 and the bump 26 of the semiconductor device. The longitudinal cross-sectional view shown in FIG. 1 corresponds to line C-C in FIG. 2A. The transverse cross-sectional view (plan view) shown in FIG. 2A corresponds to line A-A in FIG. 1.
As shown in FIGS. 1 and 2A, the through-hole interconnection section 92 shown in FIG. 18 includes two wiring sections 92d and 92d which have U-shaped transverse cross sections. As shown in the transverse cross-sectional view of FIG. 2A, the two U-shaped wiring sections 92a and 92a are disposed symmetrically in both vertical and horizontal directions with open end thereof facing each other. As shown in FIG. 1, each of the wiring sections 92d and 92d includes a through-hole protruding section 92a protruding from the bonding surface 30a. The through-hole protruding section 92a includes an oppositely-facing pair of wiring side walls 92b and 92b which extend from the bonding surface 30a toward the lower wafer 1WB. As shown in FIG. 1, an end 92c of the through-hole interconnection section 92 extends to reach an inside of the bump 26. The bump 26 is placed between the pair of the wiring side walls 92b and 92b of the through-hole interconnection section 92. In this manner, a bottom surface and side surfaces of the end 92c of the through-hole interconnection section 92 are in contact with the bump 26.
As shown in FIG. 1, a through-hole separating section 51 shown in FIG. 18 is in contact with a peripheral surface of each wiring section 92d. The through-hole separating section 51 surrounds and covers each wiring section 92d. The through-hole separating section 51 is provided to protrude from the bonding surface 30a. The protrusion length of the through-hole separating section 51 from the bonding surface 30a is shorter than that of the through-hole protruding section 92a of the through-hole interconnection section 92. The end 92c of each wiring section 92d of the through-hole interconnection section 92 is provided to protrude from an end of the through-hole separating section 51.
In the example shown in FIG. 2A, the through-hole interconnection section 92 is described to include two wiring sections 92d and 92d which have U-shaped transverse cross sections. However, the configuration of the transverse cross section of the through-hole interconnection section is not limited to that described in FIG. 2A. Alternatively, configurations shown in FIGS. 2B to 2D may be employed.
FIGS. 2B to 2D illustrate other exemplary configurations of the through-hole interconnection section. FIGS. 2B to 2D are enlarged transverse cross-sectional views showing only the through-hole interconnection section and the bump 26 of the semiconductor device shown in FIG. 18. The transverse cross-sectional view (plan view) shown in FIGS. 2B to 2D correspond to line A-A in FIG. 1. The longitudinal cross-sectional view shown in FIG. 1 corresponds to line C-C in FIGS. 2B to 2D.
The through-hole interconnection section 93 shown in FIG. 2B is described to include two wiring sections 93d and 93d which have L-shaped transverse cross sections. As shown in the transverse cross-sectional view of FIG. 2B, the two L-shaped wiring sections 93d and 93d are symmetrically placed with a substantially square-shaped space formed therebetween with respect to a diagonal line of the substantially square-shaped space.
A through-hole interconnection section 94 shown in FIG. 2C has a square ring transverse cross section. Instead of the transverse cross section shown in FIG. 2C, the through-hole interconnection section 94 may have a rectangular or parallelogram ring cross section.
A rough-hole interconnection section 95 shown in FIG. 2D has a circular ring transverse cross section. In the example shown in FIG. 2D, the through-hole interconnection section 95 has a circular ring transverse cross section. The through-hole interconnection section 95 may alternatively have one or more circular arc transverse cross sections.
In the semiconductor device shown in FIG. 18, the upper wafer 1WA includes a thin plate shaped as a substantial circle when seen in a plan view. The substrate 1SA which is a part of the upper wafer 1WA is made of n-type or p-type single crystal of silicon (Si) or other material. As shown in FIG. 18, a groove-shaped separating section 2 for separating devices is formed on the principal surface of the substrate 1SA (i.e., on the principal surface of the wafer 1WA). The groove-shaped separating section 2 includes a buried insulating layer 2b of silicon oxide (SiO2) or other material. An active region is defined on the principal surface of the substrate 1SA by the separating section 2.
In active region surrounded by groove type separating section 2, device which constitutes semiconductor circuit like MOS-FET (Metal Oxide Semiconductor Field Effect Transistor) 6, for example is formed. The MOS-FET 6 includes a semiconductor region 6a for source and drain, a gate insulation film 6b and a gate electrode 6c. The semiconductor region 6a for source and drain is provided by doping the substrate 1SA with desired impurity (e.g., phosphorus (P) or arsenic (As) for n-type channel MOS-FET 6, and boron (B) for p-type channel MOS-FET 6). The gate insulation film 6b includes silicon oxide or other material and is provided on the principal surface of the substrate 1SA. The gate electrode 6c includes low-resistance polysilicon or other material and is provided on the gate insulation film 6b. The insulating layer 7 in the active region on the principal surface of the substrate 1SA includes an insulating layer of silicon oxide or other material.
Other active devices such as a bipolar transistor and a diode may be provided instead of the MOS-FET 6 shown in FIG. 18. Passive devices such as resistance (e.g., diffusion resistance and polysilicon resistance), a capacitor and an inductor may be provided instead of the MOS-FET 6.
In FIG. 18, reference numerals 8a, 8b, 8c and 8d each denote an interlayer insulation film, numeral 10 denotes a surface protecting film, numerals 15a, 15b, and 15c denote wiring and numerals 16a, 16b, 16c and 16d each denote a plug. The interlayer insulation films 8a, 8b, 8c, and 8d are made of silicon oxide or other material. The wiring 15a to 15c and the plugs 16a to 16d are made of metal such as tungsten (W), aluminum (Al), copper (Cu). The wiring 15a of a first layer is electrically connected to the semiconductor region 6a for source and drain and the gate electrode 6c of the MOS-FET 6 via the plug 16a. The wiring 15a of the first layer is also electrically connected to the through-hole interconnecting section 9 via the plug 16b. The surface protecting film 10 includes, for example, a single silicon oxide film or a lamination of a silicon oxide film and a silicon nitride film deposited on the silicon oxide film. An opening 17 is formed in a part of the surface protecting film 10 through which a part of the third wiring 15c is exposed. The part of the wiring 15c exposed through the opening 17 when seen in a plan view is formed as a bonding pad BP. Although not shown in FIG. 18, a bump may be provided in connection with the bonding pad BP on the principal surface of the wafer 1WA.
In the semiconductor device shown in FIG. 18, the structure of the lower wafer 1WB is almost the same as that of the upper wafer 1WA except for the following points. The through-hole separating section 51 and the through-hole interconnecting section 92 are not formed on the lower wafer 1WB. Unlike the upper wafer 1WA, a conductive pattern 25 underlying the bump electrically connected to the bonding pad BP through the opening 17 is formed on the opening 17 provided on the principal surface of the lower wafer 1WB. A bump 26 is formed on the conductive pattern 25 underlying the bump.
Referring now to FIGS. 3 to 17 and 19, a manufacturing process of the semiconductor device shown in FIG. 18 will be described.
First, a manufacturing process of the upper wafer (i.e., a manufacturing process 300 of the upper wafer of the first layer in FIG. 19) will be described. The upper wafer 1WA is first prepared (process 100A in FIG. 19), and as shown in FIG. 3, the groove-shaped separating section 2 for device separation is formed on the principal surface (i.e., the principal surface of the wafer 1WA) of the substrate 1SA (process 101A in FIG. 19).
Next, in the present embodiment, as shown in FIG. 3, a device like the MOS-FET 6 which includes a semiconductor region 6a for source and drain, a gate insulation film 6b and a gate electrode 6c is formed in the active region surrounded by the groove-shaped separating section 2 of the substrate 1SA (process 103A in FIG. 19). Next, the insulating layer 7 of silicon oxide or other material is provided on the principal surface of the active region of the substrate 1SA.
Then, an insulating layer of silicon oxide or other material is deposited on the principal surface of the substrate 1SA by a chemical vapor deposition (CVD) or other process, and the upper surface of the insulating layer is smoothed to provide an interlayer insulation film 8a as shown in FIG. 4.
Next, the through-hole separating section 51 is formed on the substrate 1SA. First, as shown in FIG. 4, a resist film is applied on the principal surface of the substrate 1SA by spin coating or other process and then exposed and developed to form a resist pattern RA on the principal surface of the substrate 1SA.
Deep separation grooves 5a are then formed on the substrate 1SA as shown in FIG. 5 by etching, using the resist pattern RA as an etching mask, portions of the interlayer insulation film 8a, the insulating layer 7 and the substrate 1SA exposed from the resist pattern RA. As shown in FIG. 5, the deep separation groove 5a extends from the principal surface of the substrate 1SA along a direction perpendicular to the principal surface. The deep separation groove 5a ends at a position deeper than the separation groove 2a for device separation.
The resist pattern RA is removed and the insulating layer is formed on an inner surface and a bottom surface of the separation groove 5a. For example, an insulating layer of silicon oxide (SiO2) or other material is deposited by a chemical vapor deposition (CVD) or other process to form the through-hole separating section 51 (process 102A in FIG. 19) as shown in FIGS. 6 and 7. The insulating layer which is a part of the through-hole separating section 51 is formed in the inner surface and the bottom surface of the deep separation groove 5a as shown in FIG. 6. Space 9a formed as a U-shaped groove when seen in a plan view exists in a central portion of the deep separation groove 5a to be surrounded by the through-hole separating section 51. FIG. 6 is a cross-sectional view taken along line A-A in FIG. 7. Although FIG. 7 is a plan view, the through-hole separating section 51 is shown with diagonal lines to facilitate visualization.
Next, the through-hole interconnecting section 92 will be formed. First, the space 9a defined by the through-hole separating section 51 in the deep separation groove 5a is filled with a conductive material, which is deposited on the principal surface of the substrate 1SA by CVD or other process. Then, an excess portion of the conductive material formed outside of the deep separation groove 5a is removed by a chemical mechanical polishing (CMP) or other process so that the conductive material exists only within the deep separation groove 5a. In this manner, a conductive section used as the wiring sections 92a and 92a of the through-hole interconnecting section 92 is formed as shown in FIGS. 8 and 9 (process 104A in FIG. 19).
The method of forming the conductive section used as the wiring sections 92a and 92a of the through-hole interconnecting section 92 is not limited to CVD and may include plating or other processes.
FIG. 8 is a cross-sectional view taken along line A-A in FIG. 9. Although FIG. 9 is a plan view, the through-hole separating section 51 and the through-hole interconnecting section 92 are shown with diagonal lines to facilitate visualization. As shown in FIGS. 9 and 2A, the through-hole interconnecting section 92 includes two wire sections 92d and 92d having U-shaped transverse cross sections. The through-hole separating section 51 surrounds and covers outer peripheries of the wiring sections 92d and 92d. The through-hole separating section 51 and the through-hole interconnection section 92 are integrally formed.
Next, as shown in FIG. 10, in an ordinary wiring formation method of a semiconductor device, the interlayer insulation films 8b, 8c and 8d, the surface protecting film 10, the wiring 15a, 15b and 15c, the plugs 16a, 16b, 16c and 16d, the opening 17, and the bonding pad BP are formed on the principal surface of the substrate 1SA to form a multi-layered wiring layer (process 105A in FIG. 19).
Then, as shown in FIG. 11, a glass support substrate 21 is made to adhere to the principal surface of the wafer 1WA via an adhesive sheet 20 and a thickness of the wafer 1WA is reduced (process 107A in FIG. 19). The thickness reducing process of the wafer 1WA of the present embodiment includes the following first thickness reducing processes and the second thickness reducing process.
A dashed line in FIG. 12 shows the substrate 1SA before being subject to the first thickness reducing process. In the first thickness reducing process, as shown in FIG. 12, the back surface of the wafer 1WA (i.e., the back surface of the substrate 1SA) is ground to a desired thickness with the glass support substrate 21 fixed to the principal surface of the wafer 1WA. The first thickness reducing process is a mechanical process including grinding. The first thickness reducing process is completed before reaching the through-hole separating section 51 (i.e., before the through-hole separating section 51 is exposed from the back surface of the wafer 1WA).
In the second thickness reducing process, the back surface of the wafer 1WA is subject to etching (wet etching, dry etching or both) with the glass support substrate 21 fixed to the principal surface of the wafer 1WA. A dashed line in FIG. 13 shows the substrate 1SA before being subject to the second thickness reducing process.
First, the back surface of the wafer 1WA is immersed in a chemical solution for etching the wafer 1WA so as to wet-etch the substrate 1SA. As a result of the etching, the through-hole separating section 51 is exposed from the back surface of the wafer 1WA as shown in FIG. 13.
Next, the back surface of the wafer 1WA is immersed in a chemical solution for etching the through-hole separating section 51 so as to wet-etch a portion of the through-hole separating section 51 exposed from the back surface of the wafer 1WA. As a result of the etching, the end 92c of the through-hole interconnecting section 92 is exposed from the back surface of the wafer 1WA as shown in FIG. 14.
Finally, the back surface of the wafer 1WA is etched by immersing in a chemical solution so as to expose the through-hole separating section 51 and the through-hole interconnecting section 92 from the back surface of the wafer 1WA.
FIG. 15 is a cross-sectional view of main part of the upper wafer 1WA after being subject to the second thickness reducing process. In the upper wafer 1WA after being subject to the second thickness reducing process, lower parts of the through-hole separating section 51 and the through-hole interconnecting section 92 protrude a desired amount from the back surface of the wafer 1WA serving as the bonding surface 30a after being subject to the second thickness reducing process.
As a result of the second thickness reducing process, the wiring section 92d and 92d of the through-hole interconnecting section 92 are separated from the substrate 1SA at the side thereof by the through-hole separating section 51. At the lower part of each of the wiring sections 92d and 92d of the through-hole interconnecting section 92, the through-hole interconnection section 92 is exposed to be completely electrically separated from the substrate 1SA. In this stage, the deep separation groove 5a becomes a hole penetrating through the main surface and the back surface of the substrate 1SA.
In the above-described example, the first thickness reducing process (i.e., grinding) and the second thickness reducing process (i.e., etching) are conducted in this order in the thickness reducing process of the wafer 1WA. However, the first thickness reducing process (i.e., grinding) may be omitted.
The described second thickness reducing process includes three etching processes. However, the substrate 1SA and the through-hole separating section 51 may be etched in one etching process to complete the second thickness reducing process. The substrate 1SA and the through-hole separating section 51 may also be etched in two etching processes. The substrate 1SA may be first etched and then the through-hole separating section 51 is etched to complete the second thickness reducing process.
In this manner, the manufacturing process of the upper wafer 1WA is completed.
Next, the lower wafer is manufactured. As a lower wafer, a lowermost wafer (i.e., a lower wafer manufacturing process above the second layer in FIG. 19) of which back surface is not bonded to another wafer will be described in the manufacturing process. Here, the reference numeral 302 in FIG. 19 denotes the lower wafer of the second layer.
The manufacturing process of the lower wafer, which is the lowermost wafer, is almost the same as that of the upper wafer 1WA (processes 100A to 107A in FIG. 19) except for the following points.
In the manufacturing process of the lowermost wafer, a bump formation process (process 106B) is conducted after a formation process (process 105B) of a multi-layer wiring layer shown in FIG. 19. The manufacturing process of the lowermost wafer includes no reducing process (process 107A) of the wafer, no formation process (process 102B) of the through-hole separating section, and no formation process (process 104B) of the through-hole interconnecting section. A wafer with reduced thickness is used in an assembly process. However, the wafer thickness reducing process of process 107A has a purpose different from that of the assembly process. Thus, no wafer with reduced thickness is included in process 107A.
Next, the thus-manufactured upper and lower wafers 1WA and 1WB are bonded together (an upper and lower wafer bonding process 303 of the first and second layers in FIG. 19). First, after the lower wafer 1WB is fixed, the upper wafer 1WA shown in FIG. 15 is disposed over the principal surface (i.e., the bonding surface 30b) of the lower wafer 1WB so that the back surface (i.e., the bonding surface 30a) of the upper wafer 1WA faces the principal surface of the lower wafer 1WB as shown in FIG. 16.
Then, the upper wafer 1WA and the lower wafer 1WB are aligned with each other. In particular, the bump 26 on the principal surface of the lower wafer 1WB and the through-hole interconnecting section 9 on the back surface of the upper wafer 1WA corresponding to the bump 26 are aligned with each other (process 201 in FIG. 19).
Subsequently, as shown in FIG. 17, the facing surfaces (i.e., the bonding surfaces 30a and 30b) of the upper and lower wafers 1WA and 1WB are moved closer to each other so as to bond and press the lower wafer 1WB and upper wafer 1WA with each other. The ends 92c of the through-hole interconnection sections 92 on the back surface of the upper wafer 1WA are arranged so as to reach to the insides of the bumps 26 on the principal surface of the lower wafer 1WB; thereby, the bumps 26 and the through-hole interconnection sections 92 become in contact with each other and are connected electrically. In this manner, semiconductor circuit sections of the upper and lower wafers 1WA and 1WB are electrically connected to each other to form a desired semiconductor circuit (process 202 in FIG. 19).
In the present embodiment, the distance between the bonding surfaces 30a and 30b is sufficiently longer than the height of the bump 26. Thus, The wafer 1WA and the bump 26 are not in contact with each other. The insulating adhesive 30 is then placed between the oppositely facing bonding surfaces 30a and 30b of the upper and lower wafers 1WA and 1WB to fix the wafers 1WA and 1WB (process 203 in FIG. 19).
Then, the glass support substrate 21 is separated from the principal surface of the upper wafer 1WA to provide the semiconductor device shown in FIG. 18.
After these processes, the semiconductor device shown in FIG. 18 is cut into chips. The thus-obtained chip has a three-dimensional structure that includes plural wafers stacked together. That is, the semiconductor circuits formed on the wafers included in the chips are electrically connected to each other via the through through-hole interconnecting section 92 and the bump 26 so as to collectively form a semiconductor integrated circuit.
In the through-hole interconnection structure of the semiconductor wafer of the semiconductor device according to the present embodiment, the end 92c of the through-hole interconnection section 92 is extended to reach the inside of the bump 26. Accordingly, the bottom surface and the side surfaces of the end 92c of the through-hole interconnection section 92 are made to contact with the bump 26. Thus, the through-hole interconnection section 92 and the bump 26 are reliably surface-contacted. Thus, a highly reliable and stable electric connection can be established between the wafers 1WA and 1WB.
In the through-hole interconnection structure of the semiconductor wafer according to the present embodiment, the through-hole protruding section 92a protruding from the bonding surface 30a of the through-hole interconnection section 92 has an oppositely-facing pair of wiring side walls 92b and 92b which extend from the bonding surface 30a toward the lower wafer 1WB. The bump 26 is placed between the pair of wiring side walls 92b and 92b. In this manner, the contact area of the through-hole interconnection section 92 and the bump 26 is sufficiently large and thus the through-hole interconnection section 92 and the bump 26 are reliably surface-contacted.
The invention, however, is not limited only to the aforementioned examples. For example, although the example shown in FIG. 18 relates to the semiconductor device with two wafers 1WA and 1WB bonded together, the number of the wafers to be bonded is not limited to two, and three or more wafers may be bonded. FIG. 20 is a cross-sectional view of main part of another exemplary semiconductor device which includes a through-hole interconnection structure according to the invention. The semiconductor device shown in FIG. 20 is a three-dimensional multi-layered semiconductor device in which three substrates 1SA, 1SB and 1SC are stacked. In the semiconductor device shown in FIG. 20, the same members as those shown in FIG. 18 are denoted by the same reference numerals and description thereof will be omitted.
Next, an exemplary manufacturing process of the semiconductor device shown in FIG. 20 will be described with reference to FIG. 19. First, an uppermost wafer 1WA and a lowermost wafer 1WB are prepared in the same manner as in the manufacturing process of the semiconductor device shown in FIG. 18.
A middle wafer 1WC is prepared in the processes 100B to 106B shown in FIG. 19. The middle wafer 1WC (i.e., the semiconductor wafer) also includes a through-hole separating section 51 and a through-hole interconnecting section 92 as in the uppermost wafer 1WA. The middle wafer 1WC differs from the uppermost wafer 1WA in that a conductive pattern 25 underlying the bump and a bump 26 are formed on a principal surface of the middle wafer 1WC. The middle wafer 1WC in this stage has not been subject to the first and second thickness reducing processes and thus is still thick.
Then, two wafers 1WA and 1WC are aligned with each other as in the manufacturing method of the semiconductor device shown in FIG. 18. An adhesive 30 is placed between the wafer 1WA and 1WC. The wafers 1WA and 1WC are fixed together (process 304: 201, 202 and 203 for bonding upper and lower wafers above the third layer in FIG. 19).
Subsequently, a thickness of the lower middle wafer 1WC is reduced from the backside thereof in a thickness reducing process as described above with the glass support substrate 21 bonded to the principal surface of upper uppermost wafer 1WA (process 107A in the middle in FIG. 19). In this manner, the through-hole separating section 51 and the through-hole interconnecting section 92 are exposed (i.e., protrude) from the back surface (i.e., the bonding surface 30a) of the lower middle wafer 1WC.
Then, the middle wafer 1WC and the lowermost wafer 1WB are aligned with each other with the glass support substrate 21 bonded to the principal surface of the upper uppermost wafer WA. The adhesive 30 is placed between the wafers 1WC and 1WB to fix the wafers 1WC and 1WB (processes 201 to 203 in the lower middle in FIG. 19). Subsequent processes are the same as described above and description thereof will be omitted. When four or more wafers are to be bonded together, the process conducted for the middle wafer 1WC and the wafer bonding process may be repeated as required.
Also in the semiconductor device shown in FIG. 20, the end 92c of the through-hole interconnection section 92 is extended to reach the inside of the bump 26. Thus, the bottom surface and the side surfaces of the end 92c of the through-hole interconnection section 92 are in contact with the bump 26, and thus the through-hole interconnection section 92 and the bump 26 are reliably surface-contacted. In this manner, a reliable and stable electric connection can be established among the wafers 1WA, 1WB and 1WC.
OTHERS EXAMPLES The through-hole interconnection structure of the semiconductor wafer according to the invention is not limited to those described above. Alternatively, through-hole interconnection structures of semiconductor wafers shown in FIGS. 21 to 25 may be employed.
Other Example 1 FIG. 21 illustrates another example of the through-hole interconnection structure of the semiconductor wafer according to the invention. FIG. 21 is an enlarged vertical longitudinal sectional view showing only a neighborhood of the bonding surface 30a of the upper wafer 1WA of the semiconductor device. The transverse cross-sectional view plan view) of the connecting section of the through-hole interconnection section 96 and the bump 26 in the longitudinal cross-sectional view shown in FIG. 21 is the same as that shown in FIG. 2A. That is, the longitudinal cross-sectional view shown in FIG. 21 corresponds to line C-C in FIG. 2A. The transverse cross-sectional view (plan view) shown in FIG. 2A corresponds to line A-A in FIG. 21.
As shown in FIG. 21, the through-hole interconnection section 96 includes a through-hole interconnection section main part 96d which penetrates the substrate 1SA, a plug wiring 96e provided in contact with an end of the through-hole interconnection section main part 96d at the side of the bonding surface 30a, and a branched conductive section 96f provided in contact with a surface of the plug wiring 96e at the side of the bonding surface 30a.
As shown in FIG. 21, the through-hole interconnection section 96 has two through-hole protruding sections 96a protruded from the bonding surface 30a. Each of the two through-hole protruding sections 96a has an oppositely-facing pair of wiring side walls 96b and 96b which extend from the bonding surface 30a toward the lower wafer 1WB. As shown in FIG. 21, the pair of wiring side walls 96b and 96b is branched from the through-hole interconnection section main part 96d by the plug wiring 96e and the branched conductive section 96f The wiring side walls 96b and 96b are electrically connected to the through-hole interconnection section main part 96d.
In the present embodiment, as in the through-hole interconnection section 92 shown in FIG. 2A, the pair of wiring side walls 96b and 96b have two U-shaped transverse cross sections. The wiring side walls 96b and 96b are disposed symmetrically in both vertical and horizontal directions with open end thereof facing each other.
As shown in FIG. 21, an end 96c of the through-hole interconnection section 96 extends to reach the inside of the bump 26. The bump 26 is placed between the pair of wiring side walls 96b and 96b of the through-hole interconnection section 96.
As shown in FIG. 21, a through-hole interconnection section main part 96d is surrounded by the through-hole separating section 52 which is integrally formed with the through-hole interconnection section main part 96d. The plug wiring 96e is buried in the first layer insulation layer 8e. The branched conductive section 96f is buried in the second layer insulation layer 8f. Ends of the pair of wiring side walls 96b and 96b at the side of the branched conductive section 96f are buried in the third layer insulation layer 8g. The plug wiring 96e is buried in the first layer insulation layer 8e. The plug wiring 96e is insulated from the upper wafer 1WA with the edge of the plug wiring 96e overlapping the through-hole separating section 52 when seen in a plan view.
In the present embodiment, the through-hole interconnection section main part 96d, the plug wiring 96e, and the branched conductive section 96f all have square transverse cross sections. As shown in FIG. 21, the area of the transverse cross section of the branched conductive section 96f is the largest, the area of the transverse cross section of the through-hole interconnection section main part 96d is the smallest, and the area of the transverse cross section of the plug wiring 96e is the middle of them. The area of the transverse cross section of the plug wiring 96e may be smaller than that of the through-hole interconnection section main part 96d, and the edge of the plug wiring 96e may overlap the through-hole interconnection section main part 96d when seen in a plan view.
It suffices that the plug wiring 96e is provided in contact with the branched conductive section 96f. As shown in FIG. 21, the entire or a part of the plug wiring 96e may overlap the branched conductive section 96f when seen in a plan view. It is preferable, however, that the contact area of the plug wiring 96e and the branched conductive section 96f is made sufficiently large so that the electric resistance value in the electric connection between the plug wiring 96e and the branched conductive section 96f becomes sufficiently small, and a sufficient alignment margin of the plug wiring 96e and the branched conductive section 96f can be provided. It is further preferable that the entire surface of the plug wiring 96e overlaps the branched conductive section 96f when seen in a plan view.
The configurations of the transverse cross sections of the through-hole interconnection section main part 96d, the plug wiring 96e and the branched conductive section 96f are not particularly limited. It suffices that a branched conductive section 96f with a sufficiently large area of the transverse cross section is provided so that the through-hole interconnection section main part 96d, the plug wiring 96e and the branched conductive section 96f are electrically connected with one another, and are insulated from the upper wafer 1WA, and the pair of wiring side walls 96b and 96b can be formed with predetermined configurations of the transverse cross sections. In particular, the configurations of the transverse cross sections of the through-hole interconnection section main part 96d, the plug wiring 96e and the branched conductive section 96f are not limited to square, but may be circular or rectangle. The configurations of the transverse cross sections of the through-hole interconnection section main part 96d, the plug wiring 96e, and the branched conductive section 96f may be similar to or different from one another. For example, the configurations of the transverse cross sections of the through-hole interconnection section main part 96d and the plug wiring 96e may be circular, and the configuration of the transverse cross section of the branched conductive section 96f may be rectangle.
It suffices that the configuration of the transverse cross section of the through-hole separating section 52 can surround a peripheral surface of the through-hole interconnection section main part 96d to prevent electric connection of the through-hole interconnection section main part 96d and the plug wiring 96e with the upper wafer 1WA. The configuration of the transverse cross section of the through-hole separating section 52 is not particularly limited and can be suitably determined depending on the configuration of the transverse cross sections of the through-hole interconnection section main part 96d and the plug wiring 96e.
In the example shown in FIG. 21, the pair of wiring side walls 96b and 96b of the through-hole interconnection section 96 have two U-shaped transverse cross sections (see FIG. 2A). The configurations of the transverse cross sections of the pair of wiring side walls 96b and 96b, however, are not limited to these shown in FIG. 2A, and configurations shown in FIGS. 2B to 2D may also be employed.
Other Example 2 FIGS. 22A and 22B illustrate another example of the through-hole interconnection structure of the semiconductor wafer according to the invention. As in the through-hole interconnection structure of the semiconductor wafer shown in FIG. 22A, when the through-hole separating section 5 has a ring configuration, the bump may be disposed within the ring configuration of the through-hole separating section 5. The bump may also be projected from the ring configuration of the through-hole separating section 5 as in the bump 26a shown in FIG. 22A.
FIG. 22A is an enlarged vertical longitudinal sectional view showing only a neighborhood of the bonding surface 30a of the upper wafer 1WA when the bump 26a is projected from the ring configuration of the through-hole separating section 5. FIG. 22B is a transverse cross-sectional view (plan view) of the connecting section of the through-hole interconnection section 9 and the bump 26a in a longitudinal cross-sectional view shown in FIG. 22A. The longitudinal cross-sectional view shown in FIG. 22A corresponds to line C-C in FIG. 22B. The transverse cross-sectional view (plan view) shown in FIG. 22B corresponds to line A-A in FIG. 22A.
The through-hole interconnection section 9 shown in FIGS. 22A and 22B includes two wiring sections 91 and 91 which have rectangular transverse cross sections. The two wiring sections 91 and 91 are disposed in parallel. Each wiring sections 91 and 91 has a through-hole protruding section 91a protruding from the bonding surface 30a. The through-hole protruding section 91a has an oppositely-facing pair of wiring side walls 91b and 91b which extend from the bonding surface 30a toward the lower wafer 1WB.
As shown in FIGS. 22A and 22B, the transverse cross section of through-hole separating section 5 is a square ring configuration. The through-hole separating section 5 and the through-hole interconnection section 9 are separated from each other. The through-hole separating section 5 is formed as a frame surrounding the through-hole interconnection section 9 with certain space left therebetween.
As shown in FIGS. 22A and 22B, the through-hole separating section 5 has an oppositely-facing pair of separating side walls which extend from the bonding surface 30a toward the lower wafer 1WB. Here, the through-hole separating section 5 has a square ring configuration. Accordingly, the pair of separating side wall has a first pair of separating side walls 51a and 51a and a second pair of separating side walls 51b and 51b disposed in a direction perpendicular to the first pair of separating side walls 51a and 51a in their transverse cross sections.
As shown in FIG. 22A, the end 9c of the through-hole interconnection section 9 is extended to reach the inside of the bump 26. The bump 26 is placed between the pair of wiring side walls 91b and 91b of the through-hole interconnection section 9. That is, after the end 9c of the through-hole interconnection section 9 is made to abut the bump 26, the end 9c is pressed into the bump 26. Thus, the bump 26 is deformed so that the end 9c of the through-hole interconnection section 9 and the bump 26 are in close contact and are surface contacted. A side surface of the through-hole interconnection section 9 and the bump 26 are made to contact to provide a large contact area.
The bump 26 is placed between the first pair of separating side walls 51a and 51a and the second pair of separating side walls 51b and 51b of the through-hole separating section 5.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 22A and 22B, the through-hole separating section 5 is extended to reach the inside of the bump 26a, and the bump 26a is projected from the ring configuration of the through-hole separating section 5. However, the distance between the bonding surfaces 30a and 30b is sufficiently longer than the height of the bump 26a. Thus, the bump 26a projecting from the ring configuration of the through-hole separating section 5 and the wafer 1WA are not in contact with each other.
The through-hole interconnection structure of the semiconductor wafer shown in FIG. 22 can be manufactured in the following process. In a process in which the end 9c of the through-hole interconnection section 9 on the back surface of the upper wafer 1WA is extended to reach the inside of the bump 26a on the principal surface of the lower wafer 1WB, the bump 26a and the through-hole interconnection section 9 are made to contact with each other and is electrically connected, the through-hole separating section 5 is extended to reach the inside of the bump 26a to make the bump 26a project from the ring configuration of the through-hole separating section 5.
In this through-hole interconnection structure of the semiconductor wafer, the end 9c of the through-hole interconnection section 9 is extended to reach the inside of the bump 26a. Thus, the bottom surface and the side surfaces of the end 9c of the through-hole interconnection section 9 are made to contact with the bump 26a. Thus, a reliable and stable electric connection can be established between the wafers 1WA and 1WB.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 22A and 22B, the bump 26a is placed between the pair of wiring side walls 91b and 91b. With this configuration, the contact area of the through-hole interconnection section 9 and the bump 26a becomes large to provide reliable surface contact between the through-hole interconnection section 9 and the bump 26a.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 22A and 22B, the bump 26a is placed between the first pair of separating side walls 51a and 51a and the second pair of separating side wall pairs 51b and 51b (i.e., inside of the square ring configuration of the through-hole separating section 5), and the through-hole separating section 5 is extended to reach the inside of the bump 26a. The connecting section which includes the through-hole interconnection section 9 and the bump 26a are thus reinforced by the through-hole separating section 5. Accordingly, a more reliable and stable electric connection can be established between the wafers.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 22A and 22B, the through-hole separating section 5 is extended to reach the inside of the bump 26a. In this configuration, when the end 9c of the through-hole interconnection section 9 is extended to reach the inside of the bump 26a, the bump 26a between the through-hole separating section 5 and the through-hole interconnection section 9 is deformed toward the through-hole interconnection section 9. In this manner, the substantial contact area of the through-hole interconnection section 9 and the bump 26a is increased to provide a sufficient contact area of the through-hole interconnection section 9 and the bump 26a in the thickness direction of the bump 26a. Accordingly, the through-hole interconnection section 9 and the bump 26a are more reliably surface-contacted.
Other Example 3 FIGS. 23A to 23C illustrate another example of the through-hole interconnection structure of the semiconductor wafer according to the invention. FIG. 23A is an enlarged vertical longitudinal sectional view showing only a neighborhood of the bonding surface 30a of the upper wafer 1WA when the bump 26a is projected from the ring configuration of the through-hole separating section 5. FIG. 23B is a transverse cross-sectional view (plan view) of the connecting section of the through-hole interconnection section 97 and the bump 26a in the longitudinal cross-sectional view shown in FIG. 23A. The longitudinal cross-sectional view shown in FIG. 23A corresponds to line C-C in FIG. 23B. The transverse cross-sectional view (plan view) shown in FIG. 23B corresponds to line A-A in FIG. 23A.
Although the through-hole interconnection section 97 shown in FIGS. 23A and 23B has a square pole configuration, it may alternatively have a cylindrical or a polygonal column shape. Here, the transverse cross-sectional view (plan view) shown in FIG. 23C corresponds to line A-A in FIG. 23A, and the longitudinal cross-sectional view shown in FIG. 23A corresponds to line C-C in FIG. 23C. In the example shown in FIG. 23C, a configuration of the through-hole separating section 5 is made as a ring concentric with the through-hole interconnection section 98.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 23A to 23C, the through-hole separating section 5 is extended to reach the inside of the bump 26a, and the bump 26a is projecting from the ring configuration of the through-hole separating section 5. However, the distance between the bonding surfaces 30a and 30b is sufficiently long with respect to the height of the bump 26a. Thus, the bump 26a projecting from the ring configuration of the through-hole separating section 5 and the wafer 1WA are not in contact.
The through-hole interconnection structures of the semiconductor wafer of semiconductor device shown in FIGS. 23A to 23C can be manufactured in the following process. In a process in which the end 97c of the through-hole interconnection section 97 on the back surface of the upper wafer 1WA is extended to reach the inside of the bump on the principal surface of the lower wafer 1WB, the bump 26a and the through-hole interconnection section 97 are made to contact with each other and is electrically connected, the through-hole separating section 5 is extended to reach the inside of the bump 26a to make the bump 26a project from the ring configuration of the through-hole separating section 5.
In such a through-hole interconnection structure of the semiconductor wafer, the end 97c of the through-hole interconnection section 97(98) is extended to reach the inside of the bump 26a. With this configuration, the bottom surface and the side surfaces of the end 97c of the through-hole interconnection section 97(98) are made in contact with the bump 26a. A more reliable and stable electric connection can be established between the wafers 1WA and 1WB.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 23A to 23C, the bump 26a is placed between the pair of the separating side walls (i.e., inside of the square ring configuration shown in FIG. 23B or the circular ring configuration shown in FIG. 23C of the through-hole separating section 5), and the through-hole separating section 5 is extended to reach the inside of the bump 26a. With this configuration, the connecting section which includes the through-hole interconnection section 97(98) and the bump 26a are reinforced by the through-hole separating section 5.
In the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 23A to 23C, the through-hole separating section 5 is extended to reach the inside of the bump 26a. When the end 97c of the through-hole interconnection section 97(98) is extended to reach the inside of the bump 26a, the bump 26a between the through-hole separating section 5 and the through-hole interconnection section 97(98) is deformed toward the through-hole interconnection section 97(98). With this configuration, the through-hole interconnection section 97(98) and the bump 26a are more reliably surface-contacted.
Other Example 4 In the through-hole interconnection structure of the semiconductor wafer shown in FIG. 18, as shown in FIG. 1, although the through-hole separating section 51 is not in contact with the bump 26, the through-hole separating section 51 may be extended to reach the inside of the bump 26 as shown in FIG. 24. A manufacturing method of the semiconductor device shown in FIG. 24 is the same as that of the semiconductor device shown in FIG. 18 except the following point. In the process in which the end 92c of the through-hole interconnection section 92 on the back surface of the upper wafer 1WA is extended to reach the inside of the bump 26 on the principal surface of the lower wafer 1WB so that the bump 26 and the through-hole interconnection section 92 are made to contact with each other and are electrically contacted to each other, the through-hole separating section 51 is extended to reach the inside of the bump 26. Thus, description of the manufacturing method will be omitted.
FIG. 24 is an enlarged vertical longitudinal sectional view showing only a neighborhood of the bonding surface 30a of the upper wafer 1WA which is a part of the through-hole interconnection structure of the semiconductor wafer. FIG. 25A is an enlarged transverse cross-sectional view showing only the through-hole interconnection section 92, the through-hole separating section 51 and the bump 26 of the semiconductor device. The longitudinal cross-sectional view shown in FIG. 24 corresponds to line C-C in FIG. 25A. The transverse cross-sectional view (plan view) shown in FIG. 25A corresponds to line A-A in FIG. 24.
In this through-hole interconnection structure of the semiconductor wafer, the end 92c of the through-hole interconnection section 92 is extended to reach the inside of the bump 26. Thus, the through-hole interconnection section 92 and the bump 26 are reliably surface-contacted, and thus a more reliable and stable electric connection can be established between the wafers 1WA and 1WB.
The through-hole protruding section 92a protruding from the bonding surface 30a of the through-hole interconnection section 92 includes an oppositely-facing pair of wiring side walls 92b and 92b which extend from the bonding surface 30a toward the lower wafer 1WB. The bump 26 is placed between the pair of wiring side walls 92b and 92b. Accordingly, the contact area of the through-hole interconnection section 92 and the bump 26 becomes sufficiently large.
In the through-hole interconnection structure of the semiconductor wafer shown in FIG. 24, the through-hole separating section 51 which surrounds each of the wiring sections 92d and 92d which are the part of the through-hole interconnection section 92 is provided on the bonding surface 30a and protrudes from the bonding surface 30a. Further, the wiring sections 92d and 92d of the through-hole interconnection section 92 and the through-hole separating section 51 are integrally formed, and the end 92c of the through-hole interconnection section 92 is formed to protrude from an end of the through-hole separating section 51. With this configuration, when the end 92c of the through-hole interconnection section 92 is extended to reach the inside of the bump 26, the through-hole interconnection section 92 is reinforced by the through-hole separating section 51. Thus, a more reliable connection can be established between the through-hole interconnection section 92 and the bump 26.
In the through-hole interconnection structure of the semiconductor wafer shown in FIG. 24, the through-hole separating section 51 is extended to reach the inside of the bump 26. With this configuration, when the through-hole separating section 51 is extended to reach the inside of the bump 26, the bump 26 between the wiring sections 92d and 92d is pressed against the lower wafer 1WB by the through-hole separating section 51 and is expanded in the transverse direction. As a result, a more reliable connection is established between the through-hole interconnection section 92 and the bump 26, and thus these are more stably surface-contacted.
In the through-hole interconnection structure of the semiconductor wafer shown in FIG. 24, the through-hole separating section 51 is extended to reach the inside of the bump 26. With this configuration, the connecting section which includes the through-hole interconnection section 92 and the bump 26 is reinforced by the through-hole separating section 51.
The configuration of the transverse cross section of the through-hole interconnection section is not limited to that shown in FIG. 25A. Alternatively, the configurations shown in FIGS. 25B to 25D each corresponding to FIGS. 2B to 2D may be employed. The configuration of the transverse cross section of the through-hole interconnection section may be that shown in FIG. 25E.
FIG. 25E is an enlarged transverse cross-sectional view showing only a through-hole interconnection section 99 and the bump 26. The transverse cross-sectional view (plan view) shown in FIG. 25E corresponds to line A-A in FIG. 24 and the longitudinal cross-sectional view shown in FIG. 24 corresponds to line C-C in FIG. 25E.
The through-hole interconnection section 99 shown in FIG. 25E includes two wiring sections 99d and 99d which have rectangular transverse cross sections. The two wiring sections 99d and 99d are disposed in parallel. A peripheral part of each of the wiring sections 99d and 99d is surrounded by the through-hole separating section 51. The through-hole separating section 51 and the through-hole interconnection section 99 are integrally formed.
In the through-hole interconnection structure of the semiconductor wafer of the semiconductor device according to the invention, the through-hole interconnection section may have an area of the transverse cross section which is constant when seen in a vertical section. The end portion of the through-hole interconnection section, however, may have a varying transverse cross sectional area when seen in a vertical section. For example, the end portion of the through-hole interconnection section may have a transverse cross section of which area is gradually reduced toward the lower wafer 1WB. Such a configuration is preferred in that the through-hole interconnection section is easily extended to reach the inside of the bump.
Experiments A silicon substrate having diameter of 200 mm (8 inches) was used. A through-hole separating section and a through-hole interconnection section were formed in the same manner as in the through-hole interconnection structure of the semiconductor wafer shown in FIGS. 22A and 22B. A wafer was obtained with a principal surface having a bump underlying conductive pattern and a bump was formed thereon. The through-hole interconnection section includes two wiring sections disposed in parallel. The wiring sections were made of tungsten and have rectangular cross sections with length of 5.6 μm and width of 1.5 μm. The protruding length of the through-hole protruding section protruding from the bonding surface was 40 μm.
Three of these wafers were stacked. The through-hole interconnection section and the bump are connected between the wafers at the grid positions shown in FIG. 26. In this manner, the three wafers were bonded together to form a test piece shown in FIG. 26.
Six of such test pieces were prepared. Each test piece was measured at 58 measuring points arranged on the shadowed grids shown in FIG. 26. The electric resistance value was measured in the electric connection in the connecting section of the through-hole interconnection section of the upper wafer and the bump of middle wafer at the 58 measuring points. The electric resistance values were obtained for 310 measuring points of the 348 measuring points. The thus-obtained electric resistance values had an average of 0.5Ω±0.2Ω.
The data of the electric resistance values of 310 measuring points is shown in FIG. 27. FIG. 27 is a graph showing the electric resistance values in the electric connection between the upper wafer and the middle wafer which together constitute a wafer shown in FIG. 26, and the variation in the electric resistance values. The vertical axis shows frequency (i.e., the number of data) and the horizontal axis shows the electric resistance value.
As shown in FIG. 27, in the test piece shown in FIG. 26, it was confirmed that the electric resistance value in the inter-wafer electric connection was sufficiently small, and the variation in the electric resistance values was also small.
While preferred embodiments of the invention have been described and illustrated above and it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions and substitutions, and other modifications can be made without departing from the spirit or scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.
