Systems and Methods for Generating Predicates and Assertions
Systems and methods for deriving a predicate by constructing a logic formula from information recorded during test execution, optimizing the logic formula and computing the logical implication of the optimized logic formula. Systems and methods for deriving an assertion from a logical implication by substituting each predicate in the logical implication with corresponding design elements from a hardware design description, inserting the design elements into a target template, inserting a context-sensitive input of the target template based on design elements in the hardware design description and creating an instance name for an instantiation of the target template. Systems and methods for generating a set of clauses that are implied by a disjunctive normal formula of a set of cubes.
The present application is a Continuation in Part and claims the priority benefit of U.S. patent application Ser. No. 11/672,919 filed Feb. 8, 2007 and entitled “Methods for Automatically Generating Assertions,” which claims the priority benefit of U.S. provisional patent application No. 60/766,746 filed Feb. 9, 2006 and entitled “Methods for Automatically Generating Assertions.” The disclosure of these applications is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to electronic design automation. More specifically, the present invention relates to systems and methods for deriving predicates and assertions related to a digital hardware design.
2. Description of the Related Art
Today's hardware systems in general and integrated circuit devices in particular are commonly designed and verified through the use of an electronic design automation system. The design cycle typically involves iterative testing of a digital hardware design, represented by a hardware design description, to verify if the design operates as specified in the design specification. The electronic design automation system usually comprises a simulator or emulator (collectively referred to as simulator hereinafter) capable of loading a high level behavioral description of a digital hardware design (e.g. described in a hardware design language like Verilog). The design under test or device under test is sometimes referred to as DUT. The simulator is furthermore usually capable of loading a test that provides stimuli for inputs of the DUT. Finally, some module or entity is required to determine the result of the test. This module or entity could be an output checker, a rules monitor, a set of predicates, or any combination thereof.
In test environment 100 the simulator is implied and not shown for purposes of clarity of the illustration. The design under test 120 can be based on a behavioral description of a digital hardware design. Such descriptions commonly make use of variables that represent design elements. In design under test 120 these variables are arbitrarily labeled A, B, C, and D. These may represent (multi-bit) registers, latches, signals or any other design element that is part of design under test 120. The test or device that provides stimuli to the design is part of test environment 100, but implied and not shown in
The module or entity that determines the result of the test in test environment 100 is the set of predicates 110. Additional or alternative modules or entities for the same purpose are not shown in
When a test is executed, the simulator (or a dedicated module or entity that is a part of test environment 100) can monitor or record information about these formulas. For example, these formulas can be evaluated and found to be true or false at any particular time during test execution. This information can be used in the design cycle. The set of predicates 110 can be a part of the design specification. A formula consisting of a set of predicates connected by Boolean operators that is specified to be true under certain conditions is sometimes referred to as an assertion or a design assertion. Assertions are useful and valuable in design verification. Any Boolean combination of basic predicates may also be referred to as a composite predicate. Composite predicates are considered more powerful than basic predicates provided that they are specified to be true under certain conditions.
To improve the quality and speed of the design cycle and the quality of the design it may be beneficial to the user of an electronic design automation system to use more powerful predicates and assertions during the testing process.
SUMMARY OF THE PRESENTLY CLAIMED INVENTIONIn accordance with the present invention, systems and methods for deriving predicates and assertions related to a digital hardware design are disclosed. In one embodiment of the present technology described herein, the method includes constructing a logic formula from information recorded during test execution, optimizing the logic formula, and computing the logical implication of the optimized logic formula. A DUT can be described by a hardware design description. The recorded information can include an evaluation of a given set of predicates related to the digital hardware design. The logic formula can be in disjunctive normal form and can include a complete assignment of a set of predicates for a consecutive interval during test execution. The logic formula can be constructed in part by substituting statements about variables for corresponding predicates. Computation of an assertion based on the logic formula can involve the reverse substitution. The constructed logic formula can be reduced in size and complexity by applying mathematical optimization techniques.
Another embodiment of the present technology is a system that derives predicates according to the presented method. The system can include a processor and a memory communicatively coupled with the processor, a construction engine, an optimization engine, and an implication engine. The construction engine can construct a logic formula from information recorded during test execution. The optimization engine can optimize the logic formula. The implication engine can compute a logical implication of the optimized logic formula. In another embodiment of the present technology, the system can include a processor and a memory communicatively coupled with the processor, a substitution engine, one or two insertions engines, and a naming engine. The substitution engine can substitute each predicate in a logic implication with corresponding design elements from a hardware design description. The insertion engine can insert the design elements into a target template. The same insertion engine or a second insertion engine can insert a context-sensitive input of a target template based on design elements in the hardware design description. The naming engine can create an instance name for an instantiation of the target template.
In one more embodiment of the present technology, the system can include a processor and a memory communicatively coupled with the processor, a cube search engine, a cube edit engine, a cube delete engine, and a control engine. The cube search engine can search through a set of cubes that comprise a logic formula in disjunctive normal form (DNF) to find a subset of cubes in which a particular literal appears. The cube edit engine can modify each cube in a set of cubes in a particular way, for example by removing a particular literal (i.e. a Boolean variable or its negation) from all cubes. The cube delete engine can change a set of cubes by deleting a subset of cubes from the set of cubes. The control engine can sequentially and concurrently control the operation of the cube search engine, the cube edit engine, and the cube delete engine to generate clauses that are implied by a set of cubes, wherein a clause is a disjunction of one or more literals.
In another embodiment of the present technology, the method includes substituting each predicate in a logical implication with corresponding statements about design elements from a hardware design description, inserting the design elements into a target template, inserting a context-sensitive input of the target template based on design elements in the hardware design description, and creating an instance name for an instantiation of the target template. The target template can be in SystemVerilog Assertions (SVA) format, or Property Specification Language (PSL) format, or a hardware design language format. A unique instance name can be created by using an md5 encoding of the string that represents the logical implication to create a hash string that is part of the instance name.
Another embodiment of the present technology is a computer readable storage medium that derives assertions according to the presented method.
Embodiments of the present technology described herein allow for systems and methods for deriving predicates and assertions related to a hardware design description. The test environment 100 in
At step 801 M is set to N and a state is set to an initial state such as 1. The number N may be any number. A set of all literals L that appears in at least 1/M cubes in d are created at step 802. This may be performed by invoking cube search engine 575 repeatedly. A literal L is selected and removed from the created set at step 803. In some embodiments, a literal can be selected at random, in an order of appearance, or based on other criteria.
A determination is made as to whether M=0 or there are no literals L within the set at step 804. If M does not equal zero and there are literals left in the set, the method continues to step 807. If M equals zero or no literals L exist in the set, a determination is made as to whether the iteration should continue for the current state at step 805. The current iteration may continue if, for example, the previous call stack is not empty. If the current iteration should not continue, the generated clauses are returned as a set and the method ends. If the current iteration should continue at step 805, a new literal is selected from a previous call stack, the new literal is removed from the stack and the method of
If M is not equal to zero and there are literals within the set, the method of
At step 809, M is decremented from N to N-1 and the state is incremented. The method of
The computing system 900 of
The components shown in
Mass storage device 930, which may be implemented with a magnetic disk drive or an optical disk drive, is a non-volatile storage device for storing data and instructions for use by processor unit 910. Mass storage device 930 can store the system software for implementing embodiments of the present invention for purposes of loading that software into main memory 920.
Portable storage device 940 operates in conjunction with a portable non-volatile storage medium, such as a floppy disk, compact disk or digital video disc, to input and output data and code to and from the computer system 900 of
Input devices 960 provide a portion of a user interface. Input devices 960 may include an alpha-numeric keypad, such as a keyboard, for inputting alpha-numeric and other information, or a pointing device, such as a mouse, a trackball, stylus, or cursor direction keys. Additionally, the system 900 as shown in
Display system 970 may include a CRT, a liquid crystal display (LCD) or other suitable display device. Display system 970 receives textual and graphical information, and processes the information for output to the display device.
Peripherals 980 may include any type of computer support device to add additional functionality to the computer system. For example, peripheral device(s) 980 may include a modem or a router.
The components contained in the computer system 900 of
It is noteworthy that any hardware platform suitable for performing the processing described herein is suitable for use with the presented technology. Computer-readable storage media refer to any medium or media that participate in providing instructions to a central processing unit (CPU), a processor, a microcontroller, or the like. Such media can take forms including, but not limited to, non-volatile and volatile media such as optical or magnetic disks and dynamic memory, respectively. Common forms of computer-readable storage media include a floppy disk, a flexible disk, a hard disk, magnetic tape, any other magnetic storage medium, a CD-ROM disk, digital video disk (DVD), any other optical storage medium, RAM, PROM, EPROM, a FLASHEPROM, any other memory chip or cartridge.
The embodiments disclosed herein are illustrative. Various modifications or adaptations of the systems and methods described herein can become apparent to those skilled in the art. Such modifications, adaptations, and/or variations that rely upon the teachings of the present disclosure and through which these teachings have advanced the art are considered to be within the spirit and scope of the present invention. Hence, the descriptions and drawings herein should be limited by reference to the specific limitations set forth in the claims appended hereto.
Claims
1. A computer-implemented method for deriving a predicate, the method comprising:
- constructing a logic formula by executing a construction engine stored in memory, the logic formula constructed from information recorded during test execution;
- optimizing the logic formula by executing an optimization engine stored in memory; and
- computing a logical implication by executing an implication engine stored in memory, the logical implication computed of the optimized logic formula.
2. The computer-implemented method of claim 1, wherein the subject of the test is a hardware design description.
3. The computer-implemented method of claim 2, wherein the recorded information comprises an evaluation of a set of predicates related to the hardware design description.
4. The computer-implemented method of claim 1, wherein the logic formula is in disjunctive normal form.
5. The computer-implemented method of claim 3, wherein the logic formula includes a complete assignment of the set of predicates for a consecutive interval during test execution.
6. The computer-implemented method of claim 3, wherein the constructing step includes substituting Boolean variables for predicates.
7. The computer-implemented method of claim 6, wherein the logic formula is reduced by a reduction engine stored in memory, prior to the optimizing step.
8. The computer-implemented method of claim 6, wherein the computing step includes substituting predicates of the logical implication for Boolean variables.
9. The computer-implemented method of claim 2, wherein the test is executed in a cycle-based simulation environment.
10. The computer-implemented method of claim 2, wherein the test is executed in an event-based simulation environment.
11. The computer-implemented method of claim 1, wherein the logical implication is in conjunctive normal form.
12. A computer-implemented method for deriving an assertion from a logical implication, comprising:
- substituting each predicate in the logical implication with corresponding design elements from a hardware design description by executing a substitution engine stored in memory;
- inserting the design elements into a target template by executing an insertion engine stored in memory;
- inserting at least one context-sensitive input of the target template based on design elements in the hardware design description by executing an insertion engine stored in memory; and
- creating an instance name for an instantiation of the target template by executing a naming engine stored in memory.
13. The computer-implemented method of claim 12, wherein the target template is in SystemVerilog Assertions (SVA) format.
14. The computer-implemented method of claim 12, wherein the target template is in Property Specification Language (PSL) format.
15. The computer-implemented method of claim 12, wherein the target template is in a hardware description language.
16. The computer-implemented method of claim 12, wherein the creating step uses an md5 encoding of the string that represents the logical implication to create a unique hash string that is part of the instance name.
17. A computer readable storage medium having embodied thereon a program, the program being executable by a processor to perform a method for deriving a predicate, the method comprising:
- constructing a logic formula from information recorded during test execution;
- optimizing the logic formula; and
- computing a logical implication of the optimized logic formula.
18. The computer readable storage medium of claim 17, wherein the subject of the test is a hardware design description.
19. The computer readable storage medium of claim 18, wherein the recorded information comprises an evaluation of a set of predicates related to the hardware design description.
20. The computer readable storage medium of claim 19, wherein the construction of the logic formula includes substituting Boolean variables for predicates.
21. A computer readable storage medium having embodied thereon a program, the program being executable by a processor to perform a method for deriving an assertion from a logical implication, comprising:
- substituting each predicate in the logical implication with corresponding design elements from a hardware design description;
- inserting the design elements into a target template;
- inserting at least one context-sensitive input of the target template based on design elements in the hardware design description; and
- creating an instance name for an instantiation of the target template.
22. The computer readable storage medium of claim 21, wherein the target template is in SystemVerilog Assertions (SVA) format.
23. The computer-implemented method of claim 21, wherein the target template is in a hardware description language.
24. A system for deriving a predicate, the system comprising:
- a processor;
- a network;
- a memory communicatively coupled with the processor through the network;
- a construction engine stored in the memory and configured to be executed by the processor to construct a logic formula from information recorded during test execution;
- an optimization engine stored in the memory and configured to be executed by the processor to optimize the logic formula; and
- an implication engine stored in the memory and configured to be executed by the processor to compute a logical implication of the optimized logic formula.
25. The system of claim 24, further comprising a test engine configured to execute at least one test on a hardware design description.
26. The system of claim 25, further comprising a recording engine configured to record information during test execution.
27. A computer-implemented recursive method for generating a set of clauses, the clauses having a size less than or equal to a selected number M, wherein the clauses are implied by a disjunctive normal formula of a set of cubes, the method comprising:
- creating a set of all literals L that appear in at least 1/M cubes in the disjunctive normal formula;
- for each literal L in the set of literals, perform the following three steps recursively: remove all cubes that contain literal L from the disjunctive normal formula of a set of cubes, remove all literals L from all cubes in the disjunctive normal formula of a set of cubes, and generate a set of clauses of size less than or equal to M-1 that is implied by the disjunctive normal formula of the remaining set of cubes;
- collecting all picked literals as one clause if the total number of cubes in the set of cubes equals zero; and;
- collecting the generated clauses into a set.
28. A system for generating a set of clauses that are implied by a disjunctive normal formula of a set of cubes, the system comprising:
- a processor;
- a network;
- a memory communicatively coupled with the processor through the network;
- a cube search engine stored in the memory and configured to be executed by the processor to search through a set of cubes for a set of all literals that appear in at least 1/M cubes in the set of cubes;
- a cube delete engine stored in the memory and configured to be executed by the processor to remove all cubes that contain a selected literal from a set of cubes;
- a cube edit engine stored in the memory and configured to be executed by the processor to remove the negation of a selected literal from the cubes in a set of cubes; and
- a control engine stored in the memory and configured to be executed by the processor to: control a recursive process to generate all clauses of size less than or equal to a selected number M that are implied by a disjunctive normal formula of a set of cubes, select a literal from the set of literals returned by the cube search engine, invoke the cube delete engine and cube edit engine until the set of cubes is empty, recursively invoke the control engine to generate all clauses of size less than or equal to a selected number M-1 that are implied by a disjunctive normal formula of a set of cubes, until M is equal to zero, collect the selected literals into a clause if the set of cubes is empty, and collect the generated clauses into a set if the set of literals is empty.
29. A computer-implemented method for constructing a predicate, the method comprising:
- executing a test by executing a test engine stored in memory;
- recording information during test execution by executing a recording engine;
- constructing a predicate by executing a construction engine stored in memory, the logic formula constructed based on information recorded during test execution.
Type: Application
Filed: Dec 9, 2009
Publication Date: Apr 8, 2010
Inventors: Yuan Lu (San Jose, CA), Yunshan Zhu (Cupertino, CA)
Application Number: 12/634,586
International Classification: G06F 15/18 (20060101); G06N 5/02 (20060101);