Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Abstract: The present invention provides a vessel navigation boundary collision avoidance method. Specifically, the vessel navigation boundary collision avoidance method first performs step (A) of providing at least one boundary. In step (B), a plurality of dummy ships are established along the at least one boundary, wherein the dummy ships are freezing and each of the dummy ships is connected to at least a part of another via an intersection point. In step (C), a dummy ship domain and a dummy obstacle domain are sequentially formed according to each of the dummy ships and each of the intersection points. In step (D), a dummy ship anti-collision circle and a dummy obstacle anti-collision circle are sequentially generated based on the dummy ship domain and the dummy obstacle domain if a sailing ship domain is to have a possibility of invading the dummy ship domain and the dummy obstacle domain.

Abstract: Disclosed in the present invention are an asynchronous blockchain consensus method and system with decoupled data broadcast and consensus, an electronic device and a storage medium. The system comprises a plurality of nodes, wherein the nodes may be co-served by a plurality of mutually trusted physical or virtual devices.

Abstract: A solid-state storage device is provided, which includes a controller and a non-volatile memory. The controller selects a first word line group from a plurality of word line groups obtained by classifying the word lines based on a read threshold voltage of each word line, and a representative word line corresponding to each word line group is set based on the read threshold voltage associated with each word line group. The controller uses the read threshold voltage of a first representative word line corresponding to the first word line group to read page data of the first representative word line. When the controller cannot correctly read the page data of the first representative word line using the read threshold voltage of the first representative word line, the controller updates the read threshold voltage of the first representative word line in the first word line group.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.

Abstract: The present invention relates to carbamoyl phenylalaninol compounds and methods of using the same to treat disorders. The invention further relates to the development of methods for treating excessive sleepiness in a subject, e.g., due to narcolepsy or obstructive sleep apnea, with the surprising outcome that “normal” levels of wakefulness are achieved based on standard objective and subjective sleepiness tests.

Abstract: A material comprising an epoxy/elastomer adduct, a polymeric particle, from about 0.05 to about 20 weight percent of an epoxy/diacid adduct, and optionally, an amine reaction product.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.

Abstract: A material comprising an epoxy/elastomer adduct, a polymeric particle, from about 0.05 to about 20 weight percent of an epoxy/diacid adduct, and optionally, an amine reaction product.

Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

Abstract: An antenna structure is provided. The antenna structure includes a first metal element and a second metal element. The first metal element includes a first slot that extends along a first direction to form an elongated shape. The second metal element includes a first branch portion including a first open section and a part section. The first open section extends along the first direction to form an open end, and the part section extends along a second direction to form an open end. A projection of the part section and a projection of the first slot are partially overlapped when being observed along a third direction. The first direction, the second direction, and the third direction are perpendicular to one another.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.