METHOD AND SYSTEM FOR VARIABLE-GAIN AMPLIFIER
Method for a variable-gain amplifier (VGA). A plurality of attenuator nodes is serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier. Each of the attenuator nodes includes a transistor and an RC circuitry that couples drain, gate, and source terminals of the transistor to a control signal for the attenuator node. The VGA also includes an amplifier that has an output produced based on an input to the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes. The RC circuitry for each attenuator node is configured to pass a control signal to the gate terminal of the transistor of the attenuator node in accordance with a first time scale and permit the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the transistor while the transistor is transitioning between on and off states.
1. Field of Invention
The present teachings presented herein relate to a variable-gain amplifier. More specifically, the present teachings relate to methods and systems for improved variable-gain amplifier employing a tapped-attenuator ladder.
2. Discussion of Related Art
A variable gain amplifier (VGA) is used in a wide variety of communication system applications. In most applications, it is necessary for the VGA to maintain good dynamic range across the full gain control range. Other desirable characteristics of a VGA include high linearity, linear-in-dB gain control, low noise, low DC power consumption, CMOS compatibility, high frequency operation, large signal handling capability, and a gain control relation that is insensitive to ambient temperature.
VGA's have been used for many years, and a variety of techniques have been employed to achieve this critical circuit function. The types of VGA's reported in the literature generally fall into several broad categories. Current steering is an abundant method that usually employs some type of emitter-coupled bipolar junction transistor (BJT) pair to steer a fraction of current based on a ΔVbe control voltage. The bias control method alters the bias point of a transistor device to affect gm and the resulting gain. PIN diodes or MOSFET resistors are often used to degenerate the gain of amplifiers in a continuously variable fashion. Another method relies on a class of circuits known as multi-Tanh cells to affect the gain of a gm block. Although simple to implement, these four general methods to realize a VGA often suffer from poor linearity and small input signal handling capability.
One approach to address some of the short-comings of conventional VGAs is disclosed in U.S. Pat. No. 5,077,541 by Gilbert, entitled “Variable-Gain Amplifier Controlled by an Analog Signal and Having a Large Dynamic Range,” issued Dec. 31, 1991. This patent describes a variable-gain amplifier employing a fixed resistive attenuator ladder with a plurality of high impedance tap points to sample the signal at each of the attenuator nodes. The signal voltage at these tap points are converted to signal currents that are summed into an operational amplifier to create a composite gain function. The effective transconductance gain of each tap point is varied in the specified method to produce a continuous gain function. The fixed attenuator ladder aims at providing a stable input impedance with large input signal handling capability across the entire linear-in-dB gain range.
Although Gilbert method of signal tapping and gain interpolation control may be attractive in bipolar technology, it is less desirable in CMOS technology. Implementing the gm taps in CMOS is prone to upconverted 1/f noise due to the nature of current-carrying MOS transistors, and the gm errors are substantially greater due to the poor MOSFET Vth matching compared to BJT Vbe matching.
A CMOS-compatible, attenuator-based VGA is disclosed in U.S. Pat. No. 7,205,817 by Huang, entitled “Analog Control Integrated FET Based Variable Attenuator,” issued Apr. 17, 2007. This patent describes a method of assembling and controlling a plurality of series and parallel MOS devices to implement a variable attenuator. Huang avoids critical Vth matching issues and eliminates DC bias currents within the attenuator, but it involves controlling both the series and parallel elements along the attenuator ladder. This yields a more difficult control circuit that often results in a gain-control function with significantly bumpy deviations from the ideal linear-in-dB gain law. Controlling distortion throughout the gain control range is also difficult and requires floating P-wells of a sort not typically found in a standard N-well CMOS process.
SUMMARYAn improved variable-gain amplifier (VGA) is disclosed. According to one aspect of the present teaching, an improved VGA includes a plurality of attenuator nodes serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier. Each attenuator node comprises a transistor and an RC circuitry that couples drain, gate, and source terminals of the transistor to a control signal for the attenuator node. The improved VGA further includes an amplifier having an output produced based on an input to the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes. In this improved VGA, the RC circuitry for each attenuator node is configured to pass a control signal to the gate terminal of the transistor of the attenuator node in accordance with a first time scale and permit the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the transistor while the transistor is transitioning between on and off states. The term “float” denotes the effect whereby the AC gate voltage follows a weighted average of the source and drain AC voltages.
According to a different aspect of the present teaching, an improved VGA a plurality of attenuator nodes serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier. Each attenuator node comprises a first transistor, an RC circuitry that couples drain, gate, and source terminals of the first transistor to a control signal for the attenuator node, and an RC enabling circuitry. The improved VGA also includes an amplifier having an output produced based on an input of the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes. In the improved VGA according to this aspect of the present teaching, the RC circuitry for each attenuator node passes a first control signal to the gate terminal of the first transistor of the attenuator node in accordance with a first time scale and permits the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the first transistor while the first transistor is transitioning between on and off states. In addition, the RC enabling circuitry of each attenuator node is capable of decoupling the RC circuitry when operating so as to minimize loading to the input to the amplifier.
According to another aspect of the present teaching, an improved VGA comprises a plurality of attenuator nodes serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier, wherein each of the attenuator node comprises a first transistor and an RC circuitry that couples drain, gate, and source terminals of the first transistor to a control signal for the attenuator node. The improved VGA also includes an amplifier having an output produced based on an input of the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes. The RC circuitry for each attenuator node passes a first control signal to the gate terminal of the first transistor of the attenuator node in accordance with a first time scale and permits the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the first transistor while the first transistor is transitioning between on and off states. The improved VGA further have at least some attenuator nodes at the early stages of the attenuator ladder that include a gate clamping circuitry therein, each gate clamping circuitry having three terminals connecting to the gate of the first transistor, a second control signal, and a ground, respectively.
The present teaching also discloses an improved differential variable-gain amplifier (DVGA). The improved DVGA comprises a first set of attenuator nodes serially connected via a first set of resistors between adjacent first set of attenuator nodes to form a first attenuator ladder and coupled to a first AC input of the DVGA and a first amplifier having a first output produced based on an input of the first amplifier connected to a first plurality of coupled terminals, each of which is respectively from one of the first set of attenuator nodes. The improved DVGA also comprises a second set of attenuator nodes serially connected via a second set of resistors between adjacent second set of attenuator nodes to form a second attenuator ladder and coupled to a second AC input of the DVGA and a second amplifier having a second output produced based on an input of the second amplifier connected to a second plurality of coupled terminals, each of which is respectively from one of the second set of attenuator nodes. Each of the first and second sets of attenuator nodes comprises a transistor and an RC circuitry that couples drain, gate, and source terminals of the transistor to a control signal for the attenuator node. The RC circuitry for each attenuator node is configured to pass a control signal to the gate terminal of the transistor of the attenuator node in accordance with a first time scale and permit the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the transistor while the transistor is transitioning between on and off states.
The teachings claimed and/or described herein are further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein:
The present teaching discloses improved VGA. The exemplary implementations described herein include an N-well CMOS process with a threshold of 0.7 Volts for NMOSFET, i.e., Vth=0.7V, operating with a single 3V supply. The exemplary attenuator circuits illustrated herein employ a 50-Ohm, single-ended, ground referenced, five-node attenuator ladder with 4 dB of attenuation per stage. These exemplary embodiments are intended to simplify and clarify the detailed descriptions contained herein and are not intended to limit the scope of the present teaching.
In general, the tap transistors and RC networks for each attenuator node can be tailored separately. In some embodiments, such as the one shown herein, identical NMOS transistors and RC networks are employed for all stages of attenuator nodes.
In operation, when a control signal is used to tap on a single attenuator node, the attenuator circuit behaves in accordance with the principles of a common digital attenuator. In this case, the tapped transistor is switched ON when a sufficiently positive voltage is supplied to the gate of the NMOS transistor. To keep all other remaining transistors switched OFF, a sufficiently low control voltage can be supplied to the gate terminals of these transistors. In this exemplary situation, the voltage gain to the amplifier 160 (or high ZIN buffer) is the corresponding attenuation to the tapped attenuator node.
When two or more adjacent attenuator nodes are tapped using their corresponding control signals, the behavior of the VGA circuit 100 is more complex. In this case, the input to the amplifier 160 from the coupled drain of the tapped attenuator nodes is a weighted sum of these multiple attenuator nodes. In addition, the transistor conduction also produces undesirable loading and distortion to the attenuator ladder. Some loading effects may be inevitable for this type of passive NMOS signal tapping. However, the loading effects are generally negligible when no more than two adjacent tap transistors are conducting at any given time and the attenuator step size between adjacent nodes is less than approximately 6 dB.
Besides the loading effects, when two or more adjacent attenuator nodes are tapped, the attenuator nodes may also produce distortion effects. This includes intermodulation distortion and harmonic distortion. It is known that such distortion effects are more difficult to suppress. While the distortion of a completely ON or completely OFF transistor is usually negligible, a partially conducting transistor, particularly when it is near its threshold voltage, may create pronounced distortion products, often 30-50 dB higher than that when it is at a purely ON or OFF state. Extensive computer simulations reveal that although these distortion cannot be eliminated, they can be substantially suppressed when an appropriate control sequence is applied to a properly designed VGA circuit.
A control sequence refers to a series of control signals used to tap the transistors in each attenuator node along the attenuator ladder. In the illustrative embodiment, such a control sequence corresponds to Vc1, Vc2, Vc3, Vc4, Vc5.
In some embodiments, a preferred control sequence is such that it aims at always keeping one FET device completely ON whenever an adjacent FET device is transitioning through its threshold region. Here, a transition includes both the transition from an OFF state to an ON state and the transition from an ON state to an OFF state. For example, between Q1 and Q2, either keep Q1 ON while Q2 is transitioning from OFF to ON state or keep Q2 ON while Q1 is transitioning from ON state to OFF state. This is so called two-step transition. It is found that this provides a maximum parallel resistive loading to the transitioning FET and has an effect of reducing distortion products when a transistor in an attenuator is near its threshold, i.e., going through a transition. The two-step transition can be applied in a consecutive manner along the attenuator ladder. For example, attenuator node #1 can be kept on while attenuator node #2 is transitioning from OFF to ON state. Then attenuator node #2 can be kept on while attenuator node #1 is transitioning from ON state to OFF state. Attenuator node #2 is kept on while attenuator node #3 is transitioning from OFF to ON state, etc.
Using such a control sequence, at any point along the gain control sequence, two transistors are made active, i.e., either in an ON state or in a transition, in order to control the effective attenuation of the tapped stages. Other transistors or stages are accordingly made inactive or OFF. To enable this, the sequence of control signals, i.e., Vc1, Vc2, Vc3, Vc4, Vc5, are supplied to transistors Q1, Q2, Q3, Q4, and Q5 (130-a, . . . , 130-e) in such a way so that at any given time, only two transistors in adjacent attenuator nodes are active. To ensure that the NMOS transistors in other attenuator nodes are inactive, a low control signal can be applied to these NMOS transistors so that they are completely OFF.
In
One exemplary embodiment of a VGA 200 in accordance with the present teaching incorporating a detailed RC circuit design is depicted in
In
There are some positive effect as to distortion when the value of Rc is increased.
A complete set of transitions as applied to the exemplary 5-stage attenuator ladder (250) in a consecutive manner from attenuator node #1 through #5 is illustrated in
As discussed herein, the loading effect of the series RC branches to the attenuator ladder is usually not significant. But the loading to the input of the high ZIN buffer or amplifier 240 can be significant at higher frequencies, especially for attenuator ladders with a large number of tapped nodes. To address the issue of loading effect to the amplifier input, a circuit can be added to the VGA circuit disclosed to effectively enable or decouple the RC circuit in each attenuator node whenever it is appropriate.
In operation, when an attenuator node is neither active nor adjacent to an active node, this attenuator is not involved in an ongoing attenuator transition or any imminent attenuator transition. In this case, the attenuator node can be effectively removed from the VGA operational circuit using a low voltage on the control signal connected to the resistor, e.g., 520-a or VENBL as shown in
Additionally, the series RC network as depicted in
To reduce the negative effect of such leakage, a gate clamping circuit may be incorporated in the VGA circuit 200 or 500.
Such a gate clamping circuit serves to clamp OFF an early NMOS device, such as Q1 or Q2, using a suitable low VCLAMP signal. In operation, this grounds the gates of transistors so that it prevents large signals from leaking through inactive nodes of early stages while the nodes from later stages are active. In this way, it improves the large signal amplitude performance. The low voltage used to ground the transistor is usually supplied after the attenuator node is in an inactive state and is not adjacent to an active node. The benefit of this embellishment can be more appreciated as the attenuator range increases.
In
In
The exemplary embodiments depicted in
Differential VGA circuits based on the illustrative embodiments as shown in
While the inventions have been described with reference to the certain illustrated embodiments, the words that have been used herein are words of description, rather than words of limitation. Changes may be made, within the purview of the appended claims, without departing from the scope and spirit of the invention in its aspects. Although the inventions have been described herein with reference to particular structures, acts, and materials, the invention is not to be limited to the particulars disclosed, but rather can be embodied in a wide variety of forms, some of which may be quite different from those of the disclosed embodiments, and extends to all equivalent structures, acts, and, materials, such as are within the scope of the appended claims.
Claims
1. A variable-gain amplifier (VGA), comprising:
- a plurality of attenuator nodes serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier, wherein each of the attenuator nodes comprises a transistor and an RC circuitry that couples a drain, a gate, and a source terminals of the transistor to a control signal for the attenuator node; and
- an amplifier having an output produced based on an input to the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes, wherein
- the RC circuitry for each attenuator node is configured to pass a control signal to the gate terminal of the transistor of the attenuator node in accordance with a first time scale and permit the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the transistor while the transistor is transitioning between on and off states.
2. The VGA of claim 1, wherein the first time scale is greater than 10 AC cycles.
3. The VGA of claim 1, wherein the second time scale is substantially shorter than the first time scale.
4. The VGA of claim 1, wherein the second time scale is substantially one AC cycle.
5. The VGA according to claim 1, wherein the distortion includes at least one of intermodulation distortion and harmonic distortion.
6. The VGA of claim 1, wherein the drain of the transistor in each attenuator node is connected to at least one of the first set of resistors, which are coupled to the AC input, and a ground via a second resistor, the source of the transistor is coupled, together with sources of transistors of other attenuator nodes, to the input of the amplifier.
7. The VGA of claim 1, where the RC circuitry of an attenuator node comprises:
- a first RC branch coupling the gate and the source of the transistor of the attenuator node;
- a second RC branch coupling the gate and drain of the transistor of the attenuator node; and
- a third resistor which passes the control signal to the gate of the transistor of the attenuator node.
8. The VGA of claim 7, wherein the first RC branch comprises a fourth resistor and a first capacitor, the fourth resistor is coupled to the gate of the transistor and serially connected to the first capacitor, which is connected to the source of the transistor.
9. The VGA of claim 7, wherein the second RC branch comprises a fifth resistor and a second capacitor, the fifth resistor is coupled to the gate of the transistor and serially connected to the second capacitor, which is connected to the drain of the transistor.
10. The VGA of claim 7, wherein resistance of the first and second RC branches is selected to minimally load the attenuator ladder and allow the gate to float in accordance with the second time scale.
11. The VGA of claim 7, wherein the third resistor is selected so as to allow sufficient gate floating yet capable of responding quickly to changes in the control signal.
12. The VGA according to claim 1, wherein an attenuator step size between adjacent nodes is below 6 dB.
13. The VGA of claim 1, wherein continuous gain control is realized via a continuous two-step transition between every two adjacent attenuator nodes along the attenuator ladder, where in each two-step transition, only two adjacent attenuator nodes are activated using the control signals supplied to the two attenuator nodes and at least one of the activated attenuator nodes is on during each two-step transition period.
14. A variable-gain amplifier (VGA), comprising:
- a plurality of attenuator nodes serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier, wherein each of the attenuator nodes comprises a first transistor, an RC circuitry that couples drain, gate, and source terminals of the first transistor to a control signal for the attenuator node, and an RC enabling circuitry; and
- an amplifier having an output produced based on an input of the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes, wherein
- the RC circuitry for each attenuator node passes a first control signal to the gate terminal of the first transistor of the attenuator node in accordance with a first time scale and permits the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the first transistor while the first transistor is transitioning between on and off states, and
- the RC enabling circuitry of each attenuator node is capable of decoupling the RC circuitry when operating so as to minimize loading to the input to the amplifier.
15. The VGA of claim 14, wherein the source of the first transistor in each attenuator node is connected to at least one of the first set of resistors, which are coupled to the AC input, and a ground via a second resistor, the drain of the first transistor is coupled to the input of the amplifier.
16. The VGA of claim 14, where the RC circuitry of an attenuator node comprises:
- a first RC branch coupling the gate and the source of the first transistor of the attenuator node and having a third resistor and a first capacitor, the third resistor is coupled to the gate of the first transistor and serially connected to the first capacitor, which is connected to the source of the first transistor;
- a second RC branch coupling the gate and drain of the first transistor of the attenuator node and having a fourth resistor and a second capacitor, the fourth resistor is coupled to the gate of the first transistor and serially connected to the second capacitor, which is connected to the RC decoupling circuitry; and
- a fifth resistor which passes the first control signal to the gate of the first transistor of the attenuator node.
17. The VGA of claim 16, wherein the RC enabling circuitry comprises a second transistor and a sixth resistor, where the source of the second transistor is serially connected to the second capacitor, the drain of the second transistor is connected to the input of the amplifier, and the gate of the second transistor is serially coupled to a second control signal via the sixth resistor.
18. The VGA of claim 17, wherein continuous gain control for the VGA is realized via a continuous two-step transition between every two adjacent attenuator nodes along the attenuator ladder, where in each two-step transition, only two adjacent attenuator nodes are activated via the first control signals supplied to the two attenuator nodes, respectively, and at least one of the two activated attenuator nodes is on during each two-step transition period.
19. The VGA of claim 18, wherein the second control signal turns on the second transistor permitting the RC circuitry to connect to the input of the amplifier when the corresponding attenuator node is active or adjacent to an active attenuator node, and turns off the second transistor when the corresponding attenuator node is not active and not adjacent to an active attenuator so as to decouple the RC circuitry from the input to the amplifier.
20. A variable-gain amplifier (VGA), comprising:
- a plurality of attenuator nodes serially connected via a first set of resistors between adjacent attenuator nodes to form an attenuator ladder and coupled to an AC input of the variable-gain amplifier, wherein each of the attenuator nodes comprises a first transistor and an RC circuitry that couples a drain, a gate, and a source terminals of the first transistor to a control signal for the attenuator node; and
- an amplifier having an output produced based on an input of the amplifier connected to a plurality of coupled terminals, each of which is respectively from one of the plurality of attenuator nodes, wherein
- the RC circuitry for each attenuator node passes a first control signal to the gate terminal of the first transistor of the attenuator node in accordance with a first time scale and permit the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the first transistor while the first transistor is transitioning between on and off states, and
- at least some attenuator nodes at early stage of the attenuator ladder include a gate clamping circuitry therein, each gate clamping circuitry having three terminals connecting to the gate of the first transistor, a second control signal, and a ground, respectively.
21. The VGA of claim 20, wherein the source of the first transistor in each attenuator node is connected to at least one of the first set of resistors, which are coupled to the AC input, and the ground via a second resistor, the drain of the first transistor is coupled to the input of the amplifier.
22. The VGA of claim 20, where the RC circuitry of an attenuator node comprises:
- a first RC branch coupling the gate and the source of the first transistor of the attenuator node and having a third resistor and a first capacitor, the third resistor is coupled to the gate of the first transistor and serially connected to the first capacitor, which is connected to the source of the first transistor;
- a second RC branch coupling the gate and drain of the first transistor of the attenuator node and having a fourth resistor and a second capacitor, the fourth resistor is coupled to the gate of the first transistor and serially connected to the second capacitor, which is connected to the input of the amplifier; and
- a fifth resistor which passes the first (DC) control signal to the gate of the first transistor of the attenuator node.
23. The VGA of claim 20, wherein the gate clamping circuitry comprises a second transistor and a sixth resistor, where a source of the second transistor is coupled to the gate of the first transistor via the sixth resistor, a drain of the second transistor is connected to the ground, and the gate of the second transistor is connected to the second control signal.
24. The VGA of claim 20, wherein continuous gain control for the VGA is realized via a continuous two-step transition between every two adjacent attenuator nodes along the attenuator ladder, where in each two-step transition, only two adjacent attenuator nodes are activated via the first control signals supplied to the two attenuator nodes, respectively, and at least one of the two activated attenuator nodes is on during each two-step transition period.
25. The VGA of claim 24, wherein the second control signal supplied to a gate clamping circuitry corresponding to an attenuator node turns on the second transistor to prevent leak from the corresponding attenuator node when the corresponding attenuator node is not active or not adjacent to an active attenuator node.
26. A differential variable-gain amplifier (DVGA), comprising:
- a first set of attenuator nodes serially connected via a first set of resistors between adjacent first set of attenuator nodes to form a first attenuator ladder and coupled to a first AC input of the DVGA,
- a first amplifier having a first output produced based on an input of the first amplifier connected to a first plurality of coupled terminals, each of which is respectively from one of the first set of attenuator nodes,
- a second set of attenuator nodes serially connected via a second set of resistors between adjacent second set of attenuator nodes to form a second attenuator ladder and coupled to a second AC input of the DVGA,
- a second amplifier having a second output produced based on an input of the second amplifier connected to a second plurality of coupled terminals, each of which is respectively from one of the second set of attenuator nodes, wherein
- each of the first and second sets of attenuator nodes comprises a transistor and an RC circuitry that couples a drain, a gate, and a source terminals of the transistor to a control signal for the attenuator node, and
- the RC circuitry for each attenuator node is configured to pass a control signal to the gate terminal of the transistor of the attenuator node in accordance with a first time scale and permit the gate terminal to float in accordance with a second time scale so as to yield a reduction of distortion contributed by the transistor while the transistor is transitioning between on and off states.
27. The VGA of claim 26, wherein the source of the transistor in each of the first set of attenuator node is connected to at least one of the first set of resistors, which are coupled to the first AC input, and a ground via a third resistor, the drain of the transistor in each of the first set of attenuator nodes is coupled to the input of the first amplifier.
28. The VGA of claim 27, wherein the source of the transistor in each of the second set of attenuator node is connected to at least one of the second set of resistors, which are coupled to the second AC input, and the ground via a fourth resistor, the drain of the transistor in each of the second set of attenuator nodes is coupled to the input of the second amplifier.
Type: Application
Filed: Nov 24, 2008
Publication Date: May 27, 2010
Inventor: Walter Andrew Striflier (Sunnyvale, CA)
Application Number: 12/276,552
International Classification: H03G 7/06 (20060101);