METHOD, APPARATUS, AND SYSTEM FOR PROTECTING SUPPLY NODES FROM ELECTROSTATIC DISCHARGE
Described herein are a method, apparatus, and system for electrostatic discharge protection of supplies. The apparatus comprises a timer unit having a node with a first supply signal and operable to generate a first timer signal based on the first supply signal; and a clamp unit, coupled to the timer unit and having a node with a second supply signal, operable to clamp the second supply signal in response to electrostatic discharge (ESD) on the node with the second supply signal for a duration based on a signal level of the first timer signal.
Embodiments of the invention relate generally to the field of processors. More particularly, embodiments of the invention relate to a method, an apparatus, and a system for protecting power and/or ground supply nodes from electrostatic discharge (ESD) to enable a fast ramp of supply signal on those nodes.
BACKGROUNDDuring manufacturing of integrated circuits (ICs) or during handling of such ICs, the power or ground supply nodes/pins to the ICs may experience a high supply voltage and current (e.g., several thousand volts and currents of several amperes, positive and/or negative with respect to a local ground). These high supply voltages and currents signify an electrostatic discharge (ESD) event on the nodes, and may damage the circuits coupled to the power and/or ground nodes/pins of the ICs. The power and/or ground supply nodes/pins may also experience an ESD event indirectly when other circuits coupled to the power and/or ground supply nodes/pins experience an ESD event. In such a case, the ESD on the other circuits flows through electrical paths to the power and/or ground supply nodes/pins thus causing damage to those nodes/pins and to circuits coupled to those nodes/pins. To protect these circuits, ESD protection circuits are included in the ICs to short the power supply and ground supply nodes of the IC to one another in case of an ESD event on such supply nodes.
Such ESD protection circuits protect the ICs by clamping the high or low voltage signals on the supply nodes (power supply and ground nodes). Consequently, a rapidly changing voltage (e.g., 10 mV/μS or faster) on a supply node of the IC may appear as an ESD event to the ESD protection circuit which responds to the ESD event by shorting the nodes having the supplies (power supply and ground supply) to one another to discharge the large currents (several amperes) associated with the ESD event. By discharging the large currents associated with the ESD event, buildup of high voltages on circuit nodes of the ICs is prevented.
However, for efficient power management of ICs, advanced power generators are used that generate supply signals with fast ramp speeds (e.g., 1-10K mV/μS). These fast ramping supply signals allow the ICs to go in and out of power states to save power consumption and to improve IC performance. These fast ramping supply signals appear to an ESD protection circuit (such as the ESD protection circuit 100 of
Embodiments of the invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
Embodiments of the invention relate to a method and an apparatus for protecting power and/or ground supply nodes from electrostatic discharge (ESD) to enable fast ramp of supply signal on those nodes.
In one embodiment, an ESD protection circuit of an integrated circuit (IC) is configured so that its timer unit is decoupled from the ESD circuits' clamp unit. Details of the embodiment are discussed below with reference to
The term ramp refers herein to the up and/or down slope of the supply signals. In one embodiment, the clamp unit of the ESD protection circuit is operable to clamp a second supply signal in case of an ESD event on the node having the second supply signal. In such an embodiment, the clamp unit is operable to clamp the second supply signal for the duration of the first timer signal.
The term decouple refers herein to electrically separating the source of the ground and/or supply signals of the timer unit and the clamp unit from one another. For example, the supply signal provided to the clamp unit may be generated by an internal (e.g., on-die) voltage generator may use the first supply signal, where the first supply signal is generated by an external (e.g., off-die) voltage generator.
The above embodiment allows the second supply signal to have a faster ramp speed (e.g., 1-10K mV/μS or faster) compared to a ramp speed of the first supply signal (e.g., 1 mV/μS) without prompting the ESD protection circuit to clamp the second supply signal even with the second supply signals' much faster ramp speed. One reason for the capability of faster ramp speed for the second supply signal without clamping the second supply signal is that the first timer signal from the timer unit, which determines when to clamp the second supply signal, is based on the first supply signal.
The above embodiment thus allows the clamp unit to distinguish between an ESD event (a voltage spike on the node with the second supply signal) and a fast ramping second supply signal. Such an embodiment allows efficient power management of the IC by powering up and down the components of the IC in a fast manner (e.g., 1-10K mV/μS vs. 1 mV/μS) without causing the clamp device of the ESD circuit to turn on and thus clamp the second supply signal. The embodiments discussed herein also reduce leakage power consumption in the clamp devices of the clamp unit, which are large transistors compared to typical logic transistors, by shutting off the decoupled second power supply (supply to the clamp unit) during a power down mode of the IC.
In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present invention.
Note that in the corresponding drawings of the embodiments signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction any may be implemented with any suitable type of signal scheme, e.g., differential pair, single-ended, etc.
So as not to obscure the embodiments of the invention, the structure of the first voltage generator is not shown. In one embodiment, the first voltage generator is an off-die voltage regulator residing on a motherboard away from the IC. In another embodiment, the first voltage generator is an on-die voltage regulator operable to generate the first supply signal at a slow ramp speed (e.g., 1 mV/μS).
In one embodiment, the clamp unit 202 is operable to receive the timer signal 203 and to generate a buffered timer signal 203 to drive a clamp device (not shown) of the clamp unit 202. As mentioned above, the clamp unit 202 is decoupled from the timer unit 201 so that the clamp unit 202 operates on a different supply (power and/or ground) than the supply (power and/or ground) of the timer unit 201. In one embodiment, the clamp unit 202 has a node with a second supply signal Vdd2 which has a faster ramp speed (e.g., 1-10K mV/μS) compared to the ramp speed of the first supply signal Vdd1 (e.g., 1 mV/μS) of the timer unit 201.
In one embodiment, the node with the second supply signal Vdd2 is exposed to conditions external to the IC via C4 bumps of the IC die which are coupled to bond wires and/or die package. In such an embodiment, the node with the second supply signal Vdd2 is exposed to an ESD event. In one embodiment, the node with the second supply signal Vdd2 provides the supply signal to input-output (I/O) transceivers of the IC, wherein the I/O transceivers and thus the node with the second supply signal are exposed to ESD through the I/O transceivers from the I/O pins. The embodiments described herein discuss ESD protection for the node with the second supply signal Vdd2.
In one embodiment, the clamp device in the clamp unit 202 is an NMOS transistor operable to short the node with the second supply to a node with a ground signal in response to an ESD event on the node with the ground signal. In another embodiment, the clamp device in the clamp unit 202 is a PMOS transistor operable to short the node with the second supply to a node with a ground signal in response to an ESD event on the node with the second supply signal. In one embodiment, the clamp device in the clamp unit 202 is a PMOS transistor operable to short the node with the second supply to a node with a ground signal in response to an ESD event on the node with the ground supply signal. In one embodiment, the clamp device in the clamp unit 202 is an NMOS transistor operable to short the node with the second supply to a node with a ground signal in response to an ESD event on the node with the second supply signal.
So as not to obscure the embodiments, the following embodiments are discussed with reference to the clamp device being a PMOS transistor and the ESD event being on the node with the second supply signal when the IC is unpowered i.e., when the first and the second supply signals are at logical zero levels. While the clamp device is discussed with regards to clamping the second supply signal Vdd2, the same design can be used to clamp an ESD on the ground supply signal gnd2 via an NMOS transistor without changing the essence of the embodiments of the invention.
One purpose of the feedback unit 301 is to provide stability to the timer unit 201 by keeping the timer signal 203 at a stable level and not allowing the level of the timer signal 203 to discharge via any electrical leakage or coupling paths in the IC. By keeping the timer signal 203 at a stable level and not allowing it to discharge via leakage or coupling paths, the clamp unit 202 does not clamp the node with the second supply signal Vdd2 to the node with the ground signal in response to a discharged timer signal 203. In one embodiment, in response to an ESD event on the node with the second supply signal Vdd2, the feedback unit 301 is disabled because the timer signal remains discharged. As mentioned above, the IC is in a power down state during an ESD event and so the nodes with the first and the second supply nodes are at logical zero levels just before an ESD event.
In one embodiment the feedback unit 301 comprises a keeper device Mfb operable to be driven by an inverter which is further operable to invert the timer signal 203 to generate a feedback signal fb. In one embodiment, the timer unit 201 is operable to receive the first supply signal Vdd1.
In one embodiment, the clamp unit 202 is operable to receive the timer signal 203. In one embodiment, the clamp unit 202 comprises a buffer and a clamp device M1. In such an embodiment, the buffer is operable to generate a gatedrv signal from the timer signal 203 to drive the clamp device M1. In one embodiment, the clamp device is a PMOS transistor operable to short a node with the second supply signal Vdd2 to a node with a ground signal. As mentioned with reference to the embodiment of
As discussed later with reference to the embodiment of
Referring back to
In the top half of
The term track refers herein to the behavior of a first signal such that the ramp speed of the first signal is the same as the ramp speed of a second signal.
As the timer signal ramps up by tracking the first supply signal Vdd1, the feedback signal fb keeps the keeper device Mfb turned on. As the second supply signal Vdd2 ramps up, gatedrv signal tracks the second supply signal Vdd2. The logical level of the timer signal 203 ensures that the gatedrv signal to the clamp device M1 is such that the clamp device M1 is off when there is no ESD event on either the nodes with the first supply signal or the second supply signal.
As shown in the bottom half of
A logical zero level of the timer signal 203 means that the feedback signal fb keeps the keeper device Mfb turned off. However, the logical zero level of the timer signal 203 results in turning on the clamp device M1, thus causing the node with the second supply signal Vdd2 to short to the node with the ground supply signal. The shorting of the two nodes discharges the ESD on the node with the second supply signal Vdd2. The small ripple effect on the first supply signal is caused by an electrical path between the node with the first supply signal and the node with the second supply signal on which an ESD event occurred. As discussed above, the ESD protection circuit of the embodiments will function properly even if there was no electrical path between the node with the first supply signal and the node with the second supply signal on which an ESD event occurred.
While the embodiments of
In response to an ESD event on the node with the second supply signal Vdd2, the timer signal remains at a logical zero level causing the clamp device to turn on and clamp the second supply signal Vdd2. As mentioned above, the IC is in a power down state during an ESD event and so the nodes with the first and the second supply signals (Vdd1 and Vdd2, respectively) are at logical zero levels just before an ESD event. Compared to the embodiment of
At block 501, the first supply signal Vdd1 is generated before generating the second supply signal Vdd2. At block 502, a first timer signal 203 is generated via a timer unit 201, wherein the first timer signal 203 is based on the first supply signal Vdd1. At block 503, the second supply signal Vdd2 is clamped by the clamp unit 202 in response to an ESD on the node with the second supply signal Vdd2, wherein the clamping process lasts for a duration based on the timer signal 203.
In one embodiment, the ESD protection circuit 605 is operable to receive a second supply signal 606 from an internal voltage regulator 604. In one embodiment, the internal voltage regulator 604 is operable to receive the first supply signal 602 and generate the second supply signal 606. In other embodiments, the second supply signal 606 is generated by a power gate transistor (not shown) that is operable to receive the first supply signal 602 on one terminal of the power gate transistor and then operable to generate the second supply signal Vdd2 at the other terminal of the power gate transistor. In one embodiment, the power gate transistor is controlled by a power management signal at its gate terminal. In one embodiment, the internal voltage regulator 604 resides on the package of the processor 603. In one embodiment, the internal voltage regulator 604 is an on-die voltage regulator coupled to the ESD protection circuit 605, where both the internal voltage regulator 604 and the ESD protection circuit 605 reside within the processor 603.
Embodiments of the invention are also implemented via programmable computer-executable instructions 607. For example, in one embodiment, the size of the PMOS clamp transistor M1 of
Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
While the invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description.
In one embodiment, the output signal timerlv of the timer unit 701 is input to the level shifter 702. In one embodiment, the level shifter 702 is operable to generate a timerhv# signal from the timerlv signal. In one embodiment, the level shifter 702 is operable to keep the timerhv# signal at logical low level while the second supply signal Vdd2 is ramping up. In one embodiment, the level shifter 702 is operable to keep the timerhv# signal at a logical low level by using the first supply signal Vdd1 to power the pulldown device in the level shifter 702 via the timerlv signal. In such an embodiment, the timerhv# signal is a concave waveform shape that keeps the clamp devices off while the second supply signal ramps up.
In one embodiment, the output signals of the level shifter 701 (timerlv and timerhv#) are received by the clamp unit 703. In one embodiment, the clamp unit 703 is a stacked clamp unit compared to the clamp unit of
Referring to
The embodiments of the invention are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.
Claims
1. An apparatus comprising:
- a timer unit having a node with a first supply signal and operable to generate a first timer signal based on the first supply signal; and
- a clamp unit, coupled to the timer unit and having a node with a second supply signal, operable to clamp the second supply signal in response to electrostatic discharge (ESD), and operable to clamp for a duration based on a signal level of the first timer signal.
2. The apparatus of claim 1, wherein the timer unit is operable to generate the first timer signal with a time constant longer than the duration of an ESD event on the node with the second supply signal.
3. The apparatus of claim 1, wherein the first and the second supply signals correspond to a first power supply signal and a second power supply signal respectively.
4. The apparatus of claim 1, wherein the first and the second supply signals correspond to a first ground supply signal and a second ground supply signal respectively.
5. The apparatus of claim 1 further comprises:
- a first supply generator operable to generate the first supply signal; and
- a second supply generator operable to generate the second supply signal, wherein the first supply generator is operable to ramp the first supply signal at a ramp speed slower than a ramp speed of the second supply signal.
6. The apparatus of claim 5, wherein the first supply generator is operable to generate the first supply signal before the second supply generator generates the second supply signal, and wherein the second supply generator is operable to turn itself off before the first supply generator turns itself off.
7. The apparatus claim 1 further comprises a level shifter coupled to the timer unit and the clamp unit, wherein the clamp unit is operable to receive the second supply signal with a supply level higher than a supply level of the first supply signal, and wherein the level shifter is operable to generate a second timer signal for the clamp unit from the first timer signal, the second timer signal having a signal level to protect reliability of the clamp unit.
8. The apparatus of claim 1 further comprises a feedback unit coupled to the clamp unit or to the timer unit and operable to adjust the first timer signal in response to the first or the second supply signals being ramped up or down.
9. The apparatus of claim 1, wherein the clamp unit comprises a PMOS transistor between the node with the second supply signal and a node with a ground supply signal, wherein the second supply signal is a second power supply signal.
10. The apparatus of claim 1, wherein the clamp unit comprises an NMOS transistor between the node with the second supply signal and a node with a power supply signal, wherein the second supply signal is a ground power supply signal.
11. An system comprising:
- a first voltage generator operable to generate a first supply signal; and
- a processor coupled to the first voltage generator and comprising: a second voltage generator operable to generate a second supply signal; and an electrostatic discharge (ESD) unit operable to: generate a first timer signal via the first supply signal; and clamp the second supply signal in response to ESD, the clamping for a duration based on the first timer signal.
12. The system of claim 11, wherein the first supply generator is operable to ramp the first supply signal at a ramp speed slower than a ramp speed of the second supply signal.
13. The system of claim 11, wherein the first supply generator is operable to generate the first supply signal before the second supply generator generates the second supply signal, and wherein the second supply generator is operable to turn itself off before the first supply generator turns itself off.
14. The system of claim 11, wherein the ESD unit comprises:
- a timer unit having a node with the first supply signal and operable to generate the first timer signal based on the first supply signal; and
- a clamp unit, coupled to the timer unit and having a node with the second supply signal, operable to clamp the second supply signal.
15. The system of claim 14, wherein the clamp unit comprises a PMOS transistor between the node with the second supply signal and a node with a ground supply signal, wherein the second supply signal is a second power supply signal.
16. The system of claim 14, wherein the clamp unit comprises an NMOS transistor between the node with the second supply signal and a node with a power supply signal, wherein the second supply signal is a ground power supply signal.
17. The system of claim 14, wherein the ESD unit further comprises a feedback unit coupled to the clamp unit or to the timer unit and operable to adjust the first timer signal in response to the first or the second supply signals being ramped up or down.
18. The system claim 14, wherein the ESD unit further comprises a level shifter coupled to the timer unit and the clamp unit, wherein the clamp unit is operable to receive the second supply signal with a supply level higher than a supply level of the first supply signal, and wherein the level shifter is operable to generate a second timer signal for the clamp unit from the first timer signal, the second timer signal having a signal level to protect reliability of the clamp unit.
19. The system of claim 11, wherein the first voltage generator is an off-die voltage regulator operable to generate the first supply signal with a ramp speed slower than a ramp speed of the second supply signal.
20. The system of claim 11, wherein the second voltage generator is operable to generate the second supply signal with a ramp speed faster than a ramp speed of the first supply signal.
21. The system of claim 11, wherein the second voltage generator is operable to generate a gated version of the first supply signal as the second supply signal.
22. A method comprising:
- generating a first timer signal via a timer unit having a node with a first supply signal, the first timer signal being based on the first supply signal; and
- clamping a second supply signal in response to electrostatic discharge (ESD) on a node with the second supply signal for a duration based on the first timer signal.
23. The method of claim 22 further comprises ramping up or down the first and the second supply signals at different speeds with respect to one another.
24. The method of claim 22 further comprises providing a time constant for the first timer signal longer than the duration of an ESD event on the node with the second supply signal.
25. The method of claim 22 further comprises generating the first supply signal before generating the second supply signal.
26. The method of claim 22 further comprises generating the first supply signal with a ramp speed slower than a ramp speed of the second supply signal.
27. A processor comprising:
- a voltage generator to receive a first supply signal and to generate a second supply signal based on the first supply signal; and
- an electrostatic discharge (ESD) unit to: generate a first timer signal via the first supply signal; and clamp the second supply signal in response to ESD, the clamping for a duration based on the first timer signal.
28. The processor of claim 27, wherein the first supply signal is generated via a first supply generator which is operable to ramp the first supply signal at a ramp speed slower than a ramp speed of the second supply signal.
29. The processor of claim 27, wherein the ESD unit comprises:
- a timer unit having a node with the first supply signal and operable to generate the first timer signal based on the first supply signal; and
- a clamp unit, coupled to the timer unit and having a node with the second supply signal, operable to clamp the second supply signal.
30. The processor of claim 29, wherein the ESD unit further comprises a feedback unit coupled to the clamp unit or to the timer unit and operable to adjust the first timer signal in response to the first or the second supply signals being ramped up or down.
Type: Application
Filed: Jun 24, 2010
Publication Date: Dec 29, 2011
Patent Grant number: 8514533
Inventors: Christopher P. Mozak (Beaverton, OR), Victor Zia (Portland, OR)
Application Number: 12/822,901