Voltage Responsive Patents (Class 361/56)
  • Patent number: 11223097
    Abstract: A radiofrequency transmission line configured so as to allow a radiofrequency electrical signal to be transmitted between a first end and a second end, the transmission line including a main conductor and a ground plane electrically connected to an electrical ground of the transmission line. The ground plane includes a set of portions that are connected in series between the first end and the second end and a set of second capacitors, the set of portions including a set of second portions, each second capacitor being inserted between two contiguous second portions.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: January 11, 2022
    Assignee: Schneider Electric Industries SAS
    Inventors: Alejandro Niembro, Emmanuel Dreina
  • Patent number: 11223199
    Abstract: An over current protection system includes a first resistor, a second resistor, a third resistor, and an electrostatic discharge circuit. The first resistor includes a first terminal for receiving an input voltage, and a second terminal. The second resistor includes a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a ground terminal. The third resistor includes a first terminal, and a second terminal coupled to the first terminal of the second resistor. The electrostatic discharge circuit is coupled to the first terminal of the third resistor. When the input voltage is an abnormal voltage, the electrostatic discharge circuit is enabled for maintaining a voltage at the second terminal of the third resistor within a normal voltage range.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: January 11, 2022
    Assignee: BenQ Corporation
    Inventors: Hsin-Nan Lin, Chung-Yu Huang
  • Patent number: 11205359
    Abstract: An electrical level shifting chip and a display device are provided. The electrical level shifting chip includes an electrical level shifting module, an overcurrent protecting module, and a controlling module. The control module is configured to detect whether the electrical level shifting chip is in an electrostatic discharge test mode and to disable the overcurrent protecting module when the electrical level shifting chip is in the electrostatic discharge test mode. Avoid the overcurrent protecting module from being disturbed and causing malfunction during an electrostatic discharge test.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 21, 2021
    Inventors: Wenfang Li, Dan Cao
  • Patent number: 11205358
    Abstract: A test circuit for preventing an electrostatic discharge (ESD) device from electricity leakage and a display panel having the same are provided. The test circuit includes a switch module between the ESD device and the display panel to control an electrical connection between the ESD device and the display panel, and prevent the display panel from electricity leakage, so as to reduce power consumption.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: December 21, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Ronglei Dai
  • Patent number: 11195825
    Abstract: A semiconductor device arrangement and a method of operating a semiconductor device arrangement. The semiconductor device can be arranged for bidirectional operation. The semiconductor device arrangement can comprise: a field effect transistor comprising first and second input terminals; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to respective signal lines.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: December 7, 2021
    Assignee: Nexperia B.V.
    Inventors: Hans-Martin Ritter, Andreas Zimmerman
  • Patent number: 11183491
    Abstract: A high-frequency module includes a mounting substrate, electronic components, a sealing resin, and land conductors. The mounting substrate includes a front surface, a rear surface, and a side surface. The land conductors are provided on the rear surface. The electronic components are mounted on the front surface of the mounting substrate. A distance between the mounting surface of the land conductor near the side surface and the rear surface of the mounting substrate is larger than a distance between the mounting surface of the land conductor closer to the center than the land conductor near the side surface and the rear surface of the mounting substrate.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takanori Uejima
  • Patent number: 11184000
    Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Sualp Aras, Abidur Rahman
  • Patent number: 11177251
    Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Callaghan Taft, Tobias Hoehn, Karim Thomas Taghizadeh Kaschani
  • Patent number: 11171132
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Souvick Mitra, Alain F. Loiseau, Robert J. Gauthier, Jr., You Li, Tsung-Che Tsai
  • Patent number: 11171794
    Abstract: Systems and methods are provided for 8-channel surge protection for a network utilizing Power Over Ethernet (PoE). Four Bob Smith terminations are arranged such that one Bob Smith termination is coupled to each of four PoE nodes. Each Bob Smith termination includes a capacitor and a resistor pair coupled in series between its respective PoE node and a respective Bob Smith termination node, wherein a first pair of the Bob Smith terminations is connected between their respective PoE nodes and a first Bob Smith node and a second pair of the Bob Smith terminations is connected between their respective PoE nodes and a second Bob Smith node. The first Bob Smith node is capacitively isolated from ground via a first terminating capacitor component and a second Bob Smith node is capacitively isolated from ground via a second terminating capacitor component separate from the first terminating capacitor component.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kah Hoe Ng, Tzye Perng Poh, Khai Chiah Chng
  • Patent number: 11159014
    Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 26, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Adrien Benoit Ille, Claudia Kupfer, Gernot Langguth
  • Patent number: 11158626
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Hee Jeong Son, Ki Ryong Jung, Seung Yeop Lee
  • Patent number: 11152783
    Abstract: A circuit for protecting against electrostatic discharges includes two avalanche circuit components having different turn-on delays with respect to a beginning of an electrostatic discharge. The two avalanche circuit components are coupled in parallel. The avalanche circuit component closer to an output node has a turn-on delay on the order of 30 ns, while the avalanche circuit component closer to an input node has a turn-on delay on the order of 1 ns.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Mathieu Rouviere
  • Patent number: 11146060
    Abstract: An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N?1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N?1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: October 12, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Cheng Hsu, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 11138316
    Abstract: An apparatus of a computing system, a computer-readable medium, a method and a system. The apparatus comprises an input/output interface and one or more processors connected to the input/output interface and adapted to perform a first reading of first fuse data stored in a fuse array storage circuitry to result in read first fuse data, and receive the read first fuse data from the fuse array storage circuitry through the input/output interface; after a random time-delay, perform a second reading of second fuse data stored in the fuse array storage circuitry to result in read second fuse data, and receive the read second fuse data from the fuse array storage circuitry through the input/output interface; and compare the read first fuse data with the read second fuse data, and if there is no match, halt a boot-up of the computing system.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventor: Vui Yong Liew
  • Patent number: 11139812
    Abstract: A gate driver system includes a gate driver having a first input for receiving a digital input signal, a second input for receiving a short circuit protection signal, and output for driving a power device; a current reconstruction circuit having a first input for receiving a voltage across an inductance associated with the power device, a second input for receiving a current associated with the power device, a third input for receiving the digital input signal, and an output for providing a sensed power device current; and a comparator having a first input coupled to the output of the current reconstruction circuit, a second input coupled to a reference, and an output coupled to the second input of the gate driver.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 5, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Asantha Kempitiya
  • Patent number: 11133670
    Abstract: An air gap metal tip structure is provided for (ESD) protection. The structure includes first and second metal tips disposed along at least one horizontal axis that is parallel to a upper substrate and a lower substrate. The structure includes an air chamber formed between the upper and lower substrate within which the first metal tip and the second metal tip are disposed. The air chamber includes a portion between points of the metal tips. The structure includes an under fill level disposed between the lower and upper substrates, and above one or more layers having the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the metal tips to maintain the ESD protection for subsequent arcs.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qianwen Chen, Yang Liu, Dongbing Shao, Zheng Xu
  • Patent number: 11107637
    Abstract: A variable capacitance element is provided that includes a plurality of resistance elements that form a path for applying a control voltage to the electrodes of a plurality of variable capacitance portions connected in series. These resistance elements include first distribution resistance elements, second distribution resistance elements, a first shared resistance element, and a second shared resistance element. Moreover, vertical sectional areas of the first shared resistance element and the second shared resistance element with respect to conducting directions thereof are larger than the vertical sectional areas of the first distribution resistance elements and the second distribution resistance elements with respect to conducting directions thereof.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 31, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takaaki Mizuno
  • Patent number: 11094688
    Abstract: The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 17, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Steven J. Tanghe, Kevin R. Wrenner, Michael Amato
  • Patent number: 11088536
    Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 10, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas Demange
  • Patent number: 11088529
    Abstract: A device for acquiring signals from a sensor, the device comprising a differential amplifier, two bias resistors for biasing of the measurement device, a common mode and differential mode filter circuit, and two lightning limiter components. The differential amplifier is of the high common mode range type, the limiter components are dimensioned to reduce a lightning voltage to a maximum voltage value of the order of about one hundred volts and the filter circuit and the bias resistors are dimensioned to withstand that maximum voltage value. A correspond method for protecting a device against lightning.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 10, 2021
    Assignee: Safran Electronics & Defense
    Inventors: Olivier Meline, Mathieu Le-Meunier
  • Patent number: 11088541
    Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 10, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Jia-Rong Yeh, Yeh-Ning Jou, Hsien-Feng Liao, Yi-Han Wu, Chih-Cherng Liao, Chieh-Yao Chuang, Wei-Shung Chen, Ching-Wen Chen, Pang-Chuan Chen
  • Patent number: 11088719
    Abstract: A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiong Liu, Hiep Pham
  • Patent number: 11061054
    Abstract: Provided is a current measuring device for measuring current, including a conductor adapted to pass current therethrough, a circuit board with a wire, the wire being adapted to extract a voltage signal from the conductor, a cover member adapted to house the circuit board, first fixing means provided on the cover member, and second fixing means fixed in combination with the first fixing means, in which the conductor is mounted between the first fixing means and the second fixing means.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 13, 2021
    Assignee: KOA CORPORATION
    Inventor: Tamotsu Endo
  • Patent number: 11054451
    Abstract: An electrostatic discharge measuring device includes an integrated circuit including a collector, a discharge pad and an ESD detector circuit coupled to the collector and discharge pad. The ESD detector circuit includes a device that detects occurrence and magnitude of an electrostatic discharge between the collector and the discharge pad. In one embodiment, the device is a metal-oxide-semiconductor capacitor. In another embodiment, the device is a thin film storage bitcell. In one embodiment, the electrostatic discharge measuring device is contained in a test microelectronic package. A method includes running the test microelectronic package through a manufacturing process to determine location during manufacturing at which an electrostatic discharge occurs when an externally-similar production microelectronic packages is run through the same manufacturing process.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 6, 2021
    Assignee: NXP USA, Inc.
    Inventors: Matthew Clay Lauderdale, Robert Scott Ruth, Emmanuel U. Onyegam
  • Patent number: 11056880
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiv Harit Mathur, Nitin Gupta
  • Patent number: 11050142
    Abstract: A coupled antenna apparatus particularly well adapted for small form factor, metal encased applications that utilize satellite wireless links, e.g. GPS. Certain examples use electromagnetic feeding that includes one or more separate feed elements that are not galvanically connected to a radiator element of the antenna. Additionally, one radiator element of the antenna can be located on an outermost surface of a bezel of an electronic device, for example a wrist-wearable device. A resonating circuit is housed within an electronic device and electrically coupled to such an outer radiator element.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 29, 2021
    Assignee: Suunto Oy
    Inventors: Heikki Puuri, Erik Lindman
  • Patent number: 11024624
    Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 1, 2021
    Assignees: Arm Limited, The Regents of the University of Michigan
    Inventors: Parameshwarappa Anand Kumar Savanth, Fabrice Blanc, David Theodore Blaauw, Sechang Oh, In Hee Lee
  • Patent number: 11025054
    Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 1, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Yun-Jen Ting, Chih-Wei Lai, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 11011907
    Abstract: According to one aspect, a power device is provided. The power device includes an input having at least a first connection and a second connection, and configured to be coupled to an AC power source to receive input AC power, a converter circuit coupled to the input and configured to convert an input AC voltage to a DC voltage, a load output configured to provide output power derived from the DC voltage, a rectifier circuit coupled to the input and having a first output and a second output, and a first capacitor coupled to the first output of the rectifier circuit and the second output of the rectifier circuit.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 18, 2021
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Jonas Sonsby Mouridsen, Carsten Nommensen Tingskov
  • Patent number: 10998717
    Abstract: The present disclosure relates to a power distribution unit (PDU) having at least one power receptacle for enabling attachment of an AC power cord of an external device thereto. A branch receptacle controller (BRC) has at least one bistable relay and is associated with the one power receptacle for supplying AC power thereto from an AC power source. The BRC monitors a voltage of an external power source and uses it to detect when AC power is lost, and then toggles the bistable relay, if the relay is in a closed position, to an open position.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 4, 2021
    Assignee: Vertiv Corporation
    Inventor: Kevin R. Ferguson
  • Patent number: 10988096
    Abstract: A protective device for a trip circuit for a personal protection device for a vehicle, the trip circuit having an ignition device, a high-side end stage, and a low-side end stage. The protective device has a high-side interface for contacting the protective device to a high-side terminal and a low-side interface for contacting the protective device to a low-side terminal of the ignition device, a suppressor diode that is connected between the high-side interface and a second voltage potential; and at least one first diode that is connected between the low-side interface and the second voltage potential.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 27, 2021
    Assignee: Robert Bosch GmbH
    Inventor: Hartmut Schumacher
  • Patent number: 10992207
    Abstract: A power tool has a housing, a motor disposed within the housing, a power supply circuit for providing power to the motor, a controller circuit for controlling the power provided to the motor, and an electric static discharge (ESD) protection circuit connected to the power supply circuit and the housing. The ESD protection circuit includes a first resistor connected to the power supply circuit and the housing. The first resistor may be a high impedance resistor. The ESD protection circuit may also have a first capacitor connected in parallel to the first resistor, a second resistor connected in series to the first resistor, and a second capacitor connected in series to the first capacitor and in parallel to the second resistor.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 27, 2021
    Assignee: BLACK & DECKER INC.
    Inventors: Scott J. Eshleman, Shailesh P. Waikar, Ganapati K. Pai, Joseph Narbut
  • Patent number: 10978444
    Abstract: A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 13, 2021
    Assignee: NXP B.V.
    Inventor: Gijs Jan de Raad
  • Patent number: 10978441
    Abstract: Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 13, 2021
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Dengping Yin, Shijun Wang, Fei Yao
  • Patent number: 10971925
    Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventors: Frederic Lebon, Laurent Chevalier
  • Patent number: 10972087
    Abstract: An apparatus and method for controlling voltage sharing between a set of switching components can include applying power from a current source with a positive lead and a negative lead, closing the set of switching components to connect power from the current source to an electrical load, detecting a set of voltage values for the set of switching components, and controlling a current limiting function of at least one of the set of switching components.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 6, 2021
    Assignee: GE Aviation Systems Limited
    Inventors: Peter James Handy, Peter Michael Tyler
  • Patent number: 10971929
    Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 6, 2021
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Yan Wang, Tao Liu, Guang-Bing Chen, Yu-Xin Wang, Dong-Bing Fu, Yu-Jun Yang, Liang Chen, Yang Pu
  • Patent number: 10971488
    Abstract: A circuit includes electrostatic discharge (ESD) protection circuitry, triggering circuitry, transient detection circuitry, and deactivation circuitry. The ESD protection circuitry is coupled between a first rail and a second rail. The triggering circuitry is configured to generate an ESD activation signal when a voltage across the first rail and the second rail exceeds a voltage threshold. The ESD protection circuitry is configured to activate based on the ESD activation signal. The transient detection circuitry is configured to generate a deactivation signal when the voltage across the first rail and the second rail comprises a voltage change over time that is less than a transient threshold. The deactivation circuitry is configured to deactivate the triggering circuitry based on the deactivation signal.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Glaser, Thorsten Hinderer
  • Patent number: 10964651
    Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chou Tseng, Tzu-Heng Chang
  • Patent number: 10958263
    Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 23, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Toshimichi Yamada, Tatsuro Shinmitsu, Kazuhiko Okawa, Hiroaki Nitta, Masahiro Hayashi
  • Patent number: 10951023
    Abstract: A variable level power clamping circuit that may be used for the bypass path of an RF receiver having a low-noise amplifier (LNA). Impedance transform circuitry is used to transform the impedance of a signal path to a higher or lower impedance at a clamping circuit, causing the voltage at the clamping circuit to be, respectively, higher (thus clamping at a lower power level) or lower (thus clamping at a higher power level), and then transform the impedance after the clamping circuit to another value, such as to the impedance of the signal path. In a variant embodiment, the clamping circuit and an impedance matching element coupled to an LNA amplification path are re-purposed by selectively connecting those circuit elements to the LNA bypass path through a suitable impedance transform element when in a bypass mode.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 16, 2021
    Assignee: pSemi Corporation
    Inventor: Jonathan James Klaren
  • Patent number: 10944256
    Abstract: Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Horaira Abu, Linda K. Sun
  • Patent number: 10944255
    Abstract: A multi-channel transient voltage suppressor with ultra-low capacitance is provided, which comprises a plurality of diode strings coupled between an ESD bus line and ground, having each diode string coupled to an I/O pin; a power clamp circuit coupled to the ESD bus line; and a first diode having an anode coupled to the power clamp circuit and a cathode coupled to ground. A second diode may be alternatively disposed between the first diode and the diode strings, having an anode coupled to the ground and a cathode coupled to a common anode of the diode strings. By employing the proposed present invention, it is advantageous of reaching an ultra-low capacitance and meanwhile still maintaining a lower layout area of the circuit structure.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 9, 2021
    Assignee: Amazing Microelectronic Corp.
    Inventor: Yiming Tseng
  • Patent number: 10938354
    Abstract: An amplification device includes an amplification circuit and a protection circuit. The amplification circuit includes a transistor having a first terminal for outputting an amplified radio frequency signal, a second terminal, and a control terminal coupled to the input terminal of the amplification circuit for receiving a radio frequency signal to be amplified. The protection circuit has a first terminal coupled to the output terminal or the input terminal of the amplification circuit, and a second terminal. The protection circuit includes a switch and a first voltage clamping unit. The switch unit is turned on or turned off according to a control signal. The first voltage clamping unit is coupled to the switch unit for clamping a voltage at the first terminal of the protection circuit within a predetermined region when the switch unit is turned on.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 2, 2021
    Assignee: RichWave Technology Corp.
    Inventors: Jhao-Yi Lin, Chih-Sheng Chen, Ching-Wen Hsu
  • Patent number: 10938203
    Abstract: One example discloses a voltage limiting device, including: a first I/O port; a second I/O port; a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit; wherein the voltage limiter includes a first portion and a second portion; wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 2, 2021
    Assignee: NXP B.V.
    Inventors: Anu Mathew, Guido Wouter Willem Quax
  • Patent number: 10928951
    Abstract: A touch panel includes two ground wires. One end portion (an end portion X1) of one of the two ground wires and one end portion (an end portion Y1) of the other of the two ground wires form a gap. When the touch panel is viewed from front, the following condition as an example is satisfied: a line segment Z1 intersects at least one of the two ground wires. The line segment Z1 is a line segment which connects any one point P1 on a first line segment and any one point Q1 on a second line segment, the first line segment connecting a site of the end portion X1 and a site of the end portion Y1 which are located on two sides of an outer gate of the gap, the second line segment connecting a site of the end portion X1 and a site of the end portion Y1.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 23, 2021
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Akitoshi Sakaue, Hiroshi Okumura
  • Patent number: 10928424
    Abstract: A shunt resistor having sufficient bonding strength includes a resistor, a pair of bases which are integrally formed with the resistor so as to sandwich the resistor, recessed holes which are respectively formed in the bases, and measurement terminals which are inserted into the recessed holes and are affixed to the bases. Each measurement terminal has a shaft part and a flange part that protrudes outwardly in the circumferential direction of the shaft part. Each recessed hole is formed to have a diameter smaller than the diameter of the flange part, and the shaft parts are respectively inserted into the recessed holes.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 23, 2021
    Inventor: Kenji Murakami
  • Patent number: 10930644
    Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 23, 2021
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Eric Braun
  • Patent number: 10930639
    Abstract: An ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors each for providing two detection signals. The ESD protection circuit includes driver circuitry that produces trigger signals to clamp circuits that make conductive the clamp circuits in response to an ESD event based on the detection signals from the current mirrors.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 23, 2021
    Assignee: NXP USA, INC.
    Inventors: Kuo-Hsuan Meng, James W. Miller