Abstract: A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.

Abstract: The present disclosure provides a display panel static electricity protection device (400), static electricity protection method, and a display device (100), including a detection sub-circuit (401), a detection sub-circuit (401), a discharge circuit (402) connected with the driving chip (301), a current driving sub-circuit (403) connected with the detection sub-circuit (401), the discharge circuit (402), and a discharge terminal (404), and the discharge terminal (404) connected with a grounding wire of the driving circuit board. The detection sub-circuit (401) detects static electricity, the current driving sub-circuit (403) inputs and detects current in the detection sub-circuit (401) to open or close the discharge circuit (402). The static electricity is discharged to the discharge terminal (404) through the discharge circuit (402) and the current driving sub-circuit (403).

Abstract: A biometric skin contact sensor comprising an array of sensor pixels, wherein each sensor pixel comprises: a capacitive sensing electrode for accumulating a charge in response to proximity of a conductive object to be sensed; a reference capacitor connected to the capacitive sensing electrode; a sense voltage-controlled impedance, VCI, having a control terminal connected to a connection between the capacitive sensing electrode and the reference capacitor, the sense VCI having an impedance controlled by its control terminal voltage, and wherein the pixel is arranged so that, in response to a select voltage being applied to the pixel, the control terminal voltage of the sense VCI indicates the proximity of the conductive object to be sensed; and biasing circuitry comprising a one-way conduction path from a bias voltage connection to the control terminal of the sense VCI so that current flows from the bias voltage towards the control terminal of the sense VCI in response to the control terminal voltage of the se

Abstract: A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.

Abstract: A clamping circuit for protection against ESD events is described. In accordance with one exemplary embodiment, the circuit comprises the following: a first transistor having a control terminal and a load current path connected between a first contact and a second contact; an amplifier circuit having an amplifier input and an amplifier output connected to the control terminal of the transistor; and a trigger circuit, which is connected between the first contact and the second contact, and comprises a second transistor. The trigger circuit is configured to generate a voltage swing at the amplifier input as a reaction to a discharge current at the first contact by virtue of the fact that at least part of the discharge current drives a control terminal of the second transistor via an intrinsic capacitance of the second transistor.

Abstract: A surge protection circuit is presented. The surge protection circuit includes an input port for receiving an input voltage; an energy release cell having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switch device and to the ground via a second switch device. The surge protection circuit is adapted to close the first switch device to enable a current to flow from the input port to ground through the release cell upon occurrence of a positive voltage surge and to close the second switch device to enable a current to flow from ground to the input port through the release cell upon occurrence of a negative voltage surge.

Abstract: A display panel includes an electrostatic protection circuit including a first protection circuit electrically connected between a first signal line and a second signal line. The first protection circuit includes a first transistor connected between the first signal line and the second signal line and including a gate electrode and a lower gate electrode, a first resistor connected between the gate electrode of the first transistor and the second signal line, a first capacitor connected between the gate electrode of the first transistor and the second signal line, and a second capacitor connected between the lower gate electrode of the first transistor and the second signal line. The lower gate electrode of the first transistor receives a reference voltage.

Abstract: Embodiments provide an electrostatic discharge (ESD) protection circuit and an electrostatic discharge method. The ESD protection circuit includes: a pulse detection unit (100), a discharge transistor (300), a feedback delay unit (200), and a processing unit (400). A first terminal of the pulse detection unit (100) is connected to a first pad (101), a second terminal of the pulse detection unit (100) is connected to a second pad (102), and an output terminal of the pulse detection unit (100) is configured to output a detection result signal. A gate of the discharge transistor (300) is connected to the output terminal of the pulse detection unit (100), a drain of the discharge transistor (300) is connected to the first pad (101), and a source of the discharge transistor (300) is connected to the second pad (102). The feedback delay unit (200) includes a PMOS transistor (Mp) and an NMOS transistor (Mn).

Abstract: A display device includes a display panel including a plurality of pixels, a first panel pad, and a second panel pad and a circuit board including a first substrate pad and a second substrate pad to apply a first power voltage to the first panel pad and the second panel. The display panel further includes a first power line pattern connected to the second substrate pad to apply the first power voltage to the pixels and a second power line pattern connected to the first substrate pad. The circuit board includes a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad, a substrate power pattern electrically connected to the first substrate pad, a ground pattern receiving a ground voltage, and a second electrostatic discharge protection circuit connected between the substrate power pattern and the ground pattern.

Abstract: In one example, a circuit comprises: a controller, an electrostatic discharge (ESD) circuit, and a driver circuit. The controller has a driver control output. The ESD circuit has a driver control input and an ESD output, the driver control input coupled to the driver control output. The driver circuit has a driver input and a driver output, the driver input coupled to the ESD output.

Abstract: A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.

Abstract: In certain aspects, a clamp includes first and second transistors coupled in series between a power bus and a ground. The clamp also includes a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus. The clamp further includes a capacitive voltage divider configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage.

Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.

Abstract: Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. The power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. There may be both a pull-up third diode in the diode string for connection between I/O and VDD and a pull-down third diode between I/O and VSS. During an ESD event the ESD device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. During operational mode the ESD device is turned off and does not interfere with circuit operations.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An ESD protection apparatus includes a discharge resistor and a transistor connected in series between a first voltage rail and a second voltage rail, a first coupling capacitor, a diode and a first bias resistor connected in series between the first voltage rail and the second voltage rail, wherein a common node of the diode and the first bias resistor is connected to a gate of the transistor, and an ESD protection device connected between the first voltage rail and the second voltage rail.

Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry may be implemented as an integrated circuit and comprises driver circuitry configured to supply a drive signal to the piezoelectric transducer to cause the transducer to generate an output signal and active inductor circuitry configured to be coupled with the piezoelectric transducer. The active inductor circuitry may be tuneable to adjust a frequency characteristic of the output signal.

Abstract: The present invention discloses parallel, series and hybrid ESD protection circuits. A preferred parallel ESD protection circuit comprises a plurality of ESD devices connected in parallel, with each comprising a resistor and an OTS component connected in series. A preferred series ESD protection circuit comprises a plurality of ESD devices connected in series, wherein the OTS components in all ESD devices are disposed on a same level. A preferred hybrid ESD protections circuit comprises ESD devices connected in parallel, as well as in series.

Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.

Abstract: An electrostatic discharge (ESD) protection circuit is provided, which includes multiple ESD clamping circuits and a shunt circuit. The multiple clamping circuits comprise multiple transistors, respectively. The multiple transistors are coupled in series between a first power line and a second power line. A shunt circuit is coupled with a first terminal and a control terminal of a first transistor of the multiple transistors. The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor. The shunt circuit insulates the first terminal of the first transistor from the control terminal of the first transistor during a period outside the period of the ESD event.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a first node, a second diode circuit connected between the second output terminal and the first node, a first intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at a second node different from the first node, a first intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, a detection circuit configured to generate a trigger signal in accordance with the first intermediate voltage, and a switch circuit configured to electrically connect the first node to a ground line in accordance with the trigger signal.

Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.

Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Abstract: An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.

Abstract: The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.

Abstract: A display panel includes pads and pixels, signal lines electrically connected to the pads, and a protection circuit electrically connected between one signal line among the signal lines and a first voltage line. The protection circuit includes a first transistor, a first resistor, and a first capacitor. The first transistor includes a first electrode electrically connected to the first voltage line, a second electrode electrically connected to the one signal line, and a gate electrode. The first resistor is electrically connected between the gate electrode of the first transistor and the one signal line. The first capacitor is disposed between the gate electrode of the first transistor and the one signal line.

Abstract: An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.

Abstract: Provided is a display substrate. The display substrate includes: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data transmission lines, a plurality of electrostatic discharge circuits, a panel crack detection trace, and a plurality of electrostatic discharge dummy circuits. At least one of the electrostatic discharge dummy circuits may be connected to the panel crack detection trace. A display device is also provided.

Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).

Abstract: An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.

Abstract: A device includes a protected terminal, a reference terminal, and a rate-triggered circuit coupled to the protected terminal and to the reference terminal. The rate-triggered circuit is configured to provide an output voltage responsive to a ramp rate of a voltage at the protected terminal being greater than a rate threshold. The device also includes a transistor configured to shunt current from the protected terminal to the reference terminal responsive to the rate-triggered circuit output voltage, and a level-sensing circuit configured to turn off the transistor responsive to the voltage at the protected terminal being greater than a level-sense threshold.

Abstract: An actuating device for a motor vehicle brake may include an actuating device/brake pedal, a pressure supply device driven by an electric motor, a (master) piston-cylinder unit that may be actuated by the actuating device, and which is connected hydraulically with a fluid reservoir, a valve assembly for wheel-specifically adjusting brake pressures and for connecting or disconnecting the wheel brakes to/from the pressure supply device and the piston-cylinder unit, an electronic control unit, and one or more sensor devices that may be used to provide sense various conditions and to provide inputs to the electronic control unit.

Abstract: The present application relates to electrostatic protection circuit, integrated circuit and electrostatic discharge method.

Abstract: Embodiments relate to an electrostatic discharge (ESD) protection circuit and a chip. The ESD protection circuit includes: an ESD protection module, arranged inside a protected chip and connected to a protected circuit; and a control module, connected to the ESD protection module and configured to output a low-level signal to the ESD protection module to trigger the ESD protection module to discharge an electrostatic current when an ESD event occurs in the protected chip, and output a high-level signal to the ESD protection module to reduce a static leakage current of the ESD protection module when the ESD event does not occur in the protected chip.

Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.

Abstract: An integrated circuit includes a signal pad, receiving an input signal during a normal mode, and receive an ESD signal during an ESD mode; an internal circuit, processing the input signal during the normal mode; a variable impedance circuit, comprising a first end coupled to the signal pad, a second end coupled to the internal circuit, wherein the variable impedance circuit provides a low or high impedance path between the signal pad and the internal circuit during the normal or ESD mode; and a switch circuit, comprising a first end coupled to a control end of the variable impedance circuit, a second end coupled to a reference voltage terminal, and a control end receiving a node voltage, wherein the switch circuit switches the control end of the variable impedance circuit to have a first specific voltage or be electrically floating during the normal or ESD mode.

Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.

Abstract: The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.

Abstract: A method and system for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels of networked devices. Single-channel multimode surge suppressing systems are combined to form multi-port multimode protection systems that connect directly to multiport networked devices supporting communication channels with mixed signals data and direct current power in Gigabit Ethernet networks supporting PoE. The surge suppressing systems mitigate differential and common mode induced interference and protect from overvoltage surges associated with E1, E2, and E3 components of the HEMP and mitigate the over-voltages to predetermined allowable levels within the predetermined time.

Abstract: A gate driver integrated circuit includes a high-side region that operates in a first voltage domain according to a first pair of supply terminals that include a first lower supply terminal and a first higher supply terminal; a low-side region that operates in a second voltage domain according to a second pair of supply terminals; at least one termination region that electrically isolates the high-side region from the low-side region; a first electrostatic device arranged in the high-side region and connected to the first pair of supply terminals; a second electrostatic device arranged in the low-side region and connected to the second pair of supply terminals; and a third electrostatic device connected to a lower supply terminal of the first pair of supply terminals and is coupled in series with the first electrostatic device.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.