Abstract: A phase coherent synthesizer with good phase noise and spurious performance is described. The phase coherent synthesizer includes digital direct synthesizer (DDS) circuitry, frequency multiplier circuitry, an oscillator, and a mixing stage. The digital direct synthesizer (DDS) circuitry has a first output and a second output. The first output is associated with a fine resolution synthesis. The second output is associated with a step synthesis. A second output signal provided via the second output has a higher frequency compared with a first output signal provided via the first output. The frequency multiplier circuitry is connected with the second output. The frequency multiplier circuitry is configured to multiply the second output signal received via the second output, thereby generating a multiplied output signal. The mixing stage has two input ports connected with the frequency multiplier circuitry and the oscillator respectively.

Abstract: The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Abstract: A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.

Abstract: A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.

Abstract: An asymmetric surge protection device for a DC circuit (16) has a negative side (32) which can be connected to a current output (28) of the DC circuit (16), a positive side (30) which can be connected to a current input (26) of the DC circuit (16), and an asymmetric neutral section (34). The asymmetric neutral section (34) has a positive protection level (Vp) for a positive voltage (V) between the positive side (30) and the negative side (32), and a negative protection level (Vn) for a negative voltage (V) between the positive side (30) and the negative side (32), the positive protection level (Vp) being different from the negative protection level (Vn). Furthermore, a DC circuit arrangement (14) and a DC network (10) are shown.

Abstract: A display device which includes a display panel and a protection member above the display panel. The protection member may include an adhesive layer above the display panel, a first protection layer above the adhesive layer, and a second protection layer between the first protection layer and the adhesive layer. The first protection layer may have a first thickness and a first modulus, and the second protection layer may have a second thickness less than the first thickness and a second modulus less than the first modulus. The minimum value of the second thickness may be 20 ?m, and the maximum value of the second thickness may satisfy T2max=(0.13×T1?8.25)×ln M2+0.68×T1?5.

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 ?m.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Abstract: Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

Abstract: An electrostatic protection circuit, a power management chip, and a display terminal are provided. The electrostatic protection circuit includes a level shift unit and a power management unit. The electrostatic protection circuit also includes a clamping module. An input terminal of the clamping module receives an electrostatic detection signal. An output terminal of the clamp module outputs a fault detection signal. The output terminal of the clamp module continues to output a high electrical potential when the electrostatic detection signal transits from a low electrical potential to the high electrical potential until the power management unit stops operating.

Abstract: A grounding system includes a first circuit portion and a second circuit portion. The first circuit portion is connected to an input voltage bus and has a terminal being a first ground. The second circuit portion is connected between the first ground and a second ground, and includes a switch branch and a resistor branch. When the positive terminal of a power supply is connected to the input voltage bus and the negative terminal of the power supply is connected to the second ground, the switch branch establishes a first current path between the first ground and the second ground and shorts a first diode in the switch branch. When the positive terminal is connected to the second ground and the negative terminal is connected to the input voltage bus, the switch branch disconnects the first current path and stops shorting the first diode.

Abstract: A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

Abstract: A transient voltage protection device includes: an element body; a cavity portion provided in the element body; a pair of internal electrodes disposed in the element body; and a pair of external electrodes connected to the pair of internal electrodes. The pair of internal electrodes extend along a first direction and face each other in a second direction intersecting the first direction. The cavity portion includes a gap region located between the pair of internal electrodes in the second direction. A tip portion of at least one of the pair of internal electrodes is in contact with only the element body.

Abstract: A bridge converter converts an input voltage into an output voltage, and includes a switching circuit, a transformer, a rectifying circuit, and a control module. The switching circuit includes a first switch and a second switch. The control module sets a first time period and a second time period. The control module provides a first control signal and a second control signal to control the switching circuit based on the output voltage. The control module fixes an operation frequency of the first control signal and the second control signal at the maximum frequency based on that the control module is set in a standby mode, and provides the first control signal and the second control signal in the first time period, and shields the first control signal and the second control signal in the second time period.

Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

Abstract: A transient voltage suppressing device includes a plurality of fingers arranged laterally along a major surface of an epitaxial layer. The plurality of fingers includes fingers of a first type and fingers of a second type. The first type and second type of fingers each include a silicon controlled rectifier (SCR) region and a junction diode region. The plurality of fingers of the second type are conductively coupled together by a second metal layer disposed over top a first metal layer and electrically insulated from the first metal layer. The first metal layer conductively couples the SCR region and junction diode region of the first type of finger.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Abstract: In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.

Abstract: A method for wafer-level adjustment of protection circuits of electronic devices and a wafer for facilitating the same are provided. The method comprises: fabricating an adjustable terminal protection circuit for each of the electronic devices in the wafer; and adjusting each of the adjustable terminal protection circuits by cutting off one or more fuse elements in the one or more trimming circuits of the terminal protection circuit. The method provides a cost-effective approach to allow wafer-level on-chip adjustment of protection circuits for III-V compound devices in a flexible manner so as to address the issues of manufacturing process constrains under requirement of large wafer dimension.

Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.

Abstract: A double IO pad cell including a busing frame formed on a busing metal layer aligned with a same-sized component frame integrated on a component layer of an IC. The busing frame includes first and second IO pads, a supply voltage rail, and a ground voltage rail. The component frame includes first and second primary ESD circuitry each including a first diode coupled between a respective one of the first and second IO pads and the supply voltage rail and a second diode coupled between the respective IO pad and the ground voltage rail. The second diodes of each primary ESD circuitry are integrated adjacent each other sandwiched between the first diodes which act as collector guard bands for the second diodes. The diodes of each primary ESD circuitry of the component frame are aligned with a corresponding one of the first and second IO pads of the busing frame.

Abstract: A transient voltage protection device includes: an element body; a cavity portion provided in the element body; a pair of internal electrodes disposed in the element body; and a pair of external electrodes connected to the pair of internal electrodes. The pair of internal electrodes extend along a first direction and face each other in a second direction intersecting the first direction. The cavity portion includes a gap region located between the pair of internal electrodes in the second direction. A tip portion of at least one of the pair of internal electrodes is in contact with only the element body.

Abstract: A power electronic device includes an input which is connected to an over-current-protection device arrangement and a DC-link, wherein the DC-link includes a series connection of at least two DC-link capacitors. In such a power electronic device the risk of a fire hazard should be minimized. To this end fault detecting element(s) are provided detecting an imbalance between the DC-link capacitors or an overload of at least one of the DC-link capacitors, wherein the fault detecting element(s) control maximum current inducing element(s) connected to the DC-link.

Abstract: A protective circuit against electrostatic discharges for connection pins of an application-specific integrated circuit. The protective circuit includes a first connection pin and a second connection pin, and the first connection pin and the second connection pin being connected to one another in a Y configuration. Moreover, an application-specific integrated circuit including a protective circuit of this type is provided.

Abstract: A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.

Abstract: The present disclosure provides a display panel static electricity protection device (400), static electricity protection method, and a display device (100), including a detection sub-circuit (401), a detection sub-circuit (401), a discharge circuit (402) connected with the driving chip (301), a current driving sub-circuit (403) connected with the detection sub-circuit (401), the discharge circuit (402), and a discharge terminal (404), and the discharge terminal (404) connected with a grounding wire of the driving circuit board. The detection sub-circuit (401) detects static electricity, the current driving sub-circuit (403) inputs and detects current in the detection sub-circuit (401) to open or close the discharge circuit (402). The static electricity is discharged to the discharge terminal (404) through the discharge circuit (402) and the current driving sub-circuit (403).

Abstract: A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.

Abstract: A biometric skin contact sensor comprising an array of sensor pixels, wherein each sensor pixel comprises: a capacitive sensing electrode for accumulating a charge in response to proximity of a conductive object to be sensed; a reference capacitor connected to the capacitive sensing electrode; a sense voltage-controlled impedance, VCI, having a control terminal connected to a connection between the capacitive sensing electrode and the reference capacitor, the sense VCI having an impedance controlled by its control terminal voltage, and wherein the pixel is arranged so that, in response to a select voltage being applied to the pixel, the control terminal voltage of the sense VCI indicates the proximity of the conductive object to be sensed; and biasing circuitry comprising a one-way conduction path from a bias voltage connection to the control terminal of the sense VCI so that current flows from the bias voltage towards the control terminal of the sense VCI in response to the control terminal voltage of the se

Abstract: A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.

Abstract: A clamping circuit for protection against ESD events is described. In accordance with one exemplary embodiment, the circuit comprises the following: a first transistor having a control terminal and a load current path connected between a first contact and a second contact; an amplifier circuit having an amplifier input and an amplifier output connected to the control terminal of the transistor; and a trigger circuit, which is connected between the first contact and the second contact, and comprises a second transistor. The trigger circuit is configured to generate a voltage swing at the amplifier input as a reaction to a discharge current at the first contact by virtue of the fact that at least part of the discharge current drives a control terminal of the second transistor via an intrinsic capacitance of the second transistor.

Abstract: A display panel includes an electrostatic protection circuit including a first protection circuit electrically connected between a first signal line and a second signal line. The first protection circuit includes a first transistor connected between the first signal line and the second signal line and including a gate electrode and a lower gate electrode, a first resistor connected between the gate electrode of the first transistor and the second signal line, a first capacitor connected between the gate electrode of the first transistor and the second signal line, and a second capacitor connected between the lower gate electrode of the first transistor and the second signal line. The lower gate electrode of the first transistor receives a reference voltage.

Abstract: A surge protection circuit is presented. The surge protection circuit includes an input port for receiving an input voltage; an energy release cell having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switch device and to the ground via a second switch device. The surge protection circuit is adapted to close the first switch device to enable a current to flow from the input port to ground through the release cell upon occurrence of a positive voltage surge and to close the second switch device to enable a current to flow from ground to the input port through the release cell upon occurrence of a negative voltage surge.

Abstract: Embodiments provide an electrostatic discharge (ESD) protection circuit and an electrostatic discharge method. The ESD protection circuit includes: a pulse detection unit (100), a discharge transistor (300), a feedback delay unit (200), and a processing unit (400). A first terminal of the pulse detection unit (100) is connected to a first pad (101), a second terminal of the pulse detection unit (100) is connected to a second pad (102), and an output terminal of the pulse detection unit (100) is configured to output a detection result signal. A gate of the discharge transistor (300) is connected to the output terminal of the pulse detection unit (100), a drain of the discharge transistor (300) is connected to the first pad (101), and a source of the discharge transistor (300) is connected to the second pad (102). The feedback delay unit (200) includes a PMOS transistor (Mp) and an NMOS transistor (Mn).

Abstract: A display device includes a display panel including a plurality of pixels, a first panel pad, and a second panel pad and a circuit board including a first substrate pad and a second substrate pad to apply a first power voltage to the first panel pad and the second panel. The display panel further includes a first power line pattern connected to the second substrate pad to apply the first power voltage to the pixels and a second power line pattern connected to the first substrate pad. The circuit board includes a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad, a substrate power pattern electrically connected to the first substrate pad, a ground pattern receiving a ground voltage, and a second electrostatic discharge protection circuit connected between the substrate power pattern and the ground pattern.

Abstract: In one example, a circuit comprises: a controller, an electrostatic discharge (ESD) circuit, and a driver circuit. The controller has a driver control output. The ESD circuit has a driver control input and an ESD output, the driver control input coupled to the driver control output. The driver circuit has a driver input and a driver output, the driver input coupled to the ESD output.

Abstract: A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.

Abstract: In certain aspects, a clamp includes first and second transistors coupled in series between a power bus and a ground. The clamp also includes a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus. The clamp further includes a capacitive voltage divider configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage.

Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. The power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. There may be both a pull-up third diode in the diode string for connection between I/O and VDD and a pull-down third diode between I/O and VSS. During an ESD event the ESD device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. During operational mode the ESD device is turned off and does not interfere with circuit operations.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An ESD protection apparatus includes a discharge resistor and a transistor connected in series between a first voltage rail and a second voltage rail, a first coupling capacitor, a diode and a first bias resistor connected in series between the first voltage rail and the second voltage rail, wherein a common node of the diode and the first bias resistor is connected to a gate of the transistor, and an ESD protection device connected between the first voltage rail and the second voltage rail.

Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry may be implemented as an integrated circuit and comprises driver circuitry configured to supply a drive signal to the piezoelectric transducer to cause the transducer to generate an output signal and active inductor circuitry configured to be coupled with the piezoelectric transducer. The active inductor circuitry may be tuneable to adjust a frequency characteristic of the output signal.

Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.

Abstract: The present invention discloses parallel, series and hybrid ESD protection circuits. A preferred parallel ESD protection circuit comprises a plurality of ESD devices connected in parallel, with each comprising a resistor and an OTS component connected in series. A preferred series ESD protection circuit comprises a plurality of ESD devices connected in series, wherein the OTS components in all ESD devices are disposed on a same level. A preferred hybrid ESD protections circuit comprises ESD devices connected in parallel, as well as in series.