Voltage Responsive Patents (Class 361/56)
  • Patent number: 11569657
    Abstract: The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to first and second power bonding pads and detects whether an ESD event or an EOS event occurs at the first power bonding pad. The detection circuit controls a detection voltage on a detection node according to a detection result. The first and second power bonding pads belong to different power domains. The discharge circuit is coupled to the detection node and the first power pad. In response to the ESD event occurring at the first power bonding pad, the discharge circuit provides a discharge path between the first power bonding pad and a ground terminal according to the detection voltage. In response to the EOS event occurring at the first power bonding pad, the detection circuit activates a second discharge path between the first power bonding pad and the ground terminal.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 31, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Ching-Ho Li, Hsien-Feng Liao, Chieh-Yao Chuang, Yeh-Ning Jou
  • Patent number: 11552072
    Abstract: A symmetrical layout technique for an electrostatic discharge ESD device and a corresponding power supply network is presented. The ESD device protects an electronic circuit against an overvoltage or overcurrent and contains a first contact area to establish an electrical contact with a first supply rail, a second contact area to establish an electrical contact with a second supply rail, and a third contact area to establish an electrical contact with a third supply rail. The first and third supply rails provide a first supply voltage, and the second supply rail provides a second supply voltage. Within the ESD device, an axis of symmetry passes through the second contact area, and the first contact area and the third contact area are arranged on opposite sides with regard to the axis of symmetry. The symmetrical layout technique allows flipping the orientation of the ESD device with regard to the supply rails.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: January 10, 2023
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Marcus Peitz
  • Patent number: 11552470
    Abstract: An electrostatic discharge circuit includes six transistors. A power supply voltage node is coupled with a gate and a drain of a first transistor and connected to a source of a second transistor and a drain of a fifth transistor. A source of the first transistor is coupled to a ground voltage node and connected to a gate of a third transistor and a gate of a fourth transistor. A gate of the second transistor is connected to the drain of the first transistor. A source of the third transistor is connected to the drain of the second transistor and a gate of the fifth transistor. A drain of the fourth transistor is connected to a drain of the third transistor. A source of the fourth transistor and a source of the sixth transistor are connected to the ground voltage node.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: January 10, 2023
    Assignees: Semiconductor Manufacturing International (ShenZhen) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jue Wang
  • Patent number: 11539207
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiv Harit Mathur, Nitin Gupta
  • Patent number: 11532616
    Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 20, 2022
    Assignee: STMICROELECTRONICS (TOURS)
    Inventor: Aurelie Arnaud
  • Patent number: 11527528
    Abstract: An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 13, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jie Zeng, Raunak Kumar
  • Patent number: 11527884
    Abstract: A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 13, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan Lin, Shao-Chang Huang, Yeh-Ning Jou, Hwa-Chyi Chiou, Ching-Ho Li
  • Patent number: 11521962
    Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: December 6, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: David Michael Rogers, Eric N. Mann, Eric Lee Swindlehurst, Toru Miyamae, Timothy John Williams, Ryuta Nagai, Sungkwon Lee, Ravindra M. Kapre, Mimi Xuefeng Zhao Qian, Yan Yi, Dung Si Ho, Boo Chin-Hua
  • Patent number: 11523528
    Abstract: A flexible electrical system distribution, switching, and protection solution having two or more autonomous electrical switching devices and optionally adding circuit protection and manual switching in one self-contained device. A printed circuit board assembly is configured to operate two or more electrical switch functions to act from a remote signal input or autonomously, independently or simultaneously. The printed circuit board can be assembled into a housing where multiple independent circuits on the printed circuit board assembly can be permanently electrically connected to each other through electrical conductors thus reducing the number of independent circuits within the assembly. The assembly further consists of an electrically isolative housing and terminal studs and retaining nuts capable to receiving electrical cable ring terminals.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: December 6, 2022
    Inventor: Eric Graham
  • Patent number: 11522360
    Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: December 6, 2022
    Assignee: STMicroelectronics (Alps) SAS
    Inventors: Frederic Lebon, Laurent Chevalier
  • Patent number: 11515301
    Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 29, 2022
    Assignees: STMicroelectronics (Tours) SAS, STMicroelectronics S.r.l.
    Inventors: Aurelie Arnaud, Andrea Brischetto
  • Patent number: 11509133
    Abstract: A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal. The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 22, 2022
    Assignee: AMAZING MICROELECTRONIC CORP.
    Inventors: Chih-Ting Yeh, Sung-Chih Huang, Che-Hao Chuang
  • Patent number: 11502510
    Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: November 15, 2022
    Inventor: Chao-Cheng Lu
  • Patent number: 11495535
    Abstract: A system and method for detecting and measuring electrostatic discharge during semiconductor assembly are described. A semiconductor device fabrication process forms a conductor between two metal routes in a series path on a semiconductor die. The series path is between a bump on the die and a substrate tie. The two metal routes have a width greater than a threshold based on a metal width capable of conducting a critical current density caused by an electrostatic discharge event without conductive failure or breakdown. The conductor has a width less than the threshold. When an electrostatic discharge event occurs, if the current exceeds a critical amount of current, the conductor experiences conductive breakdown and current ceases to flow. During later testing, this series path is tested for open connections, which indicate whether the conductor acting as an electrical on-die fuse experienced conductive failure during assembly of a semiconductor chip.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 8, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gladney Asada, Regina Tien Schmidt
  • Patent number: 11482858
    Abstract: In general, according to one embodiment, a protection circuit includes first and second power lines, first and second controllers, a first transistor, and a detector. The first controller includes a first resistor element, a capacitor, first, second, and third inverters. The second controller includes third transistor. One end of the third transistor is coupled to the second power line. The other end of the third transistor is coupled to each of the output end of the first inverter and the input end of the second inverter.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 25, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kentaro Watanabe
  • Patent number: 11475940
    Abstract: Apparatuses for providing pads included in external terminals of a semiconductor device are described. An example apparatus includes a memory cell array, a data queue (DQ) circuit, a data pad and a power pad. The memory cell array may include one or more memory cells. In a write operation, the data pad receives write data and provides the write data to the DQ circuit. The DQ circuit receives the write data and provides the write data to the memory cell array. In a read operation, the DQ circuit receives read data from the memory cell array and provides the read data. The data pad receives the read data from the DQ circuit and provides the read data. The power pad provides a power supply voltage. The data pad and the power pad are disposed across from each other with respect to the DQ circuit.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Toshinao Ishii
  • Patent number: 11444453
    Abstract: An ESD protection circuit is provided. An embodiment provides an ESD protection circuit of a crystal oscillator for bearing an output swing level in an ESD IO for improving a reference clock isolation by adding a stacked diode to the ESD protection circuit and for improving a protection function by applying a secondary diode structure.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 13, 2022
    Assignee: Dialog Semiconductor Korea Inc.
    Inventor: Je Cheol Moon
  • Patent number: 11437708
    Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Patent number: 11424615
    Abstract: An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 23, 2022
    Assignee: NXP USA, Inc.
    Inventors: Kuo-Hsuan Meng, Gayathri Bhagavatheeswaran, Hector Sanchez
  • Patent number: 11418172
    Abstract: A two-terminal electrical protective device operates by harvesting energy from a small but non-zero voltage drop across a closed solid-state switch. From a default, open-circuit state, the device is remotely triggered by an AC signal to enter the desired conductive state. Power scavenged by an energy harvesting circuit while the device is in the conductive state, powers a gate drive circuit to hold the device in the conductive state for as long as current flows. When current stops, the device returns to the default open-circuit state.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 16, 2022
    Assignee: Generac Power Systems, Inc.
    Inventor: Joshua Daniel Kaufman
  • Patent number: 11411394
    Abstract: A voltage clamping circuit for protecting an internal circuitry comprising an input means for receiving Vin; a p-channel clamping transistor (PCT) coupled to input means for clamping Vin to prevent Vin from falling below a p-channel biasing voltage VbiasP; an n-channel clamping transistor (NCT) coupled to input means for clamping Vin to prevent Vin from rising above an n-channel biasing voltage VbiasN; and a plurality of output means for providing a first output voltage from PCT and a second output voltage from NCT; a p-channel bias circuit including a first, a second and a third bias transistor with each transistor possessing a threshold voltage Vth for providing a p-channel bias voltage to turn on PCT; and an n-channel bias circuit including a fourth, a fifth and a sixth bias transistor with each transistor possessing the threshold voltage Vth for providing an n-channel bias voltage to turn on NCT.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 9, 2022
    Assignee: SKYECHIP SDN BHD
    Inventor: Hoong Chin Ng
  • Patent number: 11411496
    Abstract: A power regulator includes an input capacitor connected between a first voltage bus and an intermediate point, an output capacitor connected between a second voltage bus and the intermediate point, a plurality of switches and an inductor connected between the input capacitor and the output capacitor, wherein a source of one switch of the plurality of switches is connected to the intermediate point and a protection device connected between the intermediate point and a third voltage bus.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: August 9, 2022
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Hengchun Mao, Yan-Fei Liu, Renhua Wu
  • Patent number: 11404409
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fu Tsai, Tzu-Heng Chang, Yu-Ti Su, Kai-Ping Huang
  • Patent number: 11398469
    Abstract: Examples described herein generally relate to devices that include electrostatic discharge (ESD) protection in a chip stack. In an example, a device includes a chip stack including first and second chips, ground and power supply voltage nodes, and first and second resistor-capacitor (RC) clamps. The second chip is disposed on and attached to the first chip. The ground and power supply voltage nodes are connected between and extend in the first and second chips, and are connected to the ground and power supply voltage exterior connector pads, respectively, of the first chip. The first and second RC clamps are disposed in the first and second chips, respectively. The first and second RC clamps are connected to and between the ground node and the power supply voltage node. An RC-time constant of the second RC clamp is less than an RC-time constant of the first RC clamp.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 26, 2022
    Assignee: XILINX, INC.
    Inventor: James Karp
  • Patent number: 11394378
    Abstract: An integrated circuit comprises a power switch comprising a current path and a current sense node; and a temperature sense circuit internally coupled between the current path and the current sense node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 19, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Tomas Manuel Reiter, Georg Schinner, Frank Wolter
  • Patent number: 11387647
    Abstract: Methods and apparatuses for protecting a low voltage (LV) circuit implemented with LV transistors are presented. Protection is provided via a protection circuit operating in a high voltage domain defined by a varying supply voltage and a reference ground. The protection circuit generates high side, VH, and low side, VL, voltages to the LV circuit, while protecting the LV circuits from high voltage and maintaining a minimum difference voltage, VH?VL. The protection circuit generates the difference voltage based on a voltage across a resistor of a resistor ladder that is coupled between the varying supply voltage and the reference ground. The protection circuit includes a clamp circuit that limits the minimum difference voltage for low values of the supply voltage.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 12, 2022
    Assignee: PSEMI CORPORATION
    Inventor: Carlos Zamarreno Ramos
  • Patent number: 11387354
    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Louise De Conti
  • Patent number: 11387830
    Abstract: A semiconductor memory device has an output driving circuit. The output driving circuit includes a pull-down driver and a gate control logic. The pull-down driver includes first and second transistors. The first and second transistors are coupled between a pad and a ground node. The gate control logic includes third and fourth transistors. The third and fourth transistors are coupled between a pad and a first supply voltage node. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage. The first transistor is controlled by the feedback voltage. The second and third transistors are controlled by the first supply voltage. The fourth transistor is controlled by the voltage of the pad.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 11387648
    Abstract: High voltage tolerant electrical overstress protection with low leakage current and low capacitance is provided. In one embodiment, a semiconductor die includes a signal pad, an internal circuit electrically connected to the signal pad, a power clamp electrically connected to an isolated node, and one or more isolation blocking voltage devices electrically connected between the signal pad and the isolated node. The one or more isolation blocking voltage devices are operable to isolate the signal pad from a capacitance of the power clamp. In another embodiment, a semiconductor die includes a signal pad, a ground pad, a high voltage/high speed internal circuit electrically connected to the signal pad, and a first thyristor and a second thyristor between the signal pad and the ground pad.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 12, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Javier A. Salcedo, Srivatsan Parthasarathy, Enrique C. Bosch
  • Patent number: 11380676
    Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Joong-Ho Kim, Hyun Woo Kwack, Ki Jong Lee, Doo Bock Lee
  • Patent number: 11380672
    Abstract: A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: July 5, 2022
    Assignee: Semtech Corporation
    Inventors: David J. Rose, William A. Russell, Jonathan Clark
  • Patent number: 11368016
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: June 21, 2022
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11355926
    Abstract: A test device is disclosed. The test device includes an input/output (I/O) circuit configured to allow static electricity flowing between an input/output (I/O) pad and an internal circuit to be discharged to a power-supply line, a ground line, or a substrate line, a capacitor circuit configured to perform modeling of parasitic capacitance extracted from a package design, and a discharge circuit configured to allow capacitance stored in the capacitor circuit to be discharged to the substrate line.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Woo Kim, Chang Hwi Lee, Man Ho Seung
  • Patent number: 11355490
    Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: June 7, 2022
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Chun-Cheng Chen, Wen-Tai Wang
  • Patent number: 11348882
    Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Johanna M. Swan, Adel A. Elsherbini, Veronica Aleman Strong
  • Patent number: 11349304
    Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: May 31, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Alain F. Loiseau, Robert J. Gauthier, Jr., Souvick Mitra, You Li, Meng Miao, Wei Liang
  • Patent number: 11319805
    Abstract: Systems and methods are presented for reducing electrical interference in measurement-while-drilling (“MWD”) data. An example may include, among other features a MWD data acquisition system including an analog data reception for receiving analog MWD data, an analog-to-digital conversion circuit, at least one isolation circuit for electrically isolating the analog data reception circuit and the analog-to-digital conversion circuit from a digital data transmission circuit. In some embodiments, a power isolation circuit may electrically isolate an analog section power domain from a digital section power domain. The isolation techniques may improve the quality of the analog signal received.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 3, 2022
    Assignees: Erdos Miller, Inc., Black Diamond Oilfield Rentals, LLC
    Inventors: David Erdos, Ken Miller, Nathan Szanto
  • Patent number: 11322933
    Abstract: A protection circuit, comprising: a transient suppression circuit, configured to suppress a transient voltage; and a short-circuit protection circuit connected between the transient suppression circuit and a ground terminal, wherein when the transient suppression circuit is shorted out and the transient voltage is a protection voltage, the short-circuit protection circuit disconnects a loop where the transient suppression circuit is located. The short-circuit protection circuit has a turned-on state and a turned-off state; the short-circuit protection circuit is in a turned-on state when the transient suppression circuit is shorted out and the transient voltage is greater than the protection voltage; and the short-circuit protection circuit is in a turned-off state when the transient suppression circuit is shorted out and the transient voltage is a protection voltage.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 3, 2022
    Assignees: CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventor: Wenqin Zhao
  • Patent number: 11311225
    Abstract: A system for monitoring medical conditions includes a conformable medical monitoring device that includes a first substrate layer, which includes an electronics module, many signal traces, and at least one electrode, such that one or more of the many signal traces electrically couple the at least one electrode to the electronics module. The conformable medical monitoring device includes a second substrate layer positioned over the electronics module, the first substrate layer, or any combination thereof to insulate the electronics module, the first substrate layer, or any combination thereof. The conformable medical monitoring device also includes a third substrate layer positioned over the second substrate layer, such that the third substrate layer reduces electromagnetic interference caused by a voltage pulse and includes an adjustable system coupled to the first substrate layer and that changes a position of the at least one electrode relative to the electronics module.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: April 26, 2022
    Assignee: General Electric Company
    Inventors: Azar Alizadeh, Andrew A. Burns, Matthew Jeremiah Misner, Ralf Lenigk, Jeffrey Michael Ashe, Obi Aghogho, Nancy Cecelia Stoffel, Juha Virtanen, Otto Pekander, Timo Toivanen, Robert Santala
  • Patent number: 11306748
    Abstract: A controller for a valve assembly that is configured to meet requirements for use in hazardous areas. These configurations may regulate flow of instrument air to a pneumatic actuator to operate a valve. The controller may comprise enclosures, including a first enclosure and a second enclosure, each having a peripheral wall forming an interior space, and circuitry comprising a barrier circuit disposed in the interior space of one of the enclosures that power limits digital signals that exits that enclosure. In one example, the peripheral wall of enclosures are configured to allow instrument air into the interior space of the first enclosure but to prevent instrument air from the interior space of the second enclosure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 19, 2022
    Assignee: Dresser, LLC
    Inventors: Jonathan Fredric Cohen, Jagadish Gattu, Lei Lu, Anatoly Podpaly, Harold Randall Smart, Paul Talmage Tirrell
  • Patent number: 11309479
    Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, Bruce B. Doris, Matthias Georg Gottwald, Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11307235
    Abstract: An embodiment of the invention provides an apparatus for detecting electrostatic discharges (ESD) events, comprising: an ESD detector configured to determine at least one process window that will permit the ESD detector to detect an ESD event; at least one antenna coupled to said ESD detector; and said ESD detector calibrated for at least one discharge energy. Another embodiment of the invention provides: a method for detecting electrostatic discharges (ESD) events, comprising: determining at least one process window that will permit an ESD detector to detect an ESD event; and calibrating the ESD detector for at least one discharge energy.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 19, 2022
    Assignee: Illinois Tool Works Inc.
    Inventors: Lyle D. Nelsen, Steven B. Heymann, Mark E. Hogsett
  • Patent number: 11303117
    Abstract: An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Chang Gung University
    Inventor: Liann-Be Chang
  • Patent number: 11303469
    Abstract: A sensor 1 is arranged to read data transmitted on a digital vehicle network. The sensor comprises a wire holding unit 3, and a sensing unit 5. The wire holding unit and sensing unit are connectable to one another, the sensor further comprising a locking mechanism to lock the wire holding unit and the sensing unit together, when the wire holding unit and sensing unit are connected to one another.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 12, 2022
    Assignee: Bridgestone Mobility Solutions B.V.
    Inventors: Henrik Schiller, Thomas Hagenau, Andre Pomsel, Karsten Fischer, Steffen Kurzke
  • Patent number: 11296500
    Abstract: The present invention provides an output circuit with electrostatic discharge (ESD) protection in a semiconductor chip of a source driver. The source driver is configured to drive a display panel. The output circuit includes an output buffer, an output pad, a switch and a first resistor. The switch is coupled between the output buffer and the output pad, wherein data voltages for driving the display panel are transmitted from the output buffer to the output pad via the switch. The switch includes a first metal oxide semiconductor (MOS) transistor, which includes a first terminal coupled to the output pad, a bulk terminal and a gate terminal. The first resistor is coupled between the bulk terminal of the first MOS transistor and a first power supply terminal.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 5, 2022
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jhih-Siou Cheng, Ju-Lin Huang, Chia-En Wu
  • Patent number: 11296501
    Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 5, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alan Erik Segervall, Ross Anthony Pimentel, Sumantra Seth
  • Patent number: 11296503
    Abstract: An electrostatic discharge protection (ESD) circuit is provided for a semiconductor element. The semiconductor element includes first and second drain/source electrodes and is surrounded by a deep well region. The ESD circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power terminal and includes a first control terminal electrically connected to the deep well region and generates a first control signal. The first discharge circuit is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to potential states of the deep well region and the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 5, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Kai Wang, Chang-Min Lin, Jian-Hsing Lee
  • Patent number: 11296502
    Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
  • Patent number: 11289472
    Abstract: An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su
  • Patent number: 11289902
    Abstract: A composite circuit protection device includes first and second positive temperature coefficient (PTC) components, a voltage-dependent resistor, and first, second and third conductive leads. The first PTC component includes a first PTC layer, and first and second electrode layers respectively disposed on two opposite surfaces of the first PTC layer. The second PTC component includes a second PTC layer, and third and fourth electrode layers respectively disposed on the two opposite surfaces of the second PTC layer. The voltage-dependent resistor is connected to the second and third electrode layers. The first, second and third conductive leads are bonded to the first electrode layer, the voltage-dependent resistor, and the fourth electrode layer, respectively.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 29, 2022
    Assignee: FUZETEC TECHNOLOGY CO., LTD.
    Inventors: Jack Jih-Sang Chen, Chang-Hung Jiang