Voltage Responsive Patents (Class 361/56)
  • Patent number: 10847909
    Abstract: This disclosure relates to a storage device having a small form factor. The storage device can include a circuit board configured to store data. The circuit board can be enclosed in a housing. The storage device can include a connector mounted perpendicularly to an inner surface of the circuit board and extending through an aperture of an inner surface of the housing. The connector may be configured to electrically connect to an electronic device to transfer data between the storage device and the electronic device. The connector may be a universal serial bus (USB) Type-C connector. The storage device may have a thickness, measured between the inner surface of the housing and an outer surface of the housing, that does not exceed 6 millimeters (mm), for example.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kin Ming So
  • Patent number: 10845440
    Abstract: Various approaches of adjusting a gain of received signals in integrated circuitry include implementing an open-loop source-degenerated amplifier having a pair of input devices for amplifying the received signals; boosting an effective transconductance of the input devices (e.g., using a pair of super-gm feedback loops); and setting a bias current of devices in the open-loop source-degenerated amplifier (e.g., using a constant-gm bias circuit).
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 24, 2020
    Assignee: WAVEGUIDE CORPORATION
    Inventors: Michael Trakimas, Alexander Alexeyev
  • Patent number: 10840802
    Abstract: An isolated switched capacitor converter can include: first switches coupled in series between terminals of an input port, and being configured to selectively connect a first terminal of a first capacitor to a first or second terminal of the input port; second switches coupled in series between terminals of an output port, and being configured to selectively connect a second terminal of the first capacitor to a first or second terminal of the output port; third switches coupled in series between terminals of the input port, and being configured to selectively connect a first terminal of a second capacitor to the first or second terminal of the input port; and fourth switches coupled in series between terminals of the output port, and being configured to selectively connect a second terminal of the second capacitor to the first or second terminal of the output port.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 17, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Chen Zhao
  • Patent number: 10840237
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fu Tsai, Tzu-Heng Chang, Yu-Ti Su, Kai-Ping Huang
  • Patent number: 10839750
    Abstract: An electrostatic discharging circuit includes a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and is electrically connected to the first node.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Mee-Hye Jung, Se-Hyoung Cho, Jang-Mi Kang, Kyung-Hoon Kim
  • Patent number: 10826291
    Abstract: An ESD power clamp circuit includes first, second and third timing networks, first and second NMOS transistors and an enable circuit. The first timing network has a first time constant and detects a voltage transient between first and second voltage supply nodes having a rise time less than the first time constant. The first NMOS transistor has a gate connected with an output of the first timing network and a source connected with a gate of the second NMOS transistor. The second NMOS transistor has a drain connected with the first voltage supply node and a source connected with the second voltage supply node. The second timing network is coupled with the gate of the second NMOS transistor and has a second time constant that is greater than a duration of an ESD event. The third timing network is coupled with the enable circuit and has a third time constant, the third timing network generating a first control signal based on the third time constant.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 3, 2020
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventor: Jessel T. Xavier
  • Patent number: 10819109
    Abstract: A chip protection circuit applied to a chip. The chip protection circuit comprises a transformer circuit, a first protection circuit and a second protection circuit. The transformer circuit has a first side and a second side. Each of the first side and the second side is disposed with first terminals, second terminals and center tap terminals. Three center tap terminal is coupled to a ground. The first protection circuit comprises a diode having a terminal coupled to the center tap terminal at the first side and another terminal coupled to the ground. The second protection circuit comprises input terminals and output terminals. The input terminals of the second protection circuit are coupled to the first terminal and the second terminals at the second side. The output terminals of the second protection circuit are coupled to the chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 27, 2020
    Assignee: PEGATRON CORPORATION
    Inventor: Chiu-Yang Pai
  • Patent number: 10819329
    Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 27, 2020
    Assignee: LSIS CO., LTD.
    Inventor: Young-Joo Lee
  • Patent number: 10811874
    Abstract: A load switch integrated circuit and an electronic device are provided. In a case that a surge voltage is applied to an input of the load switch integrated circuit, a surge detection circuit controls a first discharging unit to be switched on to discharge surge energy from an input of the load switch integrated circuit to the ground, and controls a first switch transistor and a second discharging unit to be switched on through a control circuit to discharge surge energy to an output of the load switch integrated circuit to the ground. Compared with a case that surge energy is discharged only by a surge protection circuit in the conventional technology, surge energy is discharged via two paths, and a circuit area is smaller than that in the conventional technology in a case that there is large surge energy to be resisted.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: October 20, 2020
    Assignee: Shanghai Awinic Technology Co., LTD
    Inventors: Jiantao Cheng, Xucheng Luo, Jianwei Hu
  • Patent number: 10804259
    Abstract: An electrostatic protection circuit, a display panel, and a display apparatus are disclosed. The electrostatic protection circuit comprises a switch control unit, a first electrostatic storage unit configured to store charges, and a second electrostatic storage unit configured to store charges, wherein the first electrostatic storage unit has a first terminal connected to a driving line and a second terminal connected to the switch control unit, and the second electrostatic storage unit has a first terminal connected to the switch control unit and a second terminal connected to a common electrode trace.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 13, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xueguang Hao, Yong Qiao, Hongfei Cheng, Xinyin Wu
  • Patent number: 10790277
    Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Maeda, Yasuyuki Morishita, Masanori Tanaka
  • Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • Patent number: 10777351
    Abstract: A complex electronic component includes a body including a first external electrode and a second external electrode, disposed on an external surface thereof and a laminate; a plurality of first electrodes and a plurality of second electrodes, disposed in the laminate and electrically connected to the first external electrode and the second external electrode, respectively; a third electrode and a fourth electrode, disposed on the laminate to be spaced apart from each other and electrically connected to the first external electrode and the second external electrode, respectively; and an ESD discharge layer disposed between the third electrode and the fourth electrode. In addition, a distance between the third electrode and the fourth electrode is within a range of 30 ?m to 60 ?m.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soo Hwan Son, Ho Yoon Kim, Man Su Byun
  • Patent number: 10762862
    Abstract: The present application discloses a display panel and a display apparatus.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 1, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 10763919
    Abstract: In an Intrinsically Safe (IS) PoDL/PoE system, a PHY in power sourcing equipment (PSE) has its differential transmit terminals coupled across a primary winding of an isolation transformer. One secondary winding is coupled between a positive terminal of a DC voltage source and a first wire of a twisted wire pair. Another secondary winding is coupled between a negative terminal (e.g., ground) of the DC voltage source and a second wire of the twisted wire pair. The secondary windings provide differential data signals output from the PHY's transceiver to the wire pair, while the DC voltage from the DC voltage source is coupled to the wire pair via the two secondary windings. The DC power is applied to a remote power device having a PHY that communicates with the PSE PHY. Therefore, the secondary windings have the dual purpose of DC-coupling and magnetically coupling the differential data to/from the PHY.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 1, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Andrew J. Gardner, Gitesh Bhagwat
  • Patent number: 10763665
    Abstract: The present invention relates to an overvoltage protection circuit (1) for protecting the electronics of a motor, in particular of an EC motor, against overvoltage pulses, with two protective devices (FS1, FS2) arranged in series connection between two connections (10, 20), wherein a resistor (R1) or (R2) is connected in parallel to each of the protective devices (FS1, FS2) and at least one capacitive element (C1) is provided in parallel connection to the first protective device (FS1), wherein the overvoltage protection circuit (1) has, between the connections (10, 20), at least a first (lower) and a second (higher) breakdown voltage point at a voltage UZ1 or UZ2 dependent on the voltage change over time k=(dU/dt) of a voltage UGA at the connections (10, 20).
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 1, 2020
    Assignee: ebm-papst Mulfingen GmbH & Co.KG
    Inventors: Fabian Schneider, Daniel Koenig
  • Patent number: 10754611
    Abstract: One embodiment provides a method, including: creating, for a user, a sound desirability index comprising (i) a plurality of sounds and (ii) desirability of the sound to the user with respect to each of the plurality of sounds, wherein the sound desirability index is created in response to the user hearing a sound and the environment of the user when hearing the sound; receiving an audible input within hearing proximity of the user; identifying the current environment of the user; determining the desirability of the audible input to the user by accessing the sound desirability index, and determining the desirability of the audible input based upon a sound in the audible input and the current environment of the user; and modifying a characteristic of at least a portion of the audible input based upon the desirability of the audible input to the user.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Priyanka Agrawal, Pankaj S. Dayama, Amit Anil Nanavati, Amrita Saha, Srikanth Govindaraj Tamilselvam
  • Patent number: 10749336
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
  • Patent number: 10749338
    Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Stefan Seidl, David Alvarez
  • Patent number: 10734176
    Abstract: A surge protective device (SPD) module includes a module housing, first and second module electrical terminals mounted on the module housing, a gas discharge tube (GDT) mounted in the module housing, and a fail-safe mechanism mounted in the module housing. The GDT includes a first GDT terminal electrically connected to the first module electrical terminal and a second GDT terminal electrically connected to the second module electrical terminal. The fail-safe mechanism includes: an electrically conductive shorting bar positioned in a ready position and repositionable to a shorting position; a biasing member applying a biasing load to the shorting bar to direct the shorting bar from the ready position to the shorting position; and a meltable member. The meltable member maintains the shorting bar in the ready position and melts in response to a prescribed temperature to permit the shorting bar to transition from the ready position to the shorting position under the biasing load of the biasing member.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: August 4, 2020
    Assignee: Raycap, Surge Protective Devices, Ltd.
    Inventors: Sebastjan Kamen{hacek over (s)}ek, Tadej Knez, Igor Juri{hacek over (c)}ev, Milenko Vukotić, Thomas Tsovilis, Zafiris G. Politis
  • Patent number: 10714933
    Abstract: An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ponnarith Pok, Timothy Don Davis
  • Patent number: 10714601
    Abstract: A vertical channel transistor comprising: a structure made of a given bismuth-based material which passes through a gate block where the structure comprises a channel region which extends through the gate block and source and drain regions on either side of the channel region and of the gate block, where the source and drain regions have a cross-section which is greater than the cross-section of the channel region (FIG. 1K).
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 14, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean-Pierre Colinge
  • Patent number: 10698238
    Abstract: A controlling circuit includes a pulse width modulation (PWM) circuit, a level shifter having a current source therein, a capacitor connected to a current source, an overcurrent protection circuit connected to the level shifter, and a controlling circuit configured to enable or disable a function of overcurrent protection of the overcurrent protection circuit within designated time. The controlling circuit includes a switch device. An input of the switch device connected to an output terminal of the capacitor, and an output terminal of the switch device connected to a controlling terminal of the overcurrent protection circuit.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 30, 2020
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Xianming Zhang, Wenfang Li
  • Patent number: 10651170
    Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lung Tung, Min-Chang Liang, Fang Chen
  • Patent number: 10651166
    Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Handoko Linewih, Chien-Hsin Lee
  • Patent number: 10651274
    Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunglyong Kim, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 10644501
    Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 5, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Shi-Hsiang Lu, Geeng-Lih Lin
  • Patent number: 10630075
    Abstract: An apparatus is described. The apparatus includes an electronic circuit includes multiple supply voltage nodes, an output node and an internal node. The electronic circuit also includes first protection circuitry coupled between the internal node and the output node. The electronic circuit also includes a control circuit coupled to the internal node to bias the internal node. The electronic circuit also includes second protection circuitry coupled to the internal node.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Stephan Henzler, Heike Schwager, Stephan Drueen, Krzysztof Domanski
  • Patent number: 10622884
    Abstract: The invention relates to an electric circuit arrangement for the input protection circuit of a switching power supply, having a surge protection circuit, which is contacted with a supply voltage on an input side and to which a current-compensated choke is connected as a suppression component, said current-compensated choke being connected to a rectifier circuit comprising an energy storage means on an output side. Via modifications to the circuit technology, such as using two varistors as surge protections, and by using suitable switching elements, such as silicon diodes as rectifier elements and ceramic capacitors as an energy storage means, the input protection circuit is designed such that the requirements, which an expanded input voltage range demands of a surge circuit, are fulfilled. Furthermore, the invention relates to a switching power supply having an electric circuit arrangement according to the invention for the input protection circuit.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 14, 2020
    Assignee: BENDER GMBH & CO. KG
    Inventor: Oliver Schaefer
  • Patent number: 10622986
    Abstract: The present disclosure discloses a gate voltage control circuit of an IGBT and a control method thereof. The gate voltage control circuit of the IGBT comprises a voltage control circuit, an active clamping circuit and a power amplifier circuit. A control voltage outputted by the voltage control circuit indirectly controls a gate voltage of the IGBT, so as to achieve a better control of the gate voltage of the IGBT with a smaller loss. It may prevent the active clamping circuit from a too-early response and may increase the active clamping circuit response speed; and may avoid the voltage oscillation of the collector-emitter voltage Vce and the gate voltage Vge, and may improve the reliability of the IGBTs connected in series.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 14, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Jianping Ying, Ming Wang, Xiaobo Huang, Jun Liu, Lifeng Qiao, Xin Wang
  • Patent number: 10615595
    Abstract: An integrated circuit is provided in which a surge protector, protecting against modest over-voltage events which may contain a lot of energy, and an electrostatic discharge (ESD) protector, protecting against high voltage events that may contain only a little energy, are provided within the integrated circuit package. The two types of protectors may protect against different types of electrical events.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 7, 2020
    Assignee: Analog Devices Global
    Inventors: James Scanlon, Brian Anthony Moane, John Twomey
  • Patent number: 10608431
    Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: March 31, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Linfeng He, Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 10608554
    Abstract: A power supply, including a primary pre-converter, coupled to supplying mains, configured to receive an AC voltage at low frequency and output a high DC voltage, and further configured to receive the high DC voltage and to output the alternating current; a primary converter, disposed on a primary side of the power supply, coupled to the high DC voltage from the primary pre-converter; an isolating transformer to receive the high frequency AC voltage and output a high frequency secondary AC voltage, and to receive a high frequency secondary AC current and to output primary high frequency AC current; and an output converter, on a secondary side of the power supply, wherein the output converter is configured to receive high frequency AC voltage from the isolating transformer and to output a DC voltage of a first or second polarity to an output, and wherein the output converter is configured to receive DC current of a first or second direction from the output and to output a high frequency AC current to the isolat
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 31, 2020
    Assignee: ESAB AB
    Inventor: Andrzej Mnich
  • Patent number: 10600776
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, and a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes. The first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure. Other embodiments are also described.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 24, 2020
    Assignee: NXP B.V.
    Inventors: Da-Wei Lai, Wei-Jhih Tseng
  • Patent number: 10601421
    Abstract: A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 24, 2020
    Assignee: Ademco Inc.
    Inventors: Jesus Omar Ponce, Luis Carlos Murillo, Cesar Alejandro Arzate, Eduardo Saenz Balderrama
  • Patent number: 10580478
    Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael V. Ho
  • Patent number: 10582317
    Abstract: The disclosure presents a method and a hearing device comprising a first portion adapted for being arranged behind an ear of a user for providing a signal, an output transducer for converting the signal to an acoustic output, a coupling element coupled to the first portion, and wherein the coupling element is adapted for transmitting at least the signal or the acoustic output.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 3, 2020
    Assignee: OTICON A/S
    Inventors: Jens Troelsen, Rune Sø, Morten Thougaard
  • Patent number: 10574224
    Abstract: The present disclosure discloses a drive circuit of a transistor, including: a high-voltage power supply and a low-voltage power supply; a high-voltage power supply domain circuit and a low-voltage power supply domain circuit, where the high-voltage power supply domain circuit is connected to the high-voltage power supply; an electrostatic discharge apparatus; a level shifter circuit, wherein the level shifter circuit includes a level detection circuit, a current limiting module, a discharge module, and a switch transistor, the level detection circuit is connected to a positive electrode of the high-voltage power supply and is separately connected to the current limiting module, the discharge module, and the high-voltage power supply domain circuit, the current limiting module is further connected to a first end of the switch transistor, the discharge module is further connected to a negative electrode of the high-voltage power supply, a control end of the switch transistor is connected to the low-voltage pow
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 25, 2020
    Assignee: BYD COMPANY LIMITED
    Inventors: Ping Fu, Fei Gao
  • Patent number: 10567029
    Abstract: A multiway switch, a radio frequency system, and an electronic device are provided. The multiway switch is applicable to an electronic device being operable in a single-frequency dual-transmit mode. The electronic device includes the multiway switch, a radio frequency circuit, and an antenna system. The multiway switch includes four T ports and 2n P ports. The four T ports are configured to be coupled with the radio frequency circuit. The 2n P ports are configured to be coupled with the antenna system. The four T ports include two first T ports coupled with all of the 2n P ports. The multiway switch is configured to be coupled with the radio frequency circuit and the antenna system to implement a preset function of transmitting a sounding reference signal (SRS) through 2n antennas of the antenna system corresponding to the 2n P ports in turn.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 18, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Jian Bai
  • Patent number: 10560137
    Abstract: A multiway switch, a radio frequency system, and a wireless communication device are provided. The multiway switch includes five throw (T) ports and four pole (P) ports. The five T ports include one first T port coupled with all of the four P ports. The multiway switch is configured to be coupled with a radio frequency circuit and an antenna system of an electronic device operable in a dual-frequency single-transmit mode, to enable a preset function of the electronic device, the antenna system includes four antennas corresponding to the four P ports, and the preset function is a function of transmitting a sounding reference signal (SRS) through the four antennas in turn.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 11, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Jian Bai
  • Patent number: 10541527
    Abstract: An amplitude limiter circuit includes an inductor and a shunt circuit. The inductor has a first terminal connected to an input node. The shunt circuit is connected to a second terminal of the inductor and also is connected to a low impedance node. If an overvoltage condition forms on the input node, the shunt circuit forms an overvoltage current path from the input node, through the inductor, through the shunt circuit and to low impedance node.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Robert C. Taft, Alexander Bodem
  • Patent number: 10535994
    Abstract: An air gap metal tip structure is provided for ESD protection that includes a lower substrate and an upper substrate disposed above the lower substrate. The air gap metal tip structure includes a first and a second metal tip disposed along at least one horizontal axis that is parallel to the upper substrate and the lower substrate. The air gap metal tip structure includes an air chamber formed between the upper and lower substrates within which the first and second metal tips are disposed. The air chamber includes a portion between points of the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an occurrence of an arc between the tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the tips to maintain the ESD protection for subsequent arcs.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qianwen Chen, Yang Liu, Dongbing Shao, Zheng Xu
  • Patent number: 10529702
    Abstract: An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is configured to provide a ground potential. The plurality of bi-directional pins are configured to provide a differential input signal for the integrated circuit. The electro-static discharge (ESD) clamp is coupled between the ground potential and the plurality of bi-directional pins.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhong Chen, Danyang Zhu, Zhuang Ma
  • Patent number: 10523002
    Abstract: An electrostatic discharge (ESD) protection circuit is provided. A detector is coupled between a first input-output pad and a second input-output pad and detects the voltage levels of the first and second input-output pads to generate a detection signal. A inverter generates a control signal according to the detection signal. A control element is coupled between the first input-output pad and a first node. A current release element is coupled between the first node and the second input-output pad. When the detection signal is at a specific level, the control element and the current release element provide a discharge path to release an ESD current from the first input-output pad to the second input-output pad. When the detection signal is not at the specific level, the control element and the current release element do not provide a discharge path.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 31, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Patent number: 10516442
    Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 24, 2019
    Assignee: Rambus Inc.
    Inventors: John W. Poulton, Frederick A. Ware, Carl W. Werner
  • Patent number: 10514409
    Abstract: A device for detecting a number of electrostatic discharges including a discharge protection unit, in which a detection unit is electrically connected in parallel to the discharge protection unit and the detection unit generates an output signal, which represents the number of electrostatic discharges. A related method is also described.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: December 24, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Michael Graf, Timo Seitzinger
  • Patent number: 10506706
    Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shle-Ge Lee, Youngbae Kim
  • Patent number: 10505364
    Abstract: An electrostatic discharge (ESD) protection apparatus includes: an ESD circuit, arranged to perform ESD protection, wherein the ESD circuit includes a first Field Effect Transistor (FET) arranged to release ESD energy; a detection circuit, arranged to perform detection to control the ESD protection apparatus to selectively operate in one of a normal mode and a discharge mode; and a logic circuit, arranged to withstand any oscillation due to resistance-inductance-capacitance (RLC) characteristics of the detection circuit. In the detection circuit, different subsets of a plurality of resistors are respectively combined with a portion of a first serial connection circuit, an entirety of the first serial connection circuit, and a second FET to form different serial connection circuits, to configure the second FET to approach a state of being completely turned off in the normal mode.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 10, 2019
    Assignee: Faraday Technology Corp.
    Inventor: Chia-Ku Tsai
  • Patent number: 10497780
    Abstract: In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Moshe Agam, Agajan Suwhanov, Johan Camiel Julia Janssens
  • Patent number: 10497697
    Abstract: A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 3, 2019
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Shekar Mallikarjunaswamy