Voltage Responsive Patents (Class 361/56)
  • Patent number: 10418358
    Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A first isolation layer is provided over the first surface of the semiconductor body. The semiconductor device further includes an electrostatic discharge protection structure over the first isolation layer. The electrostatic discharge protection structure has a first terminal region of a first conductivity type and a second terminal region of a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventor: Joachim Weyers
  • Patent number: 10418939
    Abstract: VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 17, 2019
    Assignee: The Regents of the University of California
    Inventors: Matthew Guthaus, Ping-Yao Lin
  • Patent number: 10404051
    Abstract: A protective circuit (10) comprises a terminal (11), a reference potential terminal (12) and a protective structure (13) that is arranged between the terminal (11) and the reference potential terminal (12), and is designed to be conductive in the event of an electrostatic discharge. The protective circuit (10) furthermore comprises a voltage supply circuit (14) that is coupled to a control input (16) of the protective structure (13) with its output side and is designed for delivering, in the event of radiofrequency interference, a control signal (ST) to the control input (16) with such a high voltage value that conduction of the protective structure (13) is prevented.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: September 3, 2019
    Assignee: ams AG
    Inventors: Wolfgang Reinprecht, Christian Stockreiter, Bernhard Weiss
  • Patent number: 10405386
    Abstract: A light emitting element driving apparatus includes the following: current source; error amplifier generating error signal based on comparison of a first reference voltage with the highest voltage among total forward drop voltages of element arrays or feedback voltage corresponding to a drive voltage; first and second switches for ON/OFF control to apply the feedback voltage to first and second input terminals of the error amplifier respectively; slope voltage generating circuit; PWM comparator generating a pulse modulation signal; drive amplifier controlled by the pulse modulation signal and drives a switching element supplying the drive voltage to the element arrays; PWM width detector that outputs a pulse width detection signal having different levels between when the pulse width is less than predetermined threshold value and when equal to or greater than the threshold value, and switches ON/OFF of the first and second switches based on the pulse width detection signal.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 3, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Koji Katsura, Ryosuke Kanemitsu, Keisuke Miura
  • Patent number: 10396068
    Abstract: An electrostatic discharge (ESD) protection device including an ESD protection unit and a control circuit is provided. When a voltage level of a signal received by a signal input terminal reaches an ESD protection level, the ESD protection unit transmits the signal from the signal input terminal to the system voltage terminal. The control circuit controls a conduction state between the signal input terminal and the system voltage terminal through the ESD protection unit. The control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the ESD protection unit, and to prevent the ESD protection unit from transmitting the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the ESD protection level.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 27, 2019
    Assignee: ALi Corporation
    Inventors: Chuan-Sheng Lee, Bing-You Gao
  • Patent number: 10396549
    Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masashi Arakawa, Tadashi Fukui, Koji Takayanagi
  • Patent number: 10388561
    Abstract: A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first ESD protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. The second ESD protecting circuit may include at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Yun Seok Hong
  • Patent number: 10381827
    Abstract: A protection circuit includes a first PMOS and a first PDMOS receiving input of voltage of a voltage dividing point of voltage input from an external power supply terminal, and a second PMOS and a second PDMOS receiving input of drain output voltage of the first PDMOS. The first PMOS is connected on the external power supply terminal side of the first PDMOS, and the second PMOS is connected on the external power supply terminal side of the second PDMOS. During overvoltage application, the voltage of the voltage dividing point is clamped to the breakdown voltage of a Zener diode, the second PDMOS turns OFF, and supply to an integrated circuit protected from overvoltage is cut off. When the voltage source is connected in reverse, parasitic diodes of the first and second PMOSs are reverse-biased and the flow of current in a path through the parasitic diodes is inhibited.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 13, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mutsuo Nishikawa, Kazuhiro Matsunami, Katsuhiro Shimazu
  • Patent number: 10381806
    Abstract: An ESD protection device includes a bare unitary body, and a first discharge electrode and a second discharge electrode that are disposed inside the bare unitary body. The first discharge electrode and the second discharge electrode are opposed to each other with a gap interposed therebetween. The bare unitary body includes a cavity in which the gap between the first discharge electrode and the second discharge electrode is located, and to which the first discharge electrode and the second discharge electrode are exposed. A first space of the cavity on a side closer to the first discharge electrode is smaller than a second space of the cavity on a side closer to the second discharge electrode.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 13, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsumi Yasunaka, Jun Adachi
  • Patent number: 10374420
    Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD event detector. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: August 6, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Mark B. Welty
  • Patent number: 10374418
    Abstract: A circuit and a method for electrostatic discharge clamping are provided. The circuit includes a detection module, a control module, and a clamping module. The detection, control, and clamping modules are coupled with a first power line of a first power source and a second power line of the first power source. Third terminals of the detection, control and clamping modules are coupled to a first power line of a second power source, a voltage division terminal of the detection module, a fourth terminal of the control module respectively. According to an electrostatic discharge event on the first power line of the first power source, the division voltage terminal of the detection module provides a voltage to the control module. Then, the control module controls the clamping module to couple the first power line of the first power source to the second power line of the first power source.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: August 6, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Ting Yeh, Yung-Chih Liang
  • Patent number: 10348085
    Abstract: This static electricity protection circuit starts a discharge operation only if an applied voltage is greater than or equal to a set voltage, and protects a discharge circuit also when noise or the like is applied during a normal operation. This static electricity protection circuit includes: a resistor R1 and clamp circuit that are connected in series between nodes N1 and N2; a first transistor that turns on in accordance with an increase in a potential difference generated in the resistor R1; a resistor R2 and capacitor C2 that are connected via a node N4 between the nodes N1 and N2; a second transistor that is connected in series with the first transistor between the nodes N1 and N5; a resistor R3 connected between the nodes N5 and N2; a third transistor connected between the nodes N4 and N2; and a discharge circuit connected between the nodes N1 and N2.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: July 9, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Masuhide Ikeda
  • Patent number: 10340263
    Abstract: An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Sig Won, Chan Uk Shin, Kwang Ok Jeong, Kwon Chil Kang
  • Patent number: 10332871
    Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Cornelius Russ, Giuseppe Curello, Tomasz Biedrzycki, Franz Kuttner, Luis F. Giles, Bernhard Stein
  • Patent number: 10333002
    Abstract: Provided are a thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device. The thin film transistor comprises: an active layer, an etch stop layer disposed on the active layer, an overcoating layer disposed on the etch stop layer, and a source electrode and a drain electrode disposed on the overcoating layer, wherein the overcoating layer comprises at least one of a conductive material layer, a non-transparent insulation layer and a non-transparent semiconductor layer, and the source electrode and the drain electrode are electrically connected with the active layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 25, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Seungjin Choi, Jaehong Kim
  • Patent number: 10333464
    Abstract: There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 25, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Ian Juso Dedic, Abdullah Mohd. Riazuddin Ahmed
  • Patent number: 10320186
    Abstract: A display drive chip includes an electrostatic discharge (ESD) protection circuit unit configured to protect a circuit from ESD, an output including output pins for ouputting an output signal from a circuit disposed in an electric circuit region located in a central part of the display drive chip, a main voltage metal line electrically connecting the ESD protection circuit unit and the output to each other in the electric circuit region, an auxiliary voltage metal line that is connected to the ESD protection circuit unit and is disposed in a region of the chip outside the perimeter of the electric circuit region, and connection metal lines electrically connect the auxiliary voltage metal line and the output pins to each other.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoun-Soo Kim, Myoung-Soo Kim
  • Patent number: 10320185
    Abstract: An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (RC) filter, a drive circuit including a first inverter stage receiving an input signal from the RC filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the RC filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Robert Matthew Mertens, Alexander Paul Gerdemann, Michael A. Stockinger
  • Patent number: 10304822
    Abstract: The present disclosure provides a substrate and a display device. The substrate includes an internal region and a peripheral region surrounding the internal region, a plurality of signal wires and at least one ground wire being included in the peripheral region; any two adjacent signal wires, as well as the signal wire and the ground wire which are adjacent to each other, are connected through a selective connection structure; and the selective connection structure is capable of being connected in case of electro-static discharge. In the substrate and the display device provided by the present disclosure, because static electricity in each signal channel inside the substrate can be finally discharged via the ground wire in case of ESD, ESD protection for each signal channel in the internal region and the signal wire connected thereto can be achieved.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: May 28, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wenjin Fan, Lei Zhang, Ming Hu, Yuhui Lai, Qingpu Wang, Jun Li
  • Patent number: 10298215
    Abstract: Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Gao, Yi Lu, Handoko Linewih
  • Patent number: 10290628
    Abstract: The present application belongs to field of integrated circuit and discloses an electrostatic discharge protection circuit comprising a first N-type transistor and a second N-type transistor. The first N-type transistor comprises a first gate terminal coupled to a ground terminal; a first electrode terminal coupled to the first gate terminal; and a second electrode terminal. The second N-type transistor comprises a second gate terminal coupled to a metal pad; a third electrode terminal coupled to the second gate terminal; a fourth electrode terminal, coupled to the second electrode terminal; and a first deep N well, disposed under the third electrode terminal and the fourth electrode terminal. The ESD protection circuits provided by the embodiments of the present application have advantages of small circuit area and good ESD protection.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 14, 2019
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Tsung-Lung Lee, Fu-Chiang Yang
  • Patent number: 10290758
    Abstract: A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 14, 2019
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Matthieu Moors, David D. Smith, Gabriel Harley, Taeseok Kim
  • Patent number: 10291020
    Abstract: An overvoltage protection device includes a resistor that is connected in series between an internal signal line connected to a communication terminal of a processor and a communication line, a diode of which a cathode is connected to the internal signal line and an anode is connected to a ground, and a PNP transistor of which a base is connected to a power supply terminal, an emitter is connected to the internal signal line, and a collector is connected to the ground. When a base-emitter voltage (a junction saturation voltage) of the transistor in operation is defined as VBE and a power source is turned on (a voltage V1) by the operation of the transistor, a voltage of the internal signal line is limited to the source voltage V1+VBE. When the power source is turned off (a voltage 0 V), the voltage of the internal signal line is limited to the source voltage 0 V+VBE.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 14, 2019
    Assignee: ALPINE ELECTRONICS, INC.
    Inventor: Norihiko Tanaka
  • Patent number: 10281499
    Abstract: A high side current monitoring apparatus monitors a load current flowing into a load apparatus. The high side current monitoring apparatus includes a current mirror unit, an active high voltage unit, a voltage detection unit and a bias unit. The current mirror unit generates a mirrored current and outputs the mirrored current according to the load current. The active high voltage unit is electrically connected to the current mirror unit and receives the mirrored current and works in a linear area to withstand a high voltage. The voltage detection unit is electrically connected to the active high voltage unit and detects a voltage drop across the voltage detection unit and caused by the mirrored current. The bias unit is electrically connected to the active high voltage unit and provides the active high voltage unit with a bias.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 7, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Tsung-Tai Cheng
  • Patent number: 10278272
    Abstract: An ESD protection device includes a ceramic element assembly including a glass component, first and second discharge electrodes on the same plane in the ceramic element assembly and opposed to each other with a gap therebetween, a discharge auxiliary electrode that connects the first discharge electrode to the second discharge electrode on the same plane, and a seal layer that is disposed between the discharge auxiliary electrode and the ceramic element assembly and that reduces or prevents a glass component in the ceramic element assembly from entering the discharge auxiliary electrode. The seal layer includes a conductive component.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takeshi Miki, Hiromitsu Hongo, Takahiro Sumi
  • Patent number: 10263417
    Abstract: A transient voltage suppressing (TVS) integrated circuit includes an input output pin, a ground pin, a substrate, a first TVS die and a second TVS die. The substrate provides a common bus. The first TVS die is disposed on the substrate, and includes a first input output terminal and a first reference ground terminal. The second TVS die is disposed on the substrate and includes a second input output terminal and a second reference ground terminal. The second reference ground terminal is electrically coupled to the first reference ground terminal through the common bus, and the first input output terminal is coupled to the first input out pin, and the second input output terminal is coupled to a ground pin.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 16, 2019
    Assignee: uPI Semiconductor Corp.
    Inventor: Chih-Hao Chen
  • Patent number: 10262987
    Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: April 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Cih Wang, Lu-An Chen, Tien-Hao Tang
  • Patent number: 10263418
    Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ephrem G. Gebreselasie, Icko E. T. Iben, Alain Loiseau
  • Patent number: 10256224
    Abstract: A multiple-unit semiconductor device (1) includes a normally-ON type first FET (11) and a normally-OFF type second FET (12) that are connected to each other in series between a first terminal and a second terminal (17 and 19). The multiple-unit semiconductor device (1) further includes a protection circuit that includes a switching element for discharge (16) connected to the second FET in parallel and a trigger circuit that is disposed between the first terminal and the second terminal (17 and 19) and causes the switching element for discharge to turn to an ON state when a surge is applied to the first terminal.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 9, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masaya Isobe
  • Patent number: 10249608
    Abstract: An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 2, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Iqbal Chaudhry
  • Patent number: 10250027
    Abstract: A DC and/or an AC power transmission circuit protection system is for protection of a cabling medium. The circuit protection system includes a power supply, a powered device and a circuit protection module that includes an over-current and/or over-voltage circuit module and/or a heat circuit protector. The protection system is disposed between the power supply and the powered device, and interrupts an electrical current that flows through the cabling medium when the over-current and/or over-voltage circuit module and/or the circuit protector exceeds a predetermined level. There is also provided a method to dispose the circuit protection system and the circuit protection module within the circuit and to interrupt the circuit when over-current and/or over-voltage circuit module and/or heat circuit protector exceeds a predetermined level.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: April 2, 2019
    Inventor: Frederick M. Foster
  • Patent number: 10236682
    Abstract: The invention relates to an inrush current free switching apparatus and control method thereof. The inrush current free switching apparatus includes a mechanical switch, a first unidirectional thyristor, a second unidirectional thyristor, a control unit, and a current limiting element. The first unidirectional thyristor is connected with the current limiting element in series to form a series circuit, the series circuit is connected with the second unidirectional thyristor in parallel, two ends of a main circuit of the mechanical switch is connected with the second unidirectional thyristor in parallel, the control unit is connected with the control terminal of the mechanical switch, the control unit is connected with the first unidirectional thyristor and the second unidirectional thyristor. The control unit prestores operating time parameters of the mechanical switch.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 19, 2019
    Assignees: GUANGZHOU KINGSER ELECTRONICS CO., LTD.
    Inventor: Qiaoshi Guo
  • Patent number: 10224969
    Abstract: The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Takeda, Hirokazu Nagase, Shinpei Watanabe
  • Patent number: 10219362
    Abstract: An ESD protection device includes: a first insulating layer (2a); a second insulating layer (2b) stacked on the first insulating layer (2a); a first via conductor (6a) extending through the first insulating layer (2a) in a thickness direction; a discharge gap portion (10) provided so as to be in contact with the first via conductor (6a), between the first insulating layer (2a) and the second insulating layer (2b); a first wiring line (7a) that is arranged on a surface of the first insulating layer (2a) opposite to the discharge gap portion (10) and that is electrically connected to the first via conductor (6a); and a second wiring line (7b) that is arranged on one surface of the second insulating layer (2b) and that includes a portion facing the first via conductor (6a) with at least the discharge gap portion (10) interposed therebetween.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 26, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshihito Otsubo
  • Patent number: 10218171
    Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.
    Type: Grant
    Filed: November 6, 2016
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Dongyong Zhu, Arjan Mels, Peter Christiaans
  • Patent number: 10211795
    Abstract: Aspects of this disclosure relate to an impedance transformation circuit and overload protection for a low noise amplifier. A low noise amplifier can include a first inductor, an amplification circuit configured to amplify a radio frequency signal, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier. A switch can be coupled to the amplification circuit of the low noise amplifier. An overload protection circuit can adjust an impedance of the switch based on a signal level associated with the radio frequency signal to provide overload protection for the low noise amplifier.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 19, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Leslie Paul Wallis
  • Patent number: 10199369
    Abstract: Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant actively-controlled protection circuit includes a transient overstress detection circuit, a clamp circuit electrically connected between a first node and a second node, a bias circuit that biases the clamp circuit, and a false condition shutdown circuit. The transient overstress detection circuit generates a detection signal indicating whether or not a transient overstress event is detected between the first and second nodes. Additionally, the false condition shutdown circuit generates a false condition shutdown signal based on low pass filtering a voltage difference between the first and second nodes, thereby determining independently whether or not power is present. The bias circuit controls operation of the clamp circuit in an on state or an off state based on the detection signal and the false condition shutdown signal.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 5, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Patent number: 10181721
    Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xianzhi Dai, Farzan Farbiz, Muhammad Yusuf Ali
  • Patent number: 10177137
    Abstract: An electrostatic discharge (ESD) protection apparatus is provided. A first power rail provides first reference voltage. A second power rail provides a second reference voltage. A detection circuit generates a detection result according to whether ESD stress occurs on the first power rail. A first N-type MOSFET has its gate serving as a control terminal. A second N-type MOSFET has its gate serving as a second control node. An intermediate power rail provides an intermediate voltage between the first and the second reference voltages. A first switching circuit couples the first control node to the intermediate power rail or to the first power rail according to the detection result. A second switching circuit couples the second control node to the second power rail or to the first control node according to the detection result.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: January 8, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Federico Agustin Altolaguirre, Yen-Hung Yeh, Po-Ya Lai
  • Patent number: 10170542
    Abstract: A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate field-effect transistors (JFETs), an isolation structure, and a buried layer of a second conductivity type is provided. The MOSFET is located on the substrate and has a first epitaxial layer of the second conductivity type. The JFET is located on the substrate and has a second epitaxial layer of the second conductivity type. The isolation structure is located between the MOSFET and the JFET to separate the first epitaxial layer from the second epitaxial layer. The buried layer is located between the MOSFET and the substrate. The buried layer extends from below the MOSFET to below the isolation structure and below the JFET, so as to electrically connect the MOSFET to the first JFET.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 1, 2019
    Assignee: Nuvoton Technology Corporation
    Inventor: Wen-Ying Wen
  • Patent number: 10163894
    Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
  • Patent number: 10163823
    Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chou Tseng, Tzu-Heng Chang
  • Patent number: 10164629
    Abstract: In one aspect of the teachings herein, a switching circuit for switching a power transistor is configured to control the slew rate of the switched load current in a manner that yields substantial independence from the load voltage, based on the use of a Miller-effect compensation capacitor and controllable source resistances for driving the gate or base of the power transistor. In a non-limiting example, a control circuit, such as a microcontroller, uses a set of bidirectional input/output ports to drive the transistor base or gate through a selectable combination of parallel resistors, so that the effective source resistance for transistor turn-on and turn-off is selectable by configuring different combinations of input/output settings for the set of bidirectional input/output ports. Controlling the source resistance in this manner allows the control circuit to set or otherwise control the slew rate of the load current.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: December 25, 2018
    Assignee: Omron Automotive Electronics, Inc.
    Inventor: Lucretiu Pisau
  • Patent number: 10158029
    Abstract: Apparatus and methods for compound semiconductor protection clamps are provided herein. In certain configurations, a compound semiconductor protection clamp includes a resistor-capacitor (RC) trigger network and a metal-semiconductor field effect transistor (MESFET) clamp. The RC trigger network detects when an ESD/EOS event is present between a first node and a second node, and activates the MESFET clamp in response to detecting the ESD/EOS event. When the MESFET clamp is activated, the MESFET clamp provides a low impedance path between the first and second nodes, thereby providing ESD/EOS protection. When deactivated, the MESFET clamp provides high impedance between the first and second nodes, and thus operates with low leakage current and small static power dissipation.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: December 18, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Patent number: 10153271
    Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and a surface portion of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: December 11, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10148810
    Abstract: A structure protects a SLIC telephone line interface against overvoltages lower than a negative threshold or higher than a positive threshold. The structure includes at least one thyristor connected between each conductor of the telephone line and a reference potential. For all of the included thyristors, a metallization corresponding to the main electrode on the gate side is in contact, by its entire surface, with a corresponding semiconductor region. Furthermore, the gate of each thyristor is directly connected to a voltage source defining one of the thresholds.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 4, 2018
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Jean-Michel Simonnet, Christian Ballon
  • Patent number: 10147688
    Abstract: An integrated circuit device includes a package and at least two leads exposed external to the package to permit electrical connections to the package. A first die situated in the package has a first substrate and at least a first terminal electrically coupled to a first one of the leads. A second die situated in the package has a second substrate and at least a second terminal electrically coupled to a second one of the lead. An adhesive material holding the first and second die in place forms a voltage-triggered conduction path between the first and second die electrically that isolates the second die from the first die under a first condition and provides an ESD current path between the first one of the leads and the second one of the leads under a second condition.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: December 4, 2018
    Assignee: Allegro Microsystems, LLC
    Inventors: William Wilkinson, Washington Lamar, Maxim Klebanov
  • Patent number: 10141300
    Abstract: A transient voltage suppressor (TVS) circuit includes a P-N junction diode and a silicon controlled rectifier (SCR) formed integrated in a lateral device structure of a semiconductor layer. The lateral device structure includes multiple fingers of semiconductor regions arranged laterally along a first direction on a major surface of the semiconductor layer, defining current conducting regions between the fingers. The current paths for the SCR and the P-N junction diode are formed in each current conducting region but the current path for the SCR is predominantly separated from the current path for the P-N junction diode in each current conducting region in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The TVS device of the present invention realizes low capacitance at the protected node. The TVS device is suitable for protecting data pins of an integrated circuit, especially when the data pins are used in high speed applications.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 27, 2018
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10141301
    Abstract: Semiconductor devices with cross-domain electrostatic discharge (ESD) protection and related fabrication methods are provided. An exemplary semiconductor device includes first domain circuitry, second domain circuitry, and an interface coupled between an output node of the first domain driver circuitry and second domain receiver circuitry. The receiver circuitry includes a transistor having a gate electrode coupled to the interface, with a body electrode of the transistor being coupled to protection circuitry of the first domain circuitry. The body electrode is effectively biased to a reference voltage node of the first domain by the protection circuitry in response to an ESD event to protect the gate oxide of the transistor from a potentially damaging ESD voltage.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 27, 2018
    Assignee: NXP B.V.
    Inventors: Da-Wei Lai, Taede Smedes
  • Patent number: 10141298
    Abstract: A semiconductor integrated circuit device may include a first discharging unit and a second discharging unit. The first discharging unit may be coupled between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level. The first discharging unit may be configured to discharge an electrical over stress (EOS) generated from the first line. The second discharging unit may be coupled between the first line and the second line. The second discharging unit may discharge the EOS in the first line to the second line based on an output signal from the first discharging unit.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 27, 2018
    Assignee: SK hynix Inc.
    Inventor: Yun Seok Hong