METHOD AND APPARATUS FOR CORRECTING ERRORS ON A WAFER PROCESSED BY A PHOTOLITHOGRAPHIC MASK

-

A method for correcting errors on a wafer processed by a photolithographic mask at a wafer processing site is provided. The method comprises measuring errors on the wafer, and modifying a pattern placement on the photolithographic mask by locally applying femtosecond light pulses of a laser system to the photolithographic mask at the wafer processing site.

Skip to: Description  ·  Claims  · Patent History  ·  Patent History
Description
CROSS REFERENCE TO RELATED APPLICATIONS

Pursuant to 35 U.S.C. §119, this application claims the benefit of U.S. provisional application 61/424,422, filed on Dec. 17, 2010, which is herein incorporated by reference.

TECHNICAL FIELD

The present invention relates to the field of correcting errors on a wafer processed by a photolithographic mask.

BACKGROUND

As a result of the shrinking sizes of integrated circuits, photolithographic masks or templates of the nanoimprint lithography have to project smaller and smaller structures onto a photosensitive layer, i.e. a photoresist dispensed on a wafer. In order to fulfil this demand, the exposure wavelength of photolithographic masks has been shifted from the near ultraviolet across the mean ultraviolet into the far ultraviolet region of the electromagnetic spectrum. Presently, a wavelength of 193 nm is typically used for the exposure of the photoresist on wafers. As a consequence, the manufacturing of photolithographic masks with increasing resolution is becoming more and more complex, and thus more and more expensive as well. In the future, photolithographic masks will use significantly smaller wavelengths in the extreme ultraviolet (EUV) wavelength range of the electromagnetic spectrum (approximately at 13.5 nm).

Photolithographic masks have to fulfil highest demands with respect to transmission homogeneity, planarity, pureness and temperature stability. In order to fabricate photolithographic masks with a reasonable yield, defects or errors of masks have to be corrected at the end of the manufacturing process. Various types of errors of photolithographic masks and methods for their corrections are described in U.S. Provisional Patent Application 61/351,056, filed on Jun. 3, 2010, and U.S. Provisional Patent Application 61/363,352, filed on Jul. 12, 2010, which are incorporated herein by reference in their entirety.

Typically, the basis of photolithographic masks is an ultra-pure substrate of fused quartz or other low thermal expansion material which has on one surface a thin chromium layer or a layer of another non-light transparent material. The pattern elements of photolithographic masks are generated by a so-called pattern generator based on particle beams, predominantly electrons or a respective laser beam, which write the pattern elements in the absorbing material. In a subsequent etching process, the pattern elements are formed on the substrate of the photolithographic mask. FIG. 1 schematically illustrates a mask fabrication process.

The precise position of the pattern elements on the generated mask is measured using a registration metrology tool. When the photolithographic mask exceeds the maximum tolerable positioning error of the pattern elements, the mask has to be rewritten. During the rewriting process, it is at first tried to correct the positioning errors of the first writing process. However, this works only if the positioning errors are systematic. The writing time of a critical photolithographic mask may be very long and may reach a period of up to 20 hours. Thus, the repeated writing of photolithographic masks is an extremely time-consuming and expensive process.

In an alternative process, positioning errors of photolithographic masks can be minimized by the application of a so-called registration correction (RegC) process. As described in U.S. Provisional Patent Application 61/361,056, this process uses femtosecond light pulses of a laser system to locally change the density of the substrate of a photolithographic mask which results in a shift of the pattern placement on the substrate surface of the photolithographic mask.

In order to protect the structured absorbing layer, a pellicle is mounted on the surface of the photolithographic mask carrying the absorbing pattern elements. For critical masks, or more precisely of overlay-critical masks, the measurement of the position of the pattern elements has to be repeated in order to determine the influence of the pellicle on the positioning errors. This process is schematically represented in FIG. 1.

The generation of an integrated circuit on a wafer requires the successive application of several different photolithographic masks for the fabrication of the different layers or levels of the component. The plurality of photolithographic masks necessary for the generation of the integrated circuit is called a mask set. For a complex integrated circuit, the mask set may comprise 20 to 30 different photolithographic masks. At the end of the mask fabrication process, the complete mask set is transferred to the wafer processing site or to the wafer fabrication site.

At the wafer processing site, a projection device successively illuminates a wafer by means of the individual photolithographic masks of the mask set in order to transfer the pattern elements of the various masks to the respective photoresistive layer on the wafer. FIG. 2 schematically represents this process. By a lithographic process and a subsequent etching process the pattern elements of the photolithographic mask are copied to the wafer forming the respective layer of the integrated circuit. The overlap accuracy of the different photolithographic masks on the wafer is called overlay, and is determined by means of overlay targets also copied from the photolithographic mask to the wafer or to the photoresist on the wafer, respectively, using an overlay metrology system.

If the overlay error of successive masks exceeds a predetermined threshold, the projection device is readjusted, the illumination of the latest mask is repeated and the overlay error is again measured. When the overlay error still surmounts the overlay budget, the root cause of the error has to be analyzed and the overlay specification is tightened. The respective mask is sent back to the mask fabrication site for rewriting of its pattern elements. As already briefly mentioned, this repair or rewriting process is extremely time-consuming and significantly hampers the wafer processing at the wafer processing site.

At a wafer processing site, the overlay is presently determined at special AIM (advanced imaging metrology) overlay targets which are arranged at the four corners of the scribe line of the integrated circuit. The article “Meeting overlay requirements for future technology nodes with in-die overlay metrology”, by B. Schulz et al., Proc. SPIE Vol. 6518, 2007 describes that judging the quality of a photolithographic mask by the standard registration measurement in the scribe line is not at all representative of the placement of the structures in the die. This situation can only be improved when the specification of pattern placement errors of photolithographic masks is based on a higher sampling plan including representative structures and especially locations within the die. The authors of this article report also of measurements on the influence of the pellicle to the overlay error. They conclude that this contribution is in the range of 1 nm (3σ value), however, it was too small to be determined with the available methodology and the precision levels of the overlay metrology system.

With the extension of the 193 nm ArF (argon fluorine) lithography to the 32 nm technology node highest demands are made to the positioning errors of the photolithographic masks and the overlay accuracy on the wafer. For the 32 nm node, the overlay budget reduces to about 6 nm (3σ value) depending on the device or integrated circuit to be produced. Below the 32 nm node, so called double patterning technologies are applied which require overlay accuracies of below 2.5 nm for some schemes. Moreover, the applicant detected that the contribution of the mounting of the pellicle to the positioning error may be significantly larger than estimated in the above mentioned article. This error may reach a dimension of some nanometers, which may take up more than 50% of the overall overlay budget. This error significantly reduces the yield of the overall wafer fabrication process and can therefore not be tolerated. Furthermore, the situation is complicated as the influence of the pellicle mounting process can only be poorly corrected in advance due to its insufficient systematics.

It is therefore one object of the present invention to provide a method and an apparatus for correcting errors on a wafer illuminated by a photolithographic mask which at least partly avoid the problems discussed above.

SUMMARY

According to a first aspect of the invention, a method for correcting errors on a wafer processed by a photolithographic mask at a wafer processing site comprises measuring of errors on the wafer, and modifying a pattern placement on the photolithographic mask by locally applying femtosecond light pulses of a laser system to the photolithographic mask at the wafer processing site.

The defined method measures errors on a wafer generated at the illumination of the wafer with a photolithographic mask at the final wafer overlay at the wafer processing site or at the wafer fabrication site. Therefore, the inventive method takes all problems into account which have influenced the measured overlay errors on the wafer. Since the overlay budget will further shrink with future technology nodes, it will be mandatory to determine the overall error for the mask overlay. It will be more and more difficult to separate the various contributions of the overall overlay error and to separately correct them. For example, the inventive principle a priori considers the impact of the pellicle mounting process to the measured data. Furthermore, the problems of the projection device of the photolithographic illumination system are also automatically taken into account.

The inventive principle detects errors on the wafer generated by the illumination process of different photolithographic masks. A method known as registration correction (RegC) and described in U.S. Provisional Patent Application 61/351,056 allows the calculation of shifts or displacements of pattern elements, so that the errors detected on the wafer can be corrected by modifying the pattern placement on the respective photolithographic mask(s). For this purpose, at the wafer processing site, femtosecond light pulses of a laser system are applied in order to modify the density of the mask substrate which induces the required pattern placement shifts. By this process, the individual masks representing different layers of the integrated circuit can be directly aligned to each other. Hence, the defined method reduces the alignment errors of different masks resulting in the minimization of the overlay error. Thus, the inventive method avoids to a large extent the involved rewriting of already existing photolithographic masks.

In a further aspect, the errors on the wafer comprise pattern placement errors and/or critical dimension errors and/or overlay errors.

The inventive method is not restricted to the correction of overlay errors originating from pattern placement errors on the photolithographic mask and/or from alignment problems of the projection device used in the photolithographic illumination system. It can also be used to correct a variation of the optical transmission resulting in CD (critical dimension) errors across the wafer. Furthermore, the inventive method allows simultaneously correcting both types of errors.

According to another aspect, measuring of errors comprises measuring of errors in the active area of a chip (in-die).

As already mentioned above, the 32 nm technology node and future technology nodes will require the detection of the pattern placement not just in the scribe line at the four corners of the die, but at a regular grid on the die itself (in-die). The presented method supports the measurement of the positioning errors of the pattern elements in-die. In particular, an overlay metrology system is now available which enables the measurement of positioning errors in the sub-nanometer range, so that contributions to the overlay error can now be detected which have been out of reach up to now.

In a further aspect, measuring of errors comprises measuring at a developed photoresist layer on the wafer and/or on the wafer.

The measurement of overlay errors on a wafer can be performed at the developed photoresist on the wafer. Thus, when the detected errors are below the predetermined threshold, the processing of the wafer can be continued. If the detected errors exceed the tolerable level, the last illumination step can be repeated by removing of the photoresist from the wafer and dispensing a new layer of photoresist. Prior to the second illumination, the photolithographic mask is also corrected.

In another aspect, the photolithographic mask comprises a pellicle.

According to a further aspect, modifying a pattern placement on the photolithographic mask comprises modifying a pattern placement on and/or an optical transmission of the photolithographic mask by locally applying femtosecond light pulses of a laser system. In a further aspect, locally applying of femtosecond light pulses does not introduce a variation of the optical transmission across the photolithographic mask. According to still another aspect, locally applying of femtosecond light pulses corrects pattern placement errors and/or optical transmission errors of the photolithographic mask.

As already briefly mentioned above, the femtosecond light pulses of a laser system can write an arrangement of local density variations, called pixels, in a substrate of a photolithographic mask which shift pattern elements on the surface of the photolithographic mask to a predetermined position. The induced density variation of the substrate corrects pattern placement errors on the surface of the photolithographic mask, and thus minimizing the overlay error of the mask. On the other hand, an arrangement of pixels can be written in the mask substrate which corrects a variation of the optical transmission across the photolithographic mask, so that CD errors can be corrected without inducing a shift of the pattern elements on the surface of the substrate of the photolithographic mask. Moreover, an arrangement of pixels can be defined and written which corrects both, pattern placement errors and optical transmission errors.

In another aspect, locally applying femtosecond light pulses locally changes a density of a substrate of the photolithographic mask. According to a further aspect, the density of the substrate of the photolithographic mask is locally changed in a centre of the height of the substrate.

The writing of pixels in the centre of the mask substrate avoids a bending of the substrate which might introduce image defects resulting in further errors on the wafer illuminated with the respective photolithographic mask.

In still a further aspect, the photolithographic mask comprises a transmissive photolithographic mask and/or a reflective photolithographic mask and/or a template for the nanoimprint lithography.

The generation of integrated circuits on wafers, which rely on a plurality of any kind of masks, has the problem to align pattern elements of different masks. Thus, the inventive method can be used to solve or at least significantly reduce overlay errors occurring in these wafer fabrication processes.

According to a further aspect, an apparatus for correcting errors on a wafer processed by a photolithographic mask at a wafer processing site comprises at least one overlay metrology system adapted for measuring of errors on the wafer, at least one computing means adapted for calculating an arrangement of femtosecond light pulses for the photolithographic mask from measured error data, and at least one laser system adapted for modifying a pattern placement on the photolithographic mask by applying the arrangement of femtosecond light pulses on the photolithographic mask.

Further aspects of the invention are described in further dependent claims.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

In order to better understand the present invention and to appreciate its practical applications, the following Figures are provided and referenced hereafter. It should be noted that the Figures are given as examples only and in no way limit the scope of the invention.

FIG. 1 schematically represents a flow chart of a fabrication process of a set of photolithographic masks according to the prior art;

FIG. 2 schematically shows a flow chart of a use case of a set of photolithographic masks at a wafer processing site according to the prior art;

FIG. 3 schematically represents a block diagram of some of the major components of an apparatus used for measuring overlay errors on a wafer;

FIG. 4 schematically shows a block diagram of an apparatus used for correcting overlay errors in the substrate of a photolithographic mask;

FIG. 5 schematically represents a flow chart of a fabrication process of a set of photolithographic masks according to an embodiment of the inventive method;

FIG. 6 schematically shows a flow chart of a use case of a set of photolithographic masks at a wafer processing site according to an embodiment of the inventive method;

FIG. 7 schematically represents a displacement vector map measured at the scribe lines of dies; and

FIG. 8 schematically illustrates a displacement vector map measured at nodes of a regular grid, i.e. at the scribe lines of dies and in-die.

 DETAILED DESCRIPTION

In the following, the present invention will be more fully described hereinafter with reference to the accompanying Figures, in which exemplary embodiments of the invention are illustrated. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and will convey the scope of the invention to persons skilled in the art.

This section describes an embodiment of the inventive method. To illustrate the inventive principle, differences are highlighted in the fabrication of a set of photolithographic masks with respect to the fabrication according the prior art. Further, these differences are also exemplified for a use case of a mask set. The inventive method is explained for the utilization of transmissive photolithographic masks. However, the person skilled in the art will appreciate that this is just an example and that the above defined method can also be applied to reflective photolithographic masks. Moreover, the inventive method is also well suited to correct overlay errors of templates for the nanoimprint lithography at a wafer processing site or at a wafer fabrication site.

In the following, the term integrated circuit (IC) is used for all devices fabricated on semiconducting wafers as for example memory or logic components, MEMS (micro-electromechanical systems) including sensors, detectors and displays and PICs (photonic integrated circuits) including lasers and photodiodes.

The inventive method corrects errors detected on a wafer by applying femtosecond light pulses of a laser system to a photolithographic mask with which a wafer was illuminated.

For the correction feature of the present invention, the specification refers to U.S. Provisional Patent Application 61/363,352. This document describes in detail how pattern placement errors can be corrected by the writing of a respective arrangement of pixels in the substrate of photolithographic masks. Some of the problems of photolithographic masks and of templates for the nanoimprint lithography are also briefly discussed in the above mentioned document.

FIG. 1 outlines the fabrication process 100 for a mask set according to the prior art. The process begins at 105 with the writing of the pattern 115 of the first mask 110. Then, also at step 115, the excessive parts of the absorber layer are removed from the mask substrate, for example by etching. In the next step 120, the photolithographic mask is measured in order to determine the positioning errors of the mask pattern. At decision block 125, it is decided whether the positioning errors fulfil a predetermined specification. If this is correct, the pellicle is mounted on the mask in step 135. It is then decided at decision block 145 whether the mask is an overlay critical mask. If mask m is not an overlay critical mask, it is decided at decision block 150 whether mask m is the last mask to be processed. The fabrication process is complete and ends at step 180 when m=M, indicating that the last mask has been processed. If m is not equal to M, then m is incremented by 1 in step 140, and the process proceeds to step 115, where the next mask is processed. If mask m is overlay critical (decision block 145), the mask is again measured at step 155 to check the effect of the pellicle mounting on the positioning errors. When it is determined at decision block 165 that mask m does not fulfil the specification, at step 160, the pellicle is removed and the pattern is rewritten in a new mask. If mask m fulfils the specification, it is decided at decision block 175 whether mask m is the last mask to be processed. The fabrication process is complete and ends at step 180 when m=M, indicating that the last mask has been processed. If m is not equal to M, then m is incremented by 1 in step 170, and the process proceeds to step 115, where the next mask is processed.

When it is determined at decision block 125 that the positioning errors of mask m do not fulfil the predetermined specification, at step 130, the pattern placement errors are corrected by using a so called RegC (Registration Correction) process, which is described in detail in U.S. Provisional Patent Applications 61/351,056 and 61/363,352. If the positioning errors can not be reduced by a RegC process so that mask m meets the specification, the pattern is written on a new mask and the process proceeds to step 120 where the mask is measured.

The process of FIG. 1 is repeated until all M masks of the mask set are fabricated (decision blocks 150 and 175). The complete mask set is then supplied to the wafer processing site at block 180.

FIG. 2 briefly illustrates some steps of a mask illumination process for the fabrication of ICs at a wafer processing site. The process 200 begins at 205 with the illumination of a wafer (step 215) with the first mask (step 210) of the mask set. The photoresist on the wafer is developed and the wafer is processed, for example by performing of an etching process. Then a second (generally mth) layer of photoresist is arranged on the wafer (not illustrated in FIG. 2). At step 220, the wafer is illuminated with the second, or generally with the (m+1)th mask. The overlay errors between the first and the second masks, or in general between the mth and the (m+1)th masks on the wafer are measured at step 230. If it is decided at decision block 240 that the overlay error is below the predetermined overlay budget, it is at decision block 265 checked whether the IC to be fabricated will operate according to its specification. If this is correct, the process proceeds via decision block 255 and step 235 to block 220 where the wafer is illuminated with the next (third or (m+2)th) mask. When it is determined at decision block 255 that m reaches M which is the number of masks in the respective mask set, the process ends at block 270.

If it is decided at decision block 265 that the IC will not operate according to its specification, the root cause of the problem is analyzed at block 280 and the positioning specification for mask m+1 is tightened. In step 290, a new mask m+1 is then written at the mask processing site. The process ends at block 270. Then the new mask m+1 is supplied from the mask fabrication site to the wafer processing site, the process begins again at block 205 of FIG. 2.

When it is decided at decision block 240 that the overlay error does not meet the specification, the projection device of the illumination system is readjusted at block 245. Then, at step 260, the overlay error measurement is repeated. If it is determined at decision block 275 that the overlay error does still not fulfil the predetermined error budget, the process proceeds to step 280 and the cause of the problem is analyzed. In case the overlay error meets the specification, it is at decision block 285 determined whether the IC to be fabricated will operate according to its specification. If this is true, the process proceeds via decision block 295 across step 225 to block 220 where the wafer is illuminated with the next (third or (m+2)th) mask of the mask set. Alternatively, when the illuminated mask is the last mask of the mask set (m=M), the process ends at block 270.

FIG. 3 shows a functional sketch of a registration metrology tool 300 with which pattern placement and overlay errors can be measured. A photolithographic mask 310 is supported by the high precision stage 320. The stage 320 is actively controlled in all six degrees of freedom and is the only moving part in the metrology system. As a light source an excimer laser 330 is used emitting light in the DUV (deep ultraviolet) wavelength range, at approximately 193 nm. This means that the inspection and the illumination of the photolithographic mask 310 occur at the same wavelength, as most masks are presently illuminated with a 193 nm light source. Hence, the registration and/or overlay metrology system 300 takes the effect of material properties properly into account.

The imaging objective 340 has a numerical aperture (NA) of 0.6, but can be extended to a higher NA in order to gain even more resolving power. The short wavelength of the laser system 330 significantly improves the resolution, and at the same time permits a moderate NA, which is beneficial for the CD (critical dimension) metrology and enables a pellicle compatible free working distance of about 7.5 mm. The imaging objective 340 is firmly fixed to the optical tower and is unmovable. Focusing of the laser beam onto the photolithographic mask 310 is done by a stage movement in z direction.

A CCD (charge-coupled device) camera 350 is used as a detector device which measures the light reflected from the photolithographic mask 310. The CCD camera 350 sends its signal to the signal processing unit 355 which calculates an image of the signal detected by the CCD camera 350.

A computer system 360 can display the image calculated by the signal processing unit 355 and may store the measured data. Further, the computer system 360 may contain algorithms, realized in hardware, software or both, which allow to extract control signals from the experimental data. The control signals may control the writing of an arrangement of pixels in the substrate of the photolithographic mask 310 by a second laser system in order to correct the pattern placement errors of photolithographic mask 310 (cf. FIG. 4 below). Further, the computer system 360 may control the laser source 330 and/or the high-precision stage 320 and/or the objective 340 and/or the CCD camera 350 and/or the AF system 370.

The surface of the photolithographic mask 310 may be slightly tilted, and in addition the bending of the mask 310 under its own weight leads to a variation of the best focal position. Therefore, the registration metrology tool 300 has an autofocus (AF) system 370 based on a tilted grating (not shown in FIG. 3) which supports the measurement process. The tilted mirrors 390 and the partially transmitting mirrors 395 direct the laser beam into the imaging objective 340.

Furthermore, the registration metrology tool 300 comprises an auxiliary optical system 380 for a coarse alignment of the pattern placement elements on the photolithographic mask 310.

FIG. 4 depicts a schematic block diagram of an apparatus 400 which can be used to correct errors on wafers by modifying the substrate of a photolithographic mask. Further, the apparatus 400 is also able to correct errors of templates used in the nanoimprint lithography. The apparatus 400 comprises a chuck 420 which may be movable in three dimensions. The photolithographic mask 410 or a template for the nanoimprint technique may be fixed to the chuck 420 by using various techniques such as, for example, clamping.

The apparatus 400 includes a pulse laser source 430 which produces a beam or a light beam 435 of pulses or light pulses. The laser source 430 generates light pulses of variable duration. The adjustable range of several import parameters of the laser source 430 is summarized in the following table. Table 1 represents an overview of laser beam parameters of a frequency-doubled Nd-YAG laser system which can be used in an embodiment of the inventive method.

TABLE 1 Numerical values of selected laser beam parameters for a Nd-YAG laser system Overview Parameter Numerical value Unit Pulse energy 0.05-5   μJ Pulse length 0.05-100  ps Repetition rate    1-10 000 kHz Pulse density    1 000-10 000 000 mm−2 NA (numerical aperture) 0.1-0.9 Wavelength 532 nm

In an alternative embodiment of the laser system the light pulses may be generated by a Ti:Sapphire laser operating at a wavelength of 800 nm. However, the correction of pattern placement errors is not limited to these laser types, principally all laser types may be used having a photon energy which is smaller than the band gap to the substrate of the photolithographic mask 410 and which are able to generate pulses with durations in the femtosecond range.

The steering mirror 490 directs the pulsed laser beam 435 into the focusing objective 440. The objective 440 focuses the pulsed laser beam 435 onto the photolithographic mask 410. The NA (numerical aperture) of the applied objectives depends on the predetermined spot size of the focal point and the position of the focal point within the photolithographic mask 410 or of the template. As indicated in table 1, the NA of the objective 440 may be up to 0.9 which results in a focal point spot diameter of essentially 1 μm and a maximum intensity of essentially 1020 W/cm2.

The apparatus 400 also includes a controller 480 and a computer system 460 which manage the translations of the two-axis positioning stage of the sample holder 420 in the plane perpendicular to the laser beam (x and y directions). The controller 480 and the computer system 460 also control the translation of the objective 440 perpendicular to the plane of the chuck 420 (z direction) via the one-axis positioning stage 450 to which the objective 440 is fixed. It should be noted that in other embodiments of the apparatus 400 the chuck 420 may be equipped with a three-axis positioning system in order to move the photolithographic mask 410 to the target location and the objective 440 may be fixed, or the chuck 420 may be fixed and the objective 440 may be moveable in three dimensions. Although not economical, it is also conceivable to equip both the objective 440 and the chuck 420 with three-axis positioning systems. It should be noted that manual positioning stages can also be used for the movement of the mask 410 to the target location of the pulsed laser beam 435 in x, y and z directions and/or the objective 440 may have manual positioning stages for a movement in three dimensions.

The computer system 460 may be a microprocessor, a general purpose processor, a special purpose processor, a CPU (central processing unit), a GPU (graphic processing unit), or the like. It may be arranged in the controller 480, or may be a separate unit such as a PC (personal computer), a workstation, a mainframe, etc. The computer 460 may further comprise I/O (input/output) units like a keyboard, a touchpad, a mouse, a video/graphic display, a printer, etc. In addition, the computer system 460 may also comprise a volatile and/or a non-volatile memory. The computer system 460 may be realized in hardware, software, firmware, or any combination thereof. Moreover, the computer 460 may control the laser source 430 (not indicated in FIG. 4). The computer systems 360 of FIGS. 3 and 460 of FIG. 4 may be connected to exchange data. Moreover, the computer systems 360 and 460 may be combined in a single computer system.

Further, the apparatus 400 may also provide a viewing system including a CCD (charge-coupled device) camera 465 which receives light from an illumination source arranged in the chuck 420 via the dichroic mirror 445. The viewing system facilitates navigation of the photolithographic mask 410 to the target position. Further, the viewing system may also be used to observe the formation of a modified area on the substrate material of the mask 410 by the pulsed laser beam 435 of the light source 430.

FIG. 5 schematically depicts an example of a fabrication process 500 of photolithographic masks of a mask set according to the inventive method. The process 500 begins at 505 with the first mask in the mask set (step 510). As already briefly explained in the second section of this specification, a pattern of absorbing elements is written on an absorbing layer on the substrate of a photolithographic mask with a pattern generator. In a subsequent etching process, the absorbing pattern elements are formed from the absorbing material (box 515). A material often used for the absorbing layer on photolithographic masks is chromium. Tungsten can be used as another absorber material on the surface of mask substrates. The usage of the inventive method is not restricted to these materials; rather any absorber material can be used.

The positions of the generated absorbing pattern elements are measured with the registration metrology system of FIG. 3 in order to determine whether the pattern writing process was successful, i.e. the pattern elements have their predetermined size and form and are at the desired positions (box 520). If the determined positioning errors exceed a predetermined level (decision box 525), the positions of the pattern elements are modified by writing of an arrangement of pixels into the substrate of the photolithographic mask using the laser source 430 of the apparatus 400 of FIG. 4 (box 530 of FIG. 5). The arrangement of pixels locally changes the density of the mask substrate and thus shifts the pattern elements on the mask surface to the predetermined positions. Then, it is measured whether the repair of the mask was successful (box 520). If the measured positioning error is now below the predetermined threshold (decision box 525), the pellicle is mounted on the surface of the photolithographic mask carrying the absorbing pattern elements in order to protect them from being damaged (box 535). The next mask is processed (boxes 545, 520). When all masks of the mask set are processed according to this scheme (box 540), the fabricated mask set is ready for the delivery to the wafer processing site (box 550).

As can be seen from FIG. 5, an embodiment of the mask fabrication process according to the inventive method largely avoids rewriting of photolithographic masks. If the positioning errors of a mask exceed the tolerable level, the respective mask is corrected by using the RegC process.

The mask fabrication process of FIG. 5 abandons the measurement of positioning errors for overlay-critical photolithographic masks after mounting of the pellicle. This is the decisive distinction between the mask fabrication processes according to FIGS. 1 and 5.

FIG. 6 schematically illustrates a use case of a set of photolithographic masks at the wafer processing site according to an embodiment of the inventive method. The process begins (box 605) by illuminating of a wafer with a first mask (box 610) using the projection device of the photolithographic illumination system (box 615). The first mask may be the first mask of a mask set, or in the general case, it may be any mask, but the last one of the mask set. The photoresist is developed, and the wafer is processed to generate a first layer, or generally an mth layer, respectively, of an integrated circuit. Then a new photoresist layer is dispensed on the wafer (not shown in FIG. 6).

In the next step (box 620), similar to the first photolithographic mask, a second photolithographic mask is aligned with respect to alignment marks on the wafer. Then the second mask, or generally the (m+1)th mask, is illuminated similar to the first mask in order to transfer the structure elements for the second layer, or general (m+1)th, layer of the integrated circuit from the photolithographic mask to the wafer. The photoresist is then developed.

The photolithographic masks have overlay targets which are used to determine the overlay of the second mask with respect to the first photolithographic mask. The standard overlay targets are BiB (box-in-box) targets, which allow the detection of shifts or of displacements of the second mask relative to the first mask. Since the BiB targets have a rather coarse structure, they are now more and more replaced by AIM (advanced imaging metrology) and micro AIM overlay targets.

Up to now, the overlay targets are positioned in the scribe lines of the integrated circuits. FIG. 7 schematically presents a displacement vector map or a displacement vector field measured at overlay targets arranged in scribe lines of integrated circuits. The arrow tips of the individual vectors of the displacement vector field indicate the directions of the displacement of the respective positions of the second mask with respect to the first photolithographic mask. The lengths of the vectors denote the magnitude of the shift of the respective positions of the second mask relative to the first mask. It can be seen from FIG. 7 that the restriction of the placement of the overlay targets to the scribe lines results in an irregular distribution of the overlay measuring points across the wafer.

With shrinking sizes of the structures of integrated circuits and, on the other hand, increasing sizes of integrated circuits, it will no longer be sufficient to determine the overlay at the scribe line, but not on the die on the integrated circuit itself (in-die measurement). FIG. 8 schematically shows a grid of regular nodes of overlay measuring points where the nodes are arranged in the scribe lines as well as on the die area of the integrated circuit itself. This dense grid of overlay measuring points allows the determination of the overlay error with a high spatial resolution. A dense grid of overlay measuring points is a prerequisite for a beneficial application of the inventive method.

Now back to FIG. 6, the overlay error of the second ((m+1)th) mask relative to the first (mth) mask can be measured by using the overlay metrology system 300 of FIG. 3 in order to determine a displacement vector field similar to FIG. 8 (box 630). When the measured overlay error is below a predetermined threshold (box 640) and the fabricated integrated circuit is at the end working properly (box 665), the first and the second masks can be used for the fabrication of the desired integrated circuit. If the wafer has not been illuminated with the last mask (box 655), the next mask is fetched (box 635) and the wafer is prepared for illumination with the next mask (box 620). If the wafer has been illuminated with the last mask (box 635), the process 600 ends (box 670).

If the measured overlay error does not fulfil the predetermined specification (box 640), the projection device is readjusted in order to reduce the overlay error (box 645). After removing the photoresist from the wafer, a new layer of photoresist material is dispensed on the wafer (not shown in FIG. 6). Then, the overlay measurement is repeated (box 660). When the measured overlay error fulfils the requirement with respect to the predetermined overlay error (box 675) and the fabricated integrated circuit works properly (box 685), the first and the second masks are ready for being used for the production of the respective integrated circuit. If the last mask has been processed (box 695), the process 600 ends (box 670).

In case the overlay error is still too high (box 675), the overlay errors are analyzed based on measured displacement vectors as indicated in FIG. 8 in order to determine an arrangement of pixels for the second photolithographic mask (box 680). The writing of the arrangement of pixels with the laser source 435 of the apparatus 400 of FIG. 4 in the substrate of the second photolithographic mask shifts the pattern elements on the surface of the second photolithographic (box 690).

The writing of pixels can be limited to the active area of the photolithographic mask. The correction of pattern placement errors in the active area of the photolithographic masks is very effective, since the correcting pixels can be placed close to the error positions. On the other hand, when the writing of pixels is not restricted to the active area, the flexibility of the error correction process is enhanced. If the writing of the pixels can be limited to the non-active area, the introduction of new errors in the active area of the substrate of the photolithographic mask by the pixel writing process can be avoided. Since the distance between the pattern placement error and the correcting pixels may be large, the effectiveness of the correction process may be lower. This may partly be compensated as the writing of pixels does not have to consider a variation of the optical transmission.

After correcting the second photolithographic mask, the wafer is prepared for a second illumination with the corrected second mask as described above. At the second illumination of the corrected second mask, its overlay error with respect to the first photolithographic mask is significantly reduced, so that the mask combination fulfils the predetermined overlay error.

In contrast to FIG. 2, the use case of a set of photolithographic masks according to FIG. 6 eliminates the necessity to send defective photolithographic masks from the wafer processing site to the mask fabrication site. Moreover, since the same metrology tool is used for the measurement of the overlay error and the corrected photolithographic mask, tool related impacts on the measured data are avoided.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, elements of one or more implementations may be combined, deleted, modified, or supplemented to form further implementations. As yet another example, additional steps may be provided, or steps may be eliminated, from the described process flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

Claims

1. A method for correcting errors on a wafer processed by a photolithographic mask at a wafer processing site, the method comprising:

a. measuring errors on the wafer; and
b. modifying a pattern placement on the photolithographic mask by locally applying femtosecond light pulses of a laser system to the photolithographic mask at the wafer processing site.

2. The method according to claim 1, wherein the errors on the wafer comprise at least one of pattern placement errors, critical dimension errors, or overlay errors.

3. The method according to claim 1, wherein measuring errors comprises measuring errors in the active area of a chip (in-die).

4. The method according to claim 1, wherein measuring errors comprises measuring at a developed photoresist layer on the wafer and/or on the wafer.

5. The method according to claim 1, wherein the photolithographic mask comprises a pellicle.

6. The method according to claim 1, wherein modifying a pattern placement on the photolithographic mask comprises modifying a pattern placement on and/or an optical transmission of the photolithographic mask by locally applying femtosecond light pulses of a laser system.

7. The method according to claim 1, wherein locally applying femtosecond light pulses does not introduce a variation of the optical transmission across the photolithographic mask.

8. The method according to claim 1, wherein locally applying femtosecond light pulses corrects pattern placement errors and/or optical transmission errors of the photolithographic mask.

9. The method according to claim 1, wherein locally applying femtosecond light pulses locally changes a density of a substrate of the photolithographic mask.

10. The method according to claim 9, wherein the density of the substrate of the photolithographic mask is locally changed in a centre of the height of the substrate.

11. The method according to claim 1, wherein the photolithographic mask comprises at least one of a transmissive photolithographic mask, a reflective photolithographic mask, or a template for a nanoimprint lithography.

12. An apparatus for correcting errors on a wafer processed by a photolithographic mask at a wafer processing site, comprising:

a. at least one overlay metrology system adapted for measuring errors on the wafer;
b. at least one computing means adapted for calculating an arrangement of femtosecond light pulses for the photolithographic mask from measured error data; and
c. at least one laser system adapted for modifying a pattern placement on the photolithographic mask by applying the arrangement of femtosecond light pulses on the photolithographic mask.

13. The apparatus according to claim 12, wherein the apparatus is configured to measure at least one of pattern placement errors, critical dimension errors, or overlay errors on the wafer.

14. The apparatus according to claim 12, wherein the apparatus is configured to measure errors in the active area of a chip (in-die).

15. The apparatus according to claim 12, wherein the apparatus is configured to measure errors at a developed photoresist layer on the wafer and/or on the wafer.

16. The apparatus according to claim 12, wherein applying the arrangement of femtosecond light pulses on the photolithographic mask corrects pattern placement errors and/or optical transmission errors of the photolithographic mask.

17. The apparatus according to claim 12, wherein applying the arrangement of femtosecond light pulses on the photolithographic mask locally changes a density of a substrate of the photolithographic mask.

18. The apparatus according to claim 17, wherein the density of the substrate of the photolithographic mask is locally changed in a centre of the height of the substrate.

19. The apparatus according to claim 12, wherein the photolithographic mask comprises at least one of a transmissive photolithographic mask, a reflective photolithographic mask, or a template for a nanoimprint lithography.

20. The apparatus according to claim 12, wherein the overlay metrology system comprises an ultra-precision stage, at least one laser source and at least one charge-coupled device camera operating in the ultraviolet wavelength range.

Patent History
Publication number: 20120154773
Type: Application
Filed: Dec 2, 2011
Publication Date: Jun 21, 2012
Applicant:
Inventor: Dirk Beyer (Weimar)
Application Number: 13/310,071
Classifications
Current U.S. Class: Distortion Introducing Or Rectifying (355/52)
International Classification: G03B 27/68 (20060101);