METHOD AND SYSTEM FOR TESTING AN ELECTRIC CIRCUIT

Abstract

Embodiments include a method and system for testing an electric circuit. A carrier signal of a first frequency is modulated with a multi-tone signal to generate a test signal. The test signal is applied to an input of a circuit under test (CUT). A crest factor of an output signal that corresponds to the test signal received at an output of the CUT is measured. A crest factor differential between the measured crest factor and a reference crest factor is determined. If the crest factor differential exceeds a threshold value, the CUT is determined to be defective.

Description

FIELD OF THE DISCLOSURE

Embodiments disclosed herein relate generally to testing an electric circuit, and in particular to an electric circuit testing technique that uses a multi-tone test signal.

BACKGROUND

A Device Interface Board (DIB) (sometimes referred to as a “load board”) is used to test radio frequency integrated circuits (RFIC). A DIB can include hundreds of mixed-signal and RF circuits with hundreds of active and passive components. Many of the RF circuits may be embedded in the layers of the DIB.

Before a DIB can be used to verify an RFIC, the electric circuits in the DIB itself must first be verified. Typically, in order to test a DIB, tester specific code is manually developed for testing the various electric circuits of the DIB. This process can take days, or months, for complex DIBs.

Similarly, the drive for smaller and smaller electronic devices has led to increased density of surface-mounted electric components on a printed circuit board (PCB), as well as the use of electric components embedded in a PCB. Testing, verifying, or diagnosing the electric circuits on, or embedded in, a PCB is typically either done manually, or via automated test equipment (ATE). Manual verification of electric circuits can be time-consuming and costly. The use of ATE eliminates much of the manual effort, but in turn, the ATE must be designed or programmed for a particular PCB, which is also time-consuming and costly.

Accordingly, there is a need for an efficient technique for testing electric circuits that can be applied to a variety of different electric circuits without the need to design or program ATE for each electric circuit.

SUMMARY

Embodiments disclosed herein relate to testing or validation of electric circuits. In one embodiment, a circuit under test (CUT) has an input port and an output port. A carrier signal at a first frequency is modulated with a multi-tone signal to generate a test signal. The test signal is applied, or otherwise provided, to the input port of the CUT. An output signal that corresponds to the input signal is received at the output port. A characteristic of the output signal is measured and compared to a reference characteristic, to determine a characteristic differential between the measured characteristic and the reference characteristic. The characteristic differential is compared to a predetermined threshold, and if the characteristic differential exceeds the predetermined threshold value, the CUT is determined to have a fault.

In one embodiment the characteristic is a crest factor characteristic. A reference crest factor is determined by applying a first test signal to the input port of a fault-free circuit that is identical to the CUT. The corresponding output signal is received, and the reference crest factor is determined. The first test signal is then provided to the CUT. A crest factor of the corresponding output signal is determined, and the measured crest factor is compared to the reference crest factor to determine a crest factor differential. If the crest factor differential exceeds a threshold value, the CUT is determined to contain a fault.

In one embodiment, the test signal comprises the same frequency as the carrier signal. The test signal comprises a plurality of different tones. In one embodiment, the test signal comprises in excess of two hundred tones.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a block diagram illustrating a process for testing an electric circuit according to one embodiment;

FIG. 2 is a graph illustrating exemplary output voltages of two output signals received from two electric circuits after application of a test signal;

FIG. 3A illustrates an exemplary fault-free circuit;

FIG. 3B illustrates an exemplary circuit under test (CUT) that has a “near open” defect but is otherwise identical to the circuit shown in FIG. 3A;

FIG. 4 is a table containing crest factor differentials identifying the difference between a reference crest factor and a measured crest factor of output signals that correspond to various test signals;

FIG. 5 is a graph illustrating crest factor differentials shown in FIG. 4; and

FIG. 6 is a graph illustrating a crest factor differential for various multi-tone test signals having a 1 GHz frequency, for four defective electric circuits which were identical other than the amount of metal missing from a resistive trace.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

Embodiments herein relate to testing and validation of electric circuits. A radio frequency (RF) carrier signal is modulated with a multi-tone signal to generate a test signal. The test signal is applied to an input port of a circuit under test (CUT). A characteristic, such as a crest factor, of the corresponding output signal is determined. The measured crest factor is compared to a reference crest factor, and if the crest factor differential exceeds a predetermined threshold value, the CUT is determined to contain a fault. The predetermined threshold value may simply be any crest factor differential greater than 0, or may be determined empirically.

Embodiments herein have applicability in testing a wide range of electric circuits, including circuits in printed circuit boards (PCBs), whether embedded within the PCBs or mounted on a surface of the PCBs; circuits implemented in low temperature co-fired ceramic (LTCC) multi-layer technology; and circuits implemented in integrated circuits.

FIG. 1 is a block diagram illustrating a process for testing an electric circuit according to one embodiment. A carrier signal generator 10 generates an RF carrier signal 12 at a desired first frequency. The desired first frequency may be based on attributes or characteristics of one or more CUTs. For example, an embedded passive copper trace will typically have certain design values such as length, height, and width. A copper trace may be modeled as a transmission line. For a signal to propagate in a transmission line and reach the output terminal, the length of the transmission line should typically be at least one fourth of the wavelength of the signal. Hence, the length of the copper trace may be used to determine the desired first frequency for a particular CUT. In one embodiment, this calculation may be performed for all CUTs for a particular board, such as a device interface board being tested, and an average length of such CUTs may be used to determine a desired first frequency.

A waveform generator 14, such as an arbitrary waveform generator (AWG), generates a multi-tone signal 16 comprising a plurality of tones. The multi-tone signal 16 is preferably at a frequency equal to the first frequency.

Preferably, the multi-tone signal 16 is generated with a random phase shift between the individual tones. The random phase shift may be obtained over a Gaussian distribution. The use of a Gaussian distribution enables the adjustment of the spacing between the tones. In one embodiment, additive white Gaussian noise may be added to the multi-tone signal 16 to replicate the testing environment for device-level testing.

The RF carrier signal 12 and the multi-tone signal 16 are modulated by a modulator 18, which generates a test signal 20 and provides the test signal 20 toward a CUT 24. The test signal 20 is preferably at a frequency equal to the first frequency. The test signal is provided, or otherwise applied, to an input port 22 of the CUT 24. The CUT 24 can comprise any RF circuitry, including, for example, a circuit embedded in a PCB, a circuit comprising surface-mount components, a circuit comprising a combination of surface-mount components and components embedded in a PCB, a circuit packaged in an LTCC multi-layer technology, a circuit implemented in an integrated circuit, or the like.

An output signal 26 that corresponds to the test signal 20 is received at an output port 28 of the CUT 24. A characteristic of the output signal 26 is measured by a characteristic measurement module 30. In one embodiment, the characteristic is a measured crest factor of the output signal 26. Any suitable crest factor measurement modules may be used, however, one suitable crest factor measurement module is the Analog Devices 450 MHz to 6 GHz crest factor detector (part number ADL5502) available from Analog Devices, Inc., 3 Technology Way, Norwood, Mass. 02062.

The measured crest factor 32 is provided to a comparator 34. The comparator 34 compares the measured crest factor 32 to a reference crest factor 36 to determine a crest factor differential 38. If the crest factor differential 38 exceeds a predetermined threshold value, it is determined that the CUT 24 contains a fault. An output module may then generate a signal indicating that the CUT 24 is defective.

In one embodiment, the reference crest factor 36 is generated by applying the test signal 20 to a fault-free circuit that contains the same components as the CUT 24, and is thus otherwise identical to the CUT 24. The crest factor of the output signal 26 from the fault-free circuit is then determined, and is saved as the reference crest factor 36 for comparison to a measured crest factor 32.

FIG. 2 is a graph illustrating exemplary output voltages of two output signals received from two electric circuits after application of a test signal. Output voltage 40 is the output voltage of an output signal received from a fault-free first electric circuit. Output voltage 42 is the output voltage of an output signal 26 received from a second electric circuit that is identical to the first electric circuit except that the second electric circuit contains a “near open” defect. As illustrated, the phase of the output voltage 42 differs from the phase of the output voltage 40, and thus provides a mechanism for determining defects in an electric circuit. The phase difference between the output voltage 42 and the output voltage 40 results in a difference in the root-mean-square (RMS) values of the output voltage 42 and the output voltage 40. FIG. 2 illustrates the phase shift of an output voltage associated with a single tone. The extent of phase shift caused by a defective electric circuit may differ at different frequencies. Thus, use of a multi-tone signal 16 comprising a plurality of tones enables the determination of a cumulative phase shift difference associated with a plurality of different tones. This cumulative phase shift difference results in a significant difference in crest factor between a reference multi-tone output signal 26 received from a fault-free electric circuit and a multi-tone output signal 26 received from an electric circuit having a fault.

In one embodiment, the multi-tone signal 16 consists of N tones of sinusoidal waves, each separated by an angular frequency (change in phase). The phases for the N tones may be generated over a Gaussian distribution in a random fashion. Each individual tone is represented by the product of its amplitude (a_k) and angular frequency (ω). The angular frequency is represented as a complex number. The multi-tone signal 16 in complex form is mathematically represented by the following equation:

$\begin{array}{cc}a\left(t\right)\sum _{k=0}^{N-1}a_k·{}^{jk\mathrm{\Delta \omega }t}& \left(1\right)\end{array}$

wherein the multi-tone signal 16 is denoted by a(t). The first tone is considered the fundamental tone with angular frequency ω₀, and the change in angular frequency is Δω=2π/T. a(t) is periodic with period T. The complex part is converted to real and the sine of the function is reduced to zero. The multi-tone signal 16 may then be represented by the following equation:

$\begin{array}{cc}a\left(t\right)=\sum _{k=0}^{N-1}a_k\cos \left({\omega }_0+k\mathrm{\Delta \omega }\right)t& \left(2\right)\end{array}$

The crest factor of a signal may be determined in accordance with the following:

$\begin{array}{cc}\mathrm{CF}=\frac{\mathrm{Vpeak}}{\mathrm{Vrms}}& \left(3\right)\\ V_{\mathrm{peak}}={\max }_t\left\{a\left(t\right)\right\}& \left(4\right)\\ V_{rms}=\sqrt{\underset{x\to N}{\lim }\frac{1}{2x}{\int }_0^Na^2\left(t\right)t}& \left(5\right)\end{array}$

Interested readers can obtain additional information regarding crest factors of a multi-tone signal and measurement thereof in the publication “Multitone Signals with Low Crest Factor,” by Mathias Friese, IEEE Transactions on Communications, Vol. 45, No. 10, October 1997, which is hereby incorporated herein by reference in its entirety.

FIG. 3A illustrates an exemplary fault-free circuit 43, which includes a passive metal trace 44. FIG. 3B illustrates a CUT 24 that contains a near open defect but is otherwise identical to the fault-free circuit 43 illustrated in FIG. 3A. The near open defect is modeled as depicted by components 45, in essence a passive metal trace having a certain resistance (i.e, 50 ohms in this example). The CUT 24 was tested with a number of test signals 20, each having a different carrier frequency and a different number of tones. The crest factors of the corresponding output signals 26 were then measured.

FIG. 4 illustrates a table 46 that contains crest factor differentials 38 identifying the difference between a reference crest factor 36 obtained from the circuit 43 illustrated in FIG. 3A and a measured crest factor 32 of output signals 26 that correspond to various test signals 20. Each of columns 50A-50E relates to a test signal 20 of a particular frequency. Rows 52A-52G relate to test signals 20 with different numbers of tones. For example, cell 54A indicates a crest factor differential 38 of 2.3224 dB. This was determined by first applying a one-hundred-tone test signal 20 having a frequency of 1 GHz to an input port of the fault-free circuit 43 as illustrated in FIG. 3A, and measuring the crest factor of the output signal received from the circuit 43 to determine a reference crest factor 36. An identical one-hundred-tone test signal 20 having a frequency of 1 GHz was then applied to the CUT 24 illustrated in FIG. 3B, and the crest factor of the corresponding output signal 26 was measured. The cell 54A indicates that the crest factor differential 38 between the measured crest factor 32 of the output signal 26 from the defective CUT 24 and the reference crest factor 36 was 2.3224 dB. The other cells in the table 46 illustrate other exemplary crest factor differentials 38 using test signals 20 at various frequencies and with various numbers of tones.

FIG. 5 is a graph illustrating the crest factor differentials 38 in dBs contained in the table 46 between reference crest factors 36 and measured crest factors 32 at various frequencies and numbers of tones.

FIG. 6 is a graph illustrating a crest factor differential 38 for various multi-tone test signals 20 having a 1 GHz frequency, for four defective electric circuits which are identical except for the amount of metal missing from a resistive trace. Curve 56 illustrates crest factor differentials 38 between reference crest factors 36 and measured crest factors 32 based on various 1 GHz multi-tone test signals 20 applied to an electric circuit where 90% of the metal in a resistive trace was removed. Curve 58 illustrates crest factor differentials 38 between reference crest factors 36 and measured crest factors 32 based on various 1 GHz multi-tone test signals 20 applied to an electric circuit where 50% of the metal in the resistive trace was removed. Curve 60 illustrates crest factor differentials 38 between reference crest factors 36 and measured crest factors 32 based on various 1 GHz multi-tone test signals 20 applied to an electric circuit where 20% of the metal in the resistive trace was removed. Curve 62 illustrates crest factor differentials 38 between reference crest factors 36 and measured crest factors 32 based on various 1 GHz multi-tone test signals 20 applied to an electric circuit where 10% of the metal in the resistive trace was removed.

The present embodiments have applicability in the testing or validation of a wide range of electric circuits and eliminate the need to develop special-purpose testing software for each CUT.

Claims

1. A method for testing an electric circuit, comprising:

modulating a carrier signal of a first frequency with a multi-tone signal to generate a test signal;

applying the test signal to an input of the electric circuit;

determining a crest factor of an output signal that corresponds to the test signal received at an output of the electric circuit; and

determining a crest factor differential between the crest factor and a reference crest factor.

2. The method of claim 1, further comprising:

comparing the crest factor differential to a threshold value; and

identifying the electric circuit as defective based on the comparison.

3. The method of claim 1, wherein the reference crest factor is determined by:

applying the test signal to an input of a fault-free electric circuit; and

determining the reference crest factor of an output signal that corresponds to the test signal received at an output of the fault-free electric circuit.

4. The method of claim 1, wherein the test signal has a frequency equal to the first frequency.

5. The method of claim 4, wherein the multi-tone signal has a frequency equal to the first frequency.

6. The method of claim 1, wherein the electric circuit comprises an electric circuit embedded in a printed circuit board (PCB).

7. The method of claim 6, wherein the electric circuit further comprises at least one surface-mounted component mounted to a surface of the PCB.

8. The method of claim 1, wherein the electric circuit comprises an electric circuit in an integrated circuit.

9. The method of claim 1, wherein the electric circuit comprises an electric circuit implemented in low temperature co-fired ceramic (LTCC) multi-layer technology.

10. The method of claim 1, wherein the multi-tone signal comprises in excess of one hundred tones.

11. A method for testing an electric circuit, comprising:

applying a test signal of a first frequency comprising a carrier reference signal modulated by a multi-tone signal to an input of the electric circuit;

determining a measured characteristic of an output signal received at an output of the electric circuit in response to the test signal; and

determining whether a characteristic differential between the measured characteristic and a reference characteristic exceeds a threshold value.

12. The method of claim 11, wherein the measured characteristic comprises a crest factor of the output signal.

13. The method of claim 12, wherein the carrier reference signal has a frequency equal to the first frequency.

14. The method of claim 13, wherein the multi-tone signal has a frequency equal to the first frequency.

15. The method of claim 11, wherein the electric circuit comprises an electric circuit embedded in a printed circuit board (PCB).

16. A system for testing an electric circuit, comprising:

a carrier signal generator adapted to generate a carrier signal at a first frequency;

a waveform generator adapted to generate a multi-tone signal;

a modulator adapted to modulate the carrier signal with the multi-tone signal to generate a test signal and provide the test signal toward a circuit under test (CUT);

a characteristic measurement module adapted to determine a crest factor of an output signal from the circuit under test; and

a comparator adapted to determine a crest factor differential between the crest factor and a reference crest factor.

17. The system of claim 16, further comprising:

an output module adapted to generate a signal indicating that the electric circuit is defective if the crest factor differential exceeds a threshold value.

18. The system of claim 16, wherein the test signal has a frequency equal to the first frequency.

19. The system of claim 18, wherein the multi-tone signal has a frequency equal to the first frequency.