Measurement Or Control Of Test Condition Patents (Class 324/750.01)
  • Patent number: 10884049
    Abstract: Detection of faults in an electrical power distribution network that includes measuring current flowing through a recloser in a feeder line, detecting a fault current indicating a fault is present in the feeder line, and opening a switch in the recloser in response to detecting the fault current. A first pulse having a first pulse duration time is generated, and the current flow in the recloser during the first pulse duration time is analyzed. A second pulse having a second duration time that is longer than the first pulse duration time is generated if it is determined that no fault current exists during the first pulse duration time, and the system voltages and the current flowing through the recloser after the second pulse duration time is analyzed for the presence of the fault.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 5, 2021
    Assignee: S&C Electric Company
    Inventors: Alejandro Montenegro, Yoav Sharon
  • Patent number: 10879892
    Abstract: A switching element control circuit is configured to perform a measurement mode in which a threshold voltage of a switching element is measured and a control mode in which an ON/OFF operation of the switching element is controlled in a switching manner. The switching element control circuit includes: a threshold voltage measurement power source; a third electrode voltage control part; an ON/OFF state determination part; and a memory part which stores the third electrode voltage applied to the third electrode as a threshold voltage of the switching element. The third electrode voltage control part controls, in the control mode, the third electrode voltage based on information including the threshold voltage stored in the memory part at the time of bringing the switching element into an ON state.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: December 29, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kenichi Suzuki, Wataru Miyazawa
  • Patent number: 10816631
    Abstract: A probe correction system is provided. Said probe correction system comprises a time domain reflectometry signal source comprising at least one output port. A test fixture comprises at least one probing point and at least one input port configured to be connectable to the at least one output port. A measurement device comprises at least one input channel. A probe under test comprises at least one probe input port configured to be connectable to the at least one probing point of the test fixture and at least one probe output port configured to be connectable to at least one input channel of the measurement device.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 27, 2020
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Martin Peschke, Benedikt Lippert
  • Patent number: 10749618
    Abstract: Embodiments of a controller device and methods of control for a radio frequency (RF) test environment are generally described herein. The RF test environment may include the controller device, an RF generator, and a device under test (DUT). The DUT may be configurable to switch between multiple configurations. The controller device may receive feedback from the DUT that indicates a current configuration of the DUT. The controller device may use a machine learning rule to determine a set of candidate future configurations of the DUT based on the current configuration of the DUT. The controller device may generate a set of RF waveforms corresponding to the set of candidate future configurations of the DUT, and may transfer the set of RF waveforms to the RF generator.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: August 18, 2020
    Assignee: Raytheon Company
    Inventors: Scott W. Vahey, Aubrey J. Russell
  • Patent number: 10732202
    Abstract: A repairable rigid test probe system includes an annular gimbal supported by an annular gimbal bearing of a probe card assembly, a test substrate seated and aligned within the annular gimbal, a rigid die including thick periphery and a thin center containing an array of through holes that is aligned above the test substrate, and an array of rigid probes inserted into each of the array of through holes, where each rigid probe includes: a tail end that contacts a connection on a facing surface of the test substrate, a collar limiting a distance of insertion, and a tip that contacts a corresponding contact on a facing surface of a device under test.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Craig M. Bocash, David L. Gardell, Peter W. Neff
  • Patent number: 10627441
    Abstract: A semiconductor package test apparatus includes a handler, a test board, and a board temperature controller. The handler includes a first heater and cooler to heat and cool a semiconductor package. The test board tests the semiconductor package, and includes main test board having a test socket and a base test board spaced from the main test board. The board temperature controller includes a second heater and cooler to heat and cool the main test board.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-sin Yang, Min-kyun Sun
  • Patent number: 10403613
    Abstract: A micro LED display module having a light transmissive substrate and a manufacturing method thereof are provided. The light transmissive substrate has good transmissivity with respect to the visible band. The micro LED display module comprises a driver chip block, a LED block, a circuit board and a color layer. The LED block is disposed in the driver chip block and has two semiconductor layers and a plurality of trenches. One of the two semiconductor layers is electrically connected to pixel electrodes and the other is electrically connected to the light transmissive substrate. The trenches define a plurality of micro LED pixels arranged in an array. Each micro LED pixel corresponds to one of the pixel electrodes. The circuit board is electrically connected to the driver chip block, the color layer is disposed in the light transmissive conductive layer, and one of the semiconductor layers has a common electrode.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 3, 2019
    Assignee: SYNDIANT INC.
    Inventors: Chun Chiu Daniel Wong, Hiap Liew Ong, Min Hwang Michael Lyu, Liming Wang
  • Patent number: 10401422
    Abstract: Disclosed are a circuit for testing and analyzing a through-silicon via (TSV) and a method of testing the same. The circuit according to the present disclosure is capable of measuring a voltage applied to a first comparator after passing through a TSV and subsequently determining whether the TSV has a short-circuit fault, measuring the voltage applied to a second comparator after passing through the TSV and subsequently determining whether the TSV has an open-circuit fault, and determining whether the TSV is faulty based on an output from each of the first and second comparators.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: September 3, 2019
    Assignee: INDUSTRY—ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Sung Ho Kang, Young Woo Lee
  • Patent number: 10403614
    Abstract: A micro LED display module and a manufacturing method thereof are provided. The micro LED display module comprises a driver chip block, a LED block, a circuit board and a color layer. The driver chip block has a plurality of pixel electrodes. The LED block is disposed in the driver chip block and has two semiconductor layers and a plurality of trenches. One of the two semiconductor layers is electrically connected to the pixel electrodes and the other is electrically connected to the light transmissive conductive layer. The trenches define a plurality of micro LED pixels arranged in an array. Each trench at least penetrates through the light emitting layer and one of the semiconductor layers. Each micro LED pixel corresponds to one of the pixel electrodes. The circuit board is electrically connected to the driver chip block, the color layer is disposed in the light transmissive conductive layer, and one of the semiconductor layers has a common electrode.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 3, 2019
    Assignee: SYNDIANT INC.
    Inventors: Chun Chiu Daniel Wong, Hiap Liew Ong, Min Hwang Michael Lyu, Liming Wang
  • Patent number: 10365317
    Abstract: A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 30, 2019
    Assignee: DENSO CORPORATION
    Inventors: Masanori Miyata, Yoshifumi Okabe
  • Patent number: 10340848
    Abstract: An I-V measurement method is provided for a solar cell having a collecting electrode on the first surface side of a single-crystalline silicon substrate of a first conductivity type and having a transparent electrode on the outermost surface on the second surface side of the single-crystalline silicon substrate of the first conductivity-type. An electric current is supplied to the solar cell in a state in which flexible metal foil and the transparent electrode are brought into detachable contact with each other such that the flexible metal foil follows undulations of the single-crystalline silicon substrate of a first conductivity type, and the first surface is set as a light-receiving surface. It is preferable that at least on a portion that is in contact with the transparent electrode, the metal foil is formed of at least one selected from the group consisting of Sn, Ag, Ni, In, and Cu.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 2, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Kunta Yoshikawa, Hayato Kawasaki, Kunihiro Nakano, Kenji Yamamoto
  • Patent number: 10317440
    Abstract: A test unit for testing the inductive charging capabilities of a mobile device and a method therefore is provided. Moreover, a calibrator unit for calibrating the test unit is provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 11, 2019
    Assignee: NOK9 ip AB
    Inventors: Joakim Wallman, Martin Neckmar
  • Patent number: 10267856
    Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun
  • Patent number: 10217587
    Abstract: Disclosed herein is a device comprising a pulse trigger switch module configured to generate a first control signal in response to a first input signal value and generate the second control signal in response to a second input signal value. An on pulse generator module provides a first pulse signal having a first predetermined pulse duration in response to the first control signal and an off pulse generator module provides a second pulse signal having a second predetermined pulse duration in response to the second control signal. An on pulse switch module connects a power signal to an output in response to the first pulse signal and an off pulse switch module connects the power signal to the output in response to the second pulse signal.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 26, 2019
    Assignee: WCM INDUSTRIES, INC.
    Inventor: Phil A. Parker
  • Patent number: 10175280
    Abstract: An electronic device test system is configured to test functions of an electronic device. The electronic device test system includes: a test computer, configured to execute an electronic device test program; a scanning device, configured to scan a barcode number of the electronic device; and an optical sensor module, configured to detect a connection status of the electronic device and the test computer. When the optical sensor module confirms the connection status, the electronic device test program starts a test function to test the electronic device, records a test result of the electronic device according to the barcode number, and subsequently generates a retest rate according to the test result.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 8, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Pei-Ming Chang, Shih-Chieh Hsu, Shi-Jie Zhang, Wei-Lung Huang
  • Patent number: 10140397
    Abstract: A computer-implementable method for simulating the electrical behavior of a surge arrester comprises providing a model of the surge arrester with a switchable current path between an anode and a cathode of the surge arrester, wherein the current path comprises a controllable voltage source. The current path is switched into the conducting or blocked state depending on a determined value of a voltage rise of an input voltage present between the anode and the cathode and a determined level of a response voltage. A level of the voltage of the controllable voltage source is set depending on a level of a current flowing in the current path.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: November 27, 2018
    Assignee: EPCOS AG
    Inventor: Robert Hoffmann
  • Patent number: 10054553
    Abstract: A visual inspection method for a light-emitting device includes: providing a light-emitting device having a substrate and a light-emitting portion, the substrate having a substrate upper surface and a substrate bottom surface, the light-emitting portion being provided on the substrate upper surface and having a light-emitting upper surface, a light-emitting lower surface, and a lateral surface which is provided between the light-emitting lower surface and the light-emitting upper surface and which is surrounded by a light shielding member; placing the light-emitting device on an inspection surface so that the substrate bottom surface is opposite to the inspection surface; supplying power to the light-emitting device so that the light-emitting portion emits light from the light-emitting upper surface; and capturing brightness on the inspection surface surrounding an entire outer periphery of the light-emitting device viewed in the height direction while the light-emitting portion emits light.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 21, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Kenta Kazao
  • Patent number: 9880201
    Abstract: A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 9844144
    Abstract: Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus to mount an integrated circuit (IC) package, may include a printed circuit board (PCB), a plurality of pogo pins, and a mounting mechanism. The plurality of pogo pins may be mounted to electrical contacts of the PCB, the plurality of pogo pins may be coupled to the electrical contacts at first ends of the plurality of pogo pins and may be to couple to the IC package at second ends of the plurality of pogo pins. The mounting mechanism may position the IC package on the second ends of the plurality of pogo pins. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Emad Al-Momani, Jack Mumbo, Srikanth Mothukuri
  • Patent number: 9823328
    Abstract: Systems and methods are disclosed that may be employed to calibrate current sense circuitry of CPU core voltage (Vcore) DC/DC voltage regulation circuitry by coupling an individual Vcore phase of a VR as a current source to a VSA phase of the same VR so that the Vcore phase acts as a current sink for the coupled Vcore phase during calibration of the current sense circuitry of the individual Vcore phase.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: November 21, 2017
    Assignee: Dell Products LP
    Inventors: Johan Rahardjo, John J. Breen, Abey K. Mathew
  • Patent number: 9786458
    Abstract: Disclosed herein is a device comprising a pulse trigger switch module configured to generate a first control signal in response to a first input signal value and generate the second control signal in response to a second input signal value. An on pulse generator module provides a first pulse signal having a first predetermined pulse duration in response to the first control signal and an off pulse generator module provides a second pulse signal having a second predetermined pulse duration in response to the second control signal. An on pulse switch module connects a power signal to an output in response to the first pulse signal and an off pulse switch module connects the power signal to the output in response to the second pulse signal.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: October 10, 2017
    Assignee: WCM Industries, Inc.
    Inventor: Phil A. Parker
  • Patent number: 9692299
    Abstract: Disclosed is a voltage-current characteristic generator that includes: a voltage source; a current source; a selector for selecting and outputting the output of either the voltage source or the current source; a sensing portion, connected to an output of the selector, for outputting the output of the selector and for sensing, and feeding back, the voltage and current of the output; and a controller for receiving the voltage and current detected by the sensing portion and for setting the subsequent outputs in the voltage source and the current source, wherein, in addition to setting the subsequent outputs, the controller evaluates an operating mode wherein the subsequent output from the selector is to be from either the voltage source or the current source.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: June 27, 2017
    Assignee: Keysight Technologies, Inc.
    Inventor: Takashi Kitagaki
  • Patent number: 9671456
    Abstract: A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 6, 2017
    Assignee: NXP USA, Inc.
    Inventors: Yoav Weizman, Jacob Fridburg, Shai Shperber
  • Patent number: 9664718
    Abstract: A high speed tuning and measuring algorithm is used for production level testing on-wafer a large number of chips. It applies to a hybrid active injection load pull test system. Using a pre-calibration of the passive tuner and the amplitude and phase settings of the active power injection signal and employing fast harmonic receiver VNA the test system is capable of executing frequency and time domain load pull measurement sets including more than 50 impedance points in a total of 1 second for quantities such as delivered input and output power, PAE, power gain and other. Overall test time, including device hoping and biasing on the automatic probe station is less than 1.5 seconds. This enables production level load pull operations.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 30, 2017
    Inventor: Christos Tsironis
  • Patent number: 9652966
    Abstract: A jumper has a connector and a housing. The housing at least partially encloses a processor in data communication with a non-transitory memory, a global positioning system, a rechargeable battery, and a networking device. The memory comprises software instructions that, when executed by the processor, perform steps for wirelessly transmitting data to a mobile device over a network. The data indicates a jumper identification number, a location of the jumper, and a duration after which the jumper will automatically deactivate. The steps performed include the step of wirelessly outputting an alert to the mobile device when the mobile device is at a first distance from the jumper. The first distance is settable using the mobile device. The alert causes the mobile device to at least one of vibrate and ring.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 16, 2017
    Assignees: ThyssenKrupp Elevator AG, ThyssenKrupp AG
    Inventors: Mike Palazzola, Jimmy Xu, Keith Anderson, Peter F. Feldhusen, Alan M. Parker, Frank P. Dudde, Olivia Stone, William K. Delk
  • Patent number: 9577770
    Abstract: A system for analyzing a probe card comprises a signal generator adapted to generate a radio frequency test signal. a connector for inputting into the probe card the radio frequency test signal, and a detector assembly. The detector assembly comprises an RF chuck for receiving a radio frequency signal from the probe card, and a sensor configured to receive the radio frequency signal from the RF chuck. The sensor is configured to measure a magnitude of the radio frequency signal and to output a measurement signal that represents only the magnitude of the radio frequency signal. The RF chuck and the sensor are mechanically coupled.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: February 21, 2017
    Assignees: APS Soutions GmbH, BE Precision Technology
    Inventors: Paul Oneil, Hanns-Georg Ochsenkuehn, Oscar Beijert
  • Patent number: 9568560
    Abstract: A device for supplying power to an inductive load includes a switching structure designed to control a current in the load, and elements for detecting anomalies designed to generate information on detection or information on non-detection of an anomaly of the short-circuit type able to occur in the cabling toward the load, in combination with information on validity of the information on non-detection of anomalies. The information on anomaly non-detection is delivered without setting the validity information if the measured current at the end of an appropriate time window is less than a given value of current.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: February 14, 2017
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventor: Angelo Pasqualetto
  • Patent number: 9554074
    Abstract: A readout circuit for use in an image sensor includes a sense amplifier circuit coupled to a bitline to sense analog image data from a pixel cell of the image sensor. An analog to digital converter is coupled to the sense amplifier circuit to convert the analog image data to digital image data. A ramp generator circuit is coupled to generate a first ramp signal. The analog to digital converter is coupled to generate the digital image data in response to the analog image data and the first ramp signal. A first capacitive voltage divider is coupled to the ramp generator. The first capacitive voltage divider is coupled to reduce an output voltage swing of the first ramp signal coupled to be received by the analog to digital converter to reduce noise in the first ramp signal.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: January 24, 2017
    Assignee: OmniVision Technologies, Inc.
    Inventors: Liang Zuo, Zhiqiang Song, Liping Deng
  • Patent number: 9488687
    Abstract: A multi-axis motor driving apparatus includes: a plurality of drivers individually connected to corresponding ones of the plurality of motors, for supplying electric power to the corresponding ones of the plurality of motors for driving; and an integrated controller for sequentially supplying electric power to the plurality of motors via the plurality of drivers, and based on detection signals of the encoders, determining for each driver whether or not there is miswiring of at least either of a motor wire that connects one of the plurality of drivers to one of the plurality of motors or a detector wire from the encoder.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 8, 2016
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Isamu Matsumura, Toshinobu Kira
  • Patent number: 9369436
    Abstract: Method and apparatus for use with systems including networked resources where communication between resources is via dual packet protocols wherein a first protocol includes a frame that specifies a destination device/resource and a data field and the second protocol specifies a final destination device/resource and includes a data field, where the second packets are encapsulated in the first protocol packet frames, the method including specifying access control information for resources, for each first protocol packet transmitted on the network, intercepting the first protocol packet prior to the first protocol destination resource, examining a subset of the additional embedded packet information to identify one of the intermediate path resources and the final destination resource, identifying the access control information associated with the identified at least one of the intermediate path resources and the final destination resource and restricting transmission of the first protocol packet as a function of
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 14, 2016
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: David D Brandt, Brian A Batke, Bryan L Singer, Craig D Anderson, Glenn B Schulz, Michael A Bush, John C Wilkinson, Jr., Ramdas M Pai, Steven J Scott
  • Patent number: 9342424
    Abstract: The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Wei Fan, Nagui Halim, Mark C. Johnson, Srinivasan Parthasarathy, Deepak S. Turaga, Olivier Verscheure
  • Patent number: 9274155
    Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr.
  • Patent number: 9176174
    Abstract: A system adapted to measure electrical performance of a device under test (DUT) having two or more ports includes a plurality of signal sources synchronized and configured to generated signals simultaneously, a plurality of first signal paths to obtain transmitted and reflected signals from the DUT, a plurality of second signal paths to obtain incident signals from the signal sources, and a receiver for receiving the reflected, transmitted and incident signals obtained at the first signal paths and the second signal paths. The receiver is adapted to separate the reflected and the transmitted signals obtained from each of the first signal paths. The signal sources are configured to each generate a signal having a frequency offset from each of the others of the signal sources by a known frequency delta.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 3, 2015
    Assignee: ANRITSU COMPANY
    Inventors: Donald Anthony Bradley, Karam Michael Noujeim, Jon S. Martens
  • Patent number: 9178132
    Abstract: A three-dimensional integrated circuit includes a plurality of perpendicular stacked chips. Each chip of the plurality of perpendicular stacked chips includes at least one transistor, a sensing coil, and a magnetic sensor, wherein the magnetic sensor is installed above the at least one transistor and the sensing coil and the sensing coil is installed between the magnetic sensor and the at least one transistor. The chip utilizes the sensing coil to generate a magnetic field including data, and a first chip of the plurality of perpendicular stacked chips adjacent to the chip utilizes a magnetic sensor of the first chip to receive the data generated by the sensing coil of the chip through the magnetic field generated by the sensing coil of the chip.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 3, 2015
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chrong Jung Lin, Ya-Chin King
  • Patent number: 9075100
    Abstract: An exemplary embodiment relates to a method for detecting a failure on a differential bus comprising the steps: detecting a first signal between the bus lines, detecting a second signal between the bus lines, and detecting the failure in case the first signal and the second signal do not show the same absolute value or in case the first signal and the second signal do not show nearly the same absolute value.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 7, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Daniela Trombetti
  • Patent number: 9041421
    Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Chun-Hsien Peng, Pei-Wei Chen, Ping-Hsuan Tsu, ChiaYu Yang, Chun-Yu Lin
  • Publication number: 20150137840
    Abstract: A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Mark Whittington, Mohammadreza Samadiboroujeni
  • Publication number: 20150137839
    Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: Advantest Corporation
    Inventors: Michael JONES, Takahiro Yasui, Alan S. Krech, JR., Edmundo Delapuente, Taichi Fukuda
  • Publication number: 20150137838
    Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: Teradyne, Inc.
    Inventors: Howard Lin, Corbin L. Champion, Jan Paul Anthonie van der Wagt, Ronald A. Sartschev
  • Patent number: 9035667
    Abstract: An automatic testing equipment, an automatic testing system, an a method for controlling automatic testing thereof are disclosed. The automatic testing equipment is used for receiving a control signal to test a durability of a connecting port of a device under test (DUT). The automatic testing equipment includes a testing platform, a testing unit, and a power control unit. The testing platform is used for disposing the DUT. The testing unit includes a main body, an assembly unit, and a height adjustment unit. The assembly unit is used for assembling a test connector. The height adjustment unit is connected with the main body and works with the assembly unit to adjust a height of the assembly unit. The power control unit drives the testing unit to test the connecting port via the test connector after receiving the control signal.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: May 19, 2015
    Assignee: Wistron Corporation
    Inventors: Shi-Ping Wu, Chang-Hao Wang
  • Patent number: 9034666
    Abstract: Some embodiments provide methods, process, systems and apparatus for use in testing multi-axis Micro Electro Mechanical Systems (MEMS) devices. In some embodiments, methods of testing are provided, comprising: selecting, according to a test specification and a test program, at least a first MEMS device on a substrate comprising a plurality of MEMS formed relative to the substrate and applying one or more electrical probes to the first MEMS device; providing power to the first MEMS device through the one or more electrical probes; measuring output signals of the first MEMS device; applying a force to the first MEMS device using a force actuator; measuring a set of output signals of the first MEMS device based on the applied force; and processing test data and generating output test results according to the test specification and test program.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 19, 2015
    Inventors: Vladimir Vaganov, Nickolai Belov
  • Patent number: 9035668
    Abstract: A touch testing system for a capacitive touch device and a method thereof are provided. The system includes a test fixture, at least one magnetization component, at least one magnetic induction component and a driving unit. The fixture is disposed on the touch device and has at least one chute on a position corresponding to the touching area. The magnetization component is disposed on the fixture and enabled by a driving signal to produce a magnetic force. The magnetic induction component is slidably disposed in the chute and inducts the magnetic force to slide along the chute, such that the sensing unit produces a touch testing information. The driving unit is coupled to the magnetization component and the sensing unit, provides the driving signal to enable the magnetization component and receives the touch testing information to feed back a testing result on the capacitive touch device accordingly.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 19, 2015
    Assignee: HannStar Display Corporation
    Inventors: Chien-Hsiang Huang, Hui-Ju Chen
  • Patent number: 9030225
    Abstract: An over voltage protection testing apparatus is applied for testing an over voltage protection function of a power supply apparatus. The over voltage protection testing apparatus mainly includes a voltage boost-storage unit and an energy release unit. The voltage boost-storage unit boosts an original output voltage outputted from the power supply apparatus into a testing voltage. Therefore, no extra testing voltage source is required for testing the over voltage protection function of the power supply apparatus. Moreover, the extra energy would be released to the energy release unit after the testing of the over voltage protection function of the power supply apparatus is finished. Therefore, the energy releasing of the present invention is faster than the energy releasing of a related art.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 12, 2015
    Assignee: Chicony Power Technology Co., Ltd.
    Inventors: Chih-Ching Huang, Jhen-Siang Huang, Wen-Nan Huang, Shiu-Hui Lee
  • Patent number: 9018965
    Abstract: To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.R.L.
    Inventor: Raffaele Ricci
  • Patent number: 9013198
    Abstract: A hard disk drive system including a controller and a plurality of slave testing modules located in respective components of the hard disk drive system. The controller is arranged on a printed circuit board of the hard disk drive system and is configured to transmit information from the hard disk drive system to a host device, receive information from the host device, and, using a master testing module located in the controller, provide test configuration data corresponding to the information received from the host device. Each of the plurality of slave testing modules is configured to receive the test configuration data from the master testing module and test operation of the respective component of the hard disk drive system using the test configuration data.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: April 21, 2015
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho
  • Patent number: 9007078
    Abstract: A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: April 14, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Cheng Hsieh, Shang-Fu Yeh, Ka-Yi Yeh
  • Patent number: 9000786
    Abstract: Methods and systems are disclosed that may be implemented to complete individual phase current sense calibration of a multi-phase voltage regulator (VR) and/or to detect any and all individual bad phases of such a VR by utilizing the reconfiguration capability of a digital VR controller-based VR in conjunction with an improved test process. The disclosed systems and methods may be employed in one example to identify that all individual phases of the multi-phase VR are operational to contribute to the output of the multi-phase VR using a rotating single phase operation testing mode. Individual phase current sense calibration may also be additionally or alternatively completed while the VR is operating under the rotating single phase operation mode.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Dell Products LP
    Inventors: Shiguo Luo, Philip B. Geiger
  • Patent number: 9000785
    Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics SA
    Inventors: Clement Charbuillet, Patrick Scheer
  • Publication number: 20150091594
    Abstract: A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes.
    Type: Application
    Filed: June 24, 2014
    Publication date: April 2, 2015
    Inventor: Brett J Hamilton
  • Publication number: 20150084656
    Abstract: A test and measurement system including a device under test, two de-embed probes connected to the device under test, and a test and measurement instrument connected to the two de-embed probes. The test and measurement instrument includes a processor configured to determine the S-parameter set of the device under test based on measurements from the device under test taken by the two de-embed probes.
    Type: Application
    Filed: May 1, 2014
    Publication date: March 26, 2015
    Applicant: Tektronix, Inc.
    Inventors: John J. Pickerd, Kan Tan, Daniel G. Knierim