Abstract: A controller controls multiple parallel-coupled power transistors. A correction amount calculation unit generates a reference value based on multiple detection values, each of which has a correlation with the switching loss of corresponding one of the multiple power transistors, and generates multiple correction amounts such that the multiple detection values approach the reference value. A gate signal generating unit generates multiple gate signals based on a control instruction and the multiple correction amounts.

Abstract: A method of manufacturing a heater for an aerosol-generating device is provided, the method including: forming a heater body including a heater body frame and a heating element, the heater body defining at least a portion of a boundary of a heating chamber configured to receive an aerosol-generating article such that the heating element is configured to heat the heating chamber, at least part of the heater body frame being manufactured by additive manufacturing. A method of manufacturing an aerosol-generating device; and a heater; and an aerosol-generating device are also provided.

Abstract: A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

Abstract: An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage.

Abstract: Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

Abstract: A system and method for testing devices such as integrated circuits (IC) with integrated antenna arrays configured for wireless signal reception. The method performs a calibration operation on a reference device under test (DUT). During the calibration operation, the DUT receives a series of first signals from a first far-field (FF) location and a series of array transmissions from a second near-field (NF) location using different beamforming settings, and determines therefrom a set of calibration parameters. The calibration parameters may be used by a probe antenna system (PAS) to transmit an array transmission to the DUT from the second NF location to emulate a single probe or multi-probe transmission from the first FF location.

Abstract: A substrate processing technique including: (a) modifying a first base surface of a substrate by supplying a first modifier and a second modifier to the substrate having a surface on which the first base and a second base are exposed, wherein the first modifier contains one or more atoms to which at least one first functional group and at least one second functional group are directly bonded, wherein the second modifier contains an atom to which at least one first functional group and at least one second functional group are directly bonded, and wherein the number of the at least one first functional group contained in one molecule of the second modifier is smaller than the number of the at least one first functional group contained in one molecule of the first modifier; and (b) forming a film on a second base surface by supplying film-forming gas to the substrate.

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

Abstract: A test circuit for testing a switching device. The test circuit includes: a first terminal for receiving a drive signal; second, third and fourth terminals respectively coupled to a ground electrode, a control electrode and a power-supply electrode, of the switching device; and a clamping circuit coupled between the second terminal and the fourth terminal. The clamping circuit is configured to, upon turning on of the switching device responsive to the drive signal, cause a voltage at the third terminal to be a first voltage higher than a threshold of the switching device, and, upon turning off of the switching device responsive to the drive signal, cause the voltage at the third terminal to be a third voltage between the threshold and the first voltage, while clamping a voltage at the fourth terminal to a second voltage lower than a withstand voltage of the switching device.

Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.

Abstract: A monitoring system is proposed for monitoring the state of a cable which is routed through a cable routing device or an energy chain. A monitoring apparatus (10; 20; 30) is provided for this purpose and has an evaluation unit which determines information relating to the state of the cable to be monitored. The invention provides for the monitoring apparatus to comprise a first data communication device (11) with a data communication interface and a second data communication device (12; 12?) with a data communication interface. These devices (11,12) are configured for data communication according to a digital data transmission protocol and are connected by means of the interfaces thereof via the cable (13; I3A; I3B) to be monitored.

Abstract: The present disclosure provides a test apparatus and a jumper thereof. The test apparatus includes a base board and the jumper. The base board has a first slot and a second slot. The first slot has a plurality of electrical contacts, and is configured to receive a plurality of pins of a device under test. The jumper is inserted into the second slot. The jumper includes a body and a plurality of first circuits. The first circuits are disposed on the body and electrically connect the electrical contacts of the first slot to a plurality of pins of a tester.

Abstract: An output module includes a first connection terminal, a second connection terminal, a power supply terminal, a controller, an output device, and a first cutoff switch. The first connection terminal is connected to a high potential side terminal of an external load. The second connection terminal is connected to a low potential side terminal of the external load. The power supply terminal is provided with an external power supply from an external power source. The output device is configured to operate by receiving a power supply generated by or based on the external power supply and to output an analog voltage or an analog current of a value instructed by the controller toward the first connection terminal. The first cutoff switch is configured to be controlled by the controller to open and close a first path between the second connection terminal and a ground.

Abstract: The present invention provides a short-circuit probe card, including: a substrate having an upper surface and a lower surface; a plurality of first contacts formed on the upper surface; and a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts. The first contacts and second contacts are all grounded.

Abstract: One embodiment of the present invention sets forth an integrated circuit. The integrated circuit includes a plurality of subunits associated with a plurality of operating voltages. The integrated circuit also includes one or more voltage regulator circuits that convert a first input voltage into a first plurality of output voltages during a first test, wherein the plurality of output voltages is delivered to the plurality of subunits via a plurality of output channels.

Abstract: An apparatus comprises an antenna array comprising a plurality of antennas. The apparatus comprises a communication interface for receiving a control signal. The apparatus is configured to form a first radio frequency beam in accordance with a predetermined test case independent from the control signal using the antenna array. The apparatus is configured to form a second radio frequency beam that is different from the predetermined test case responsive to instructions contained in the control signal.

Abstract: A method for measuring an input capacitance of a pin of an electronic device includes, using a tester including Pin Electronics (PE), obtaining a first capacitance measurement while the pin is disconnected from the PE, and a second capacitance measurement while the pin is connected to the PE. The input capacitance of the pin is calculated from the first and second capacitance measurements.

Abstract: A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

Abstract: A detection apparatus is for detecting interference on signal paths in a differential voltage measuring system with a signal measuring circuit for measuring bioelectric signals with a number of useful signal paths having at least one shield. In an embodiment, the detection apparatus includes at least one analysis unit, connected to the shield and embodied to detect interference in a useful signal path of the voltage measuring system via a signal measured at the shield in the case of interference.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: A method for driving an output node includes driving a control node of an output device coupled to the output node according to an input signal and using a fixed regulated voltage and a variable regulated voltage. The method includes generating the fixed regulated voltage based on a first power supply voltage, a second power supply voltage, and a first reference voltage. The method includes generating the variable regulated voltage based on the first power supply voltage, the second power supply voltage, and a second reference voltage. The method includes generating the second reference voltage based on the first power supply voltage, the second power supply voltage, a reference current, and a predetermined target voltage level of the control node of the output device. In an embodiment of the method, generating the second reference voltage includes periodically calibrating the second reference voltage.

Abstract: An example test system includes power amplifier circuitry to force voltage or current to a test channel and one or more processing devices configured to control the power amplifier circuitry to comply with a compliance curve. The compliance curve relates output of the voltage to output of the current. According to the compliance curve, maximum current output increases as an absolute value of the voltage output increases.

Abstract: A low-profile passive slide screw load pull tuner is used on-wafer, especially in millimeter-wave frequencies from 25 to 110 GHz and above. It uses special rotating tuning probes insertable in a short slabline mounted inside the tuner housing, which holds the control gear. The tuner is mounted at an angle matching the angle of the wafer-probe, is connected directly of the wafer-probe and ensures optimum reflection factor tuning range.

Abstract: An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

Abstract: A touch sensing unit includes a base layer including a touch sensing area and a touch peripheral area, a touch electrode disposed in the touch sensing area, a touch line disposed in the touch peripheral area and electrically connected to the touch electrode, an inspection pad disposed in a pad area located at one side of the touch peripheral area, and an inspection thin film transistor disposed in the pad area and electrically connected to the touch line and the inspection pad.

Abstract: An inspection system includes a prober, a tester and a malfunction analysis/prediction unit. The prober has a stage holding a substrate having multiple devices formed thereon, a transport unit that transfers the substrate to the stage, and a probe card that brings a plurality of probes into contact with electrodes of the multiple devices on the substrate. A tester applies electrical signals to the multiple devices on the substrate through the probe card and inspects electrical characteristics of the multiple devices. The malfunction analysis/prediction unit, when a malfunction or a sign indicating a stage leading to the malfunction has occurred during an inspection, analyzes history information of the prober and tester related to the malfunction to determine or predict a location of the malfunction.

Abstract: A method and a test apparatus for determining the elements of a dielectric equivalent circuit diagram for an insulation of an electric system and to an insulation monitoring device. All data points of the system's step response are stored for a measuring period Tm, and fault resistance Rf and an initial value Ce0 of leakage capacitance Ce are calculated. After this determination of fault resistance Rf and initial value Ce0, the elements of absorption element Ra and Ca and leakage capacitance Ce are determined by numeric signal processing by using an approximation algorithm which continuously simulates the recorded step response. For simulating the step response, a transfer function G(s) modelled by the equivalent circuit diagram having equivalent circuit diagram elements Rf, Ce, Ra, Ca and measurement resistance Rm is formed analytically and the output signal is calculated, which is described using transfer function G(s), by means of the step function.

Abstract: Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge of an egress domain clock cycle. The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle. The second rising edge may be N egress domain clock cycles after the first rising edge. The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer.

Abstract: A photonic circuit testing device, including a photonic test chip including, on the side of a first surface of the chip: micropillars, each intended to be placed in contact with a corresponding electric connection pad of the photonic circuit; and first optical input/output ports, each intended to be optically coupled to a second corresponding optical input/output port of the photonic circuit.

Abstract: A driving circuit adaptable to an electrophoretic display includes a first transistor and a second transistor electrically connected in series between a first positive voltage node and a first negative voltage node, the first transistor and the second transistor being interconnected at an output node; a third transistor electrically connected between the output node and a ground; a first voltage regulator that switchably provides one of a plurality of positive supply voltages to the first positive voltage node; a second voltage regulator that provides a negative supply voltage to the first negative voltage node; a switching circuit having a plurality of outputs electrically connected to the first transistor, the second transistor and the third transistor to turn on or off the first transistor, the second transistor and the third transistor respectively; and a controller that controls the first voltage regulator, the second voltage regulator and the switching circuit.

Abstract: A stabilization technique is disclosed that suppresses or inhibits glitching behavior on automated test equipment (ATE) during mode transitions. Adjustable stabilizing circuitry can be coupled to at least one of a force voltage circuit or a force current circuit is forcing voltage or current to a device under test (DUT). The adjustable stabilizing circuitry can be adjustably configurable in response to whether at least one of a current clamp or a voltage clamp is in an active clamping mode. In this manner, unwanted glitching behavior associated with mode changes can be reduced or suppressed.

Abstract: A die probe including a probe tip operably connected to a first surface of a thin film; a metal trace, wherein a first portion of the metal trace is operably connected to a second surface of the thin film, the second surface of the thin film opposite the first surface of the thin film; and an upper space transformer, wherein a second portion of the metal trace is operably connected to the upper space transformer, wherein a pressurized liquid and/or gas is configured to expand a space between the second surface of the thin film and the upper space transformer.

Abstract: A semiconductor system includes a slave and a master, wherein the slave includes a plurality of unit memory regions, and is configured to transmit determination result data generated by comparing reference data and test data, to the master, and wherein the master is configured to write the reference data and the test data in the plurality of unit memory regions.

Abstract: A system includes a controller that is configured to generate a plurality of switch control signals; a plurality of electrical circuit elements, the plurality of electrical circuit elements being characterized by a plurality of impedances, respectively; a plurality of voltage sources; and a plurality of switches that are programmable to couple the plurality of electrical circuit elements to the plurality of voltage sources responsive to the plurality of switch control signals.

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

Abstract: A method and device for determining a division of a total insulation resistance and of a total system leakage capacitance in an ungrounded power supply system. The basic idea is to determine how the total insulation resistance is divided into partial insulation resistances and how the total system leakage capacitance is divided into partial system leakage capacitances between the active conductors of the ungrounded power supply system from displacement voltages measured between each of the active conductors of the ungrounded power supply system based on values determined in advance for the total insulation resistance and for the total system leakage capacitance of the ungrounded power supply system. By evaluating the displacement voltages in terms of their changes in amplitude, their frequency and their phasing, conclusions can be drawn as to the division of the total insulation resistance and of the total system leakage capacitance between the individual active conductors.

Abstract: Method for the continuous insulation monitoring of an electrical conductor arrangement (12) with an active conductor (3) and a conductor structure (14) electrically insulated from the active conductor (3), wherein the quality of the conductor arrangement (12) as well as the arrangement of the active conductor (3) and the conductor structure (14) is such that almost identical propagation conditions for the active conductor (3) and the conductor structure (14) apply to a current flow against ground (E), wherein an insulation resistance measurement is being carried out, wherein an insulation monitoring unit (20) is connected between the conductor structure (14) and ground (E), which superimposes a measurement voltage onto the electrical conductor arrangement (12), which generates a measurement current proportionally to the insulation resistance of the conductor arrangement (12), which is acquired in the insulation resistance measurement unit (20) and evaluated.

Abstract: Detection of faults in an electrical power distribution network that includes measuring current flowing through a recloser in a feeder line, detecting a fault current indicating a fault is present in the feeder line, and opening a switch in the recloser in response to detecting the fault current. A first pulse having a first pulse duration time is generated, and the current flow in the recloser during the first pulse duration time is analyzed. A second pulse having a second duration time that is longer than the first pulse duration time is generated if it is determined that no fault current exists during the first pulse duration time, and the system voltages and the current flowing through the recloser after the second pulse duration time is analyzed for the presence of the fault.

Abstract: A switching element control circuit is configured to perform a measurement mode in which a threshold voltage of a switching element is measured and a control mode in which an ON/OFF operation of the switching element is controlled in a switching manner. The switching element control circuit includes: a threshold voltage measurement power source; a third electrode voltage control part; an ON/OFF state determination part; and a memory part which stores the third electrode voltage applied to the third electrode as a threshold voltage of the switching element. The third electrode voltage control part controls, in the control mode, the third electrode voltage based on information including the threshold voltage stored in the memory part at the time of bringing the switching element into an ON state.

Abstract: A probe correction system is provided. Said probe correction system comprises a time domain reflectometry signal source comprising at least one output port. A test fixture comprises at least one probing point and at least one input port configured to be connectable to the at least one output port. A measurement device comprises at least one input channel. A probe under test comprises at least one probe input port configured to be connectable to the at least one probing point of the test fixture and at least one probe output port configured to be connectable to at least one input channel of the measurement device.

Abstract: Embodiments of a controller device and methods of control for a radio frequency (RF) test environment are generally described herein. The RF test environment may include the controller device, an RF generator, and a device under test (DUT). The DUT may be configurable to switch between multiple configurations. The controller device may receive feedback from the DUT that indicates a current configuration of the DUT. The controller device may use a machine learning rule to determine a set of candidate future configurations of the DUT based on the current configuration of the DUT. The controller device may generate a set of RF waveforms corresponding to the set of candidate future configurations of the DUT, and may transfer the set of RF waveforms to the RF generator.

Abstract: A repairable rigid test probe system includes an annular gimbal supported by an annular gimbal bearing of a probe card assembly, a test substrate seated and aligned within the annular gimbal, a rigid die including thick periphery and a thin center containing an array of through holes that is aligned above the test substrate, and an array of rigid probes inserted into each of the array of through holes, where each rigid probe includes: a tail end that contacts a connection on a facing surface of the test substrate, a collar limiting a distance of insertion, and a tip that contacts a corresponding contact on a facing surface of a device under test.

Abstract: A semiconductor package test apparatus includes a handler, a test board, and a board temperature controller. The handler includes a first heater and cooler to heat and cool a semiconductor package. The test board tests the semiconductor package, and includes main test board having a test socket and a base test board spaced from the main test board. The board temperature controller includes a second heater and cooler to heat and cool the main test board.

Abstract: Disclosed are a circuit for testing and analyzing a through-silicon via (TSV) and a method of testing the same. The circuit according to the present disclosure is capable of measuring a voltage applied to a first comparator after passing through a TSV and subsequently determining whether the TSV has a short-circuit fault, measuring the voltage applied to a second comparator after passing through the TSV and subsequently determining whether the TSV has an open-circuit fault, and determining whether the TSV is faulty based on an output from each of the first and second comparators.

Abstract: A micro LED display module having a light transmissive substrate and a manufacturing method thereof are provided. The light transmissive substrate has good transmissivity with respect to the visible band. The micro LED display module comprises a driver chip block, a LED block, a circuit board and a color layer. The LED block is disposed in the driver chip block and has two semiconductor layers and a plurality of trenches. One of the two semiconductor layers is electrically connected to pixel electrodes and the other is electrically connected to the light transmissive substrate. The trenches define a plurality of micro LED pixels arranged in an array. Each micro LED pixel corresponds to one of the pixel electrodes. The circuit board is electrically connected to the driver chip block, the color layer is disposed in the light transmissive conductive layer, and one of the semiconductor layers has a common electrode.

Abstract: A micro LED display module and a manufacturing method thereof are provided. The micro LED display module comprises a driver chip block, a LED block, a circuit board and a color layer. The driver chip block has a plurality of pixel electrodes. The LED block is disposed in the driver chip block and has two semiconductor layers and a plurality of trenches. One of the two semiconductor layers is electrically connected to the pixel electrodes and the other is electrically connected to the light transmissive conductive layer. The trenches define a plurality of micro LED pixels arranged in an array. Each trench at least penetrates through the light emitting layer and one of the semiconductor layers. Each micro LED pixel corresponds to one of the pixel electrodes. The circuit board is electrically connected to the driver chip block, the color layer is disposed in the light transmissive conductive layer, and one of the semiconductor layers has a common electrode.

Abstract: A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.

Abstract: An I-V measurement method is provided for a solar cell having a collecting electrode on the first surface side of a single-crystalline silicon substrate of a first conductivity type and having a transparent electrode on the outermost surface on the second surface side of the single-crystalline silicon substrate of the first conductivity-type. An electric current is supplied to the solar cell in a state in which flexible metal foil and the transparent electrode are brought into detachable contact with each other such that the flexible metal foil follows undulations of the single-crystalline silicon substrate of a first conductivity type, and the first surface is set as a light-receiving surface. It is preferable that at least on a portion that is in contact with the transparent electrode, the metal foil is formed of at least one selected from the group consisting of Sn, Ag, Ni, In, and Cu.

Abstract: A test unit for testing the inductive charging capabilities of a mobile device and a method therefore is provided. Moreover, a calibrator unit for calibrating the test unit is provided.

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.