INTERFERENCE CANCELLATION AND IMPROVED SIGNAL-TO-NOISE RATIO CIRCUITS, SYSTEMS, AND METHODS
Interference cancellation for wideband and narrowband communications systems is provided without apriori knowledge of statistical information about an interfering signal. In one embodiment a demodulator circuit can operate in an environment where a “no lock” situation would normally occur to remove the interference and acquire signals in low signal-to-noise ratio (SNR) conditions and high signal-to-interference ration (SIR) conditions. In other embodiments, performance is improved by introducing statistics of the interfering signal, and these statistics regarding the communications channel and interference properties (i.e., characteristics of the interfering signal) can be adaptive or “learned” in other embodiments.
Latest STMICROELECTRONICS (CANADA), INC. Patents:
- Network interface for a SoC comprising an improved communication controller
- Apparatus and method for depth-based image scaling of 3D visual content
- Interference cancellation and improved signal-to-noise ratio circuits, systems, and methods
- S12 TX FIR architecture
- NETWORK INTERFACE FOR A SoC COMPRISING AN IMPROVED COMMUNICATION CONTROLLER
The present application claims the benefit of copending U.S. Provisional Patent Application No. 61/429,034, filed Dec. 31, 2010, which application is incorporated herein by reference in its entirety.
TECHNICAL FIELDEmbodiments relate generally to communications systems and, more specifically, to demodulation circuits having interference cancellation and improved signal-to-noise ratio performance.
BACKGROUNDIn both narrowband and wideband communications systems interference cancellation is the process of removing or “cancelling” the degrading effects of a high power interfering signal that is spectrally adjacent to the input signal of interest (i.e., the desired input signal). This degradation is measured in terms of a reduced bit error rate (BER), reduced distance over which input signals may be communicated over the corresponding communications channel, and increased guard band protection resulting in lower efficiency utilization of the frequency or band of interest, as will be appreciated by those skilled in the art. The use of interference cancellation is prevalent in wideband systems such as cellular telephone systems, terrestrial wireless systems employing IEEE802.16 protocols, and in systems where a wideband, high power transmitter is co-located with a receiver bank, as will also be appreciated by those skilled in the art. In many situations the type or characteristics of the interference is known, or in other situations the interference cancellation system attempts to adaptively characterize or “learn” the type of interference prior to implementing approaches to remove or cancel this interference. There is a need for improved methods, circuits, and systems for interference cancellation in communications systems.
SUMMARYEmbodiments are directed to circuits, systems, and methods of interference cancellation for wideband and narrowband communications systems without a priori knowledge of statistical information about an interfering signal. According to one embodiment, a demodulator circuit can operate in an environment where a “no lock” situation would normally occur to remove the interference and acquire signals in low signal-to-noise ratio (SNR) conditions and high signal-to-interference ratio (SIR) conditions. In other embodiments, performance is improved by introducing statistics of the interfering signal, and these statistics regarding the communications channel and interference properties (i.e., characteristics of the interfering signal) can be adaptive or “learned.”
According to one embodiment, a demodulation circuit includes an interference estimation circuit adapted to receive an input signal and generate an interference estimation signal from the input signal and an adaptive filtering circuit coupled to the interference estimation circuit and operable to perform spectral inversion on the estimation signal to obtain an inverted signal that is then applied to the input signal to substantially cancel interference contained in the input signal.
In the present description, certain details are set forth in conjunction with the described embodiments to provide a sufficient understanding of the invention. One skilled in the art will appreciate, however, that the invention may be practiced without these particular details. Furthermore, one skilled in the art will appreciate that the example embodiments described below do not limit the scope of the present disclosure, and will also understand that various modifications, equivalents, and combinations of the disclosed embodiments and components of such embodiments are within the scope of the present disclosure. Embodiments including fewer than all the components or steps of any of the respective described embodiments may also be within the scope of the present disclosure although not expressly described in detail below. Finally, the operation of well-known components and/or processes has not been shown or described in detail below to avoid unnecessarily obscuring the present disclosure.
The demodulation circuit 100 receives the input signal 106 which includes a known signal of interest or desired signal S and the interfering signal I. This concept is illustrated in the graph of
In
An analog-to-digital converter (ADC) 110 samples the filtered input signal from the varactor variable filter 108, with this sampling adhering to the requirements of the Nyquist sampling theorem, and outputs digital values corresponding to these samples. An I-Q clock generator 112 generates a plurality of clock signals that are applied to appropriately clock the ADC 110 and other components in the interference estimation circuit 102. As seen in
A complex multiplier 114 receives these digital values from the ADC 110 and performs complex multiplication on these digital values to thereby effectively multiply this digital signal into baseband and form an equivalent I-Q sample set, as will be discussed in more detail below. An adaptive low pass filter 116 receives the I-Q sample set from the complex multiplier 114 and this filter in combination with an I-Q phase order filter 118 operate to filter this sample set to thereby isolate the multiplication images generated by the complex multiplication, and provide passband shaping in the form of adaptive filtering. In this way, the I-Q phase order filter 118 outputs an estimate of the interfering signal I to be removed as seen in
The output of the I-Q phase order filter 118 is supplied to a second complex multiplier 120 that is clocked by a clock generated by a second I-Q clock generator 122. This second I-Q clock generator 122 generates a clock that is corrected based upon corrections being applied by a demodulator circuit 124 on a symbol-by-symbol basis. More specifically, the demodulator circuit 124 demodulator provides symbol clock information to a numerically controlled oscillator (NCO) 126 which operates at a multiple of the symbol clock frequency and operates in combination with a fine phase adjustment circuit 128 to fine tune phase correction of the clock generated by the second I-Q clock generator 122. This coupling of the demodulator circuit 124 and the coherent symbol clock via the NCO 126 and fine phase adjustment circuit 128 functions to perform the coherent removal of interference. The demodulator circuit 124 is capable of locking and synchronizing due to the first stage non-coherent interference reduction performed by the interference estimation circuit 102, as will be described in more detail below.
The second complex multiplier 120 receives the output from the I-Q phase order filter 118 an complex multiplies responsive to the clock signals from the second I-Q clock generator 122. These clock signals from the second I-Q clock generator have a frequency of approximately (fc-F1), where recall as discussed above the frequency F1 is the frequency of the in-band portion of the interfering signal I that is being removed. An adaptive low pass filter 130 then filters the output from the complex multiplier 120 to thereby isolate the in-band portion of the interfering signal I as shown in
At this point, the spectrally inverted in-band interference signal I output by the I-Q phase order filter 132 as illustrated in
In a similar way, a complex multiplier 140, sin(x)/x compensation circuit 142, and digital-to-analog converter (DAC) 144 operate in combination to receive the output signal from the I-Q phase order filter 118 and to re-modulate this signal to the passband. Thus, the output of the DAC 144 essentially represents the original input signal 106 supplied to the ADC 110.
The interference-corrected signal output from the summation circuit 146 is input to an analog-to-digital converter (ADC) 148 that samples and digitizes this signal and provides corresponding digital values to the demodulator circuit 124 which, in turn, demodulates these digital values to obtain the original unmodulated I-Q encoded data.
In another embodiment, the interference cancellation circuit 102 of
The demodulation circuit 100 described in
The adaptive filtering circuit of
Analysis and removal of in band interference is possible with the demodulation circuits 100/900 of
The following equations provide a mathematical foundation for the operation of the previously described embodiments:
Input (0,
A1 cos(ω1t+φ1)+A2 cos(ω2t+φ2) (1)
ADC 110:
Complex Multiplier 114:
[A1 cos(ω1t+φ1)+Ak cos(ω2t+φ2)][cos(ωst+φs)+sin(ωst+φx)] (3)
I-Q Phase Order Filter 118:
Complex Multiplier 140: Spectrally inverted signal with non-coherent sampling errors embedded
Where m/n is the sampling error term representing the non-coherent representation of the input interfering signal.
Coherent Cancellation:
Identical output to equation (5) above except that the ratio of (m/n) approaches 0 and Δ approaches “1”.
Input to ADC 148:
Represents the required signal plus interfering signal attenuated by a factor of K, where K represents the attenuation due to the interference canceller non coherent and coherent final inversion of the interfering signal:
One skilled in the art will understand that even though various embodiments and advantages have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Moreover, the functions performed by various components described above may be implemented through circuitry or components other than those disclosed for the various embodiments described above. Moreover, the described functions of the various components may be combined to be performed by fewer elements or performed by more elements, depending upon design considerations for the device or system being implemented, as will appreciated by those skilled in the art. Therefore, the present invention is to be limited only by the appended claims.
Claims
1. A demodulation circuit, comprising:
- an interference estimation circuit adapted to receive an input signal and generate an interference estimation signal from the input signal; and
- an adaptive filtering circuit coupled to the interference estimation circuit and operable to perform spectral inversion on the estimation signal to obtain an inverted signal is then applied to the input signal to substantially cancel interference contained in the input signal.
2. The demodulation circuit of claim 1, wherein the adaptive filtering circuit generates the inverted signal to cancel both in band and out of band interference present on the input signal.
3. The demodulation circuit of claim 2, wherein the adaptive filtering circuit is operable to cancel one of two adjacent interfering signals.
4. The demodulation circuit of claim 3, wherein the adaptive filtering circuit is operable to cancel both adjacent interfering signals.
5. The demodulation circuit of claim 1, wherein the interference estimation circuit and adaptive filtering circuits are formed only from digital circuitry.
6. The demodulation circuit of claim 1, wherein the interference estimation circuit comprises:
- an analog-to-digital converter adapted to receive in input signal having a desired signal and an interfering signal;
- a complex multiplier circuit coupled to the analog-to-digital converter;
- an adaptive low pass filter having an input coupled to the complex multiplier circuit and an output; and
- an I-Q phase order circuit coupled to the adaptive low pass filter.
7. The demodulation circuit of claim 6 further comprising an I-Q delay circuit coupled to the output of the I-Q phase order circuit.
8. An incoherent demodulator comprising: local oscillator circuitry for producing a pair of orthogonal carriers; a pair of analog mixers for incoherently demodulating a pair of modulated orthogonal signals with said orthogonal carriers to produce a pair of analog orthogonal baseband signals, there being a phase rotation in said analog orthogonal baseband signals resulting from the incoherent demodulation of said modulated signals; a pair of analog-to-digital converters for processing said analog orthogonal baseband signals to produce first and second digital signals; gain controlled circuitry for scaling the first digital signal, said gain controlled circuitry including averaging circuitry to produce a first average value representing an average power of a scaled first digital signal, and a second average value representing an average power of said second digital signal, such that a difference which exists between the average power of the scaled first digital signal and the average power of the second digital signal reduces to zero; and a digital phase shifter for processing first and second output signals of said gain controlled circuitry so that the processed first and second output signals no longer contain said phase rotation.
9. The incoherent demodulator of claim 8, further comprising first and second automatic gain controlled circuits for respectively processing first and second digital output digital signals processed by said digital phase shifter to produce amplitude-controlled digital output whose amplitudes are maintained at a value.
10. The incoherent demodulator of claim 8, wherein said gain controlled circuitry further comprises: a digital multiplier for multiplying said first digital signal with a control signal to produce the scaled first digital signal; and control circuitry for deriving a signal from said first and second average values and supplying the signal to said digital multiplier as said control signal so that a difference which exists between said first and second average values reduces to zero.
11. The incoherent demodulator of claim 10, wherein said control circuitry is arranged to make a comparison between the first and second average values and derives said control signal from a result of the comparison.
12. The incoherent demodulator of claim 3, wherein said control circuitry is arranged to determine a ratio between the first and second average values and derives said control signal from said ratio.
13. The incoherent demodulator of claim 8, wherein said control circuitry comprises: a multiplier for multiplying one of said first and second average values by a scaling factor to produce a scaled average value; a comparator for producing a difference signal representing a difference between the scaled average value and the other one of said first and second average values; and an integrator for integrating said difference signal and supplying the integrated difference signal to said multiplier as said scaling factor, whereby the scaling factor represents said ratio between the first and second average values when said difference signal becomes equal to zero.
14. The incoherent demodulator of claim 8, wherein said control circuitry comprises: a first multiplier for multiplying said first average value by a scaling factor to produce a scaled first average value; a second multiplier for multiplying said second average value by said scaling factor to produce a scaled second average value; a comparator for producing a difference signal representing a difference between the scaled second average value and 1; and an integrator for integrating said difference signal and supplying the integrated difference signal to said first and second multipliers as said scaling factor, whereby the scaled first average value represents said ratio between the first and second average values when the scaled second average value becomes equal to 1.
15. The incoherent demodulator of claim 8, wherein said averaging circuitry includes said phase rotation in the calculation of said first average value representing the average power of the scaled first digital signal and said second average value representing the average power of said second digital signal.
16. The incoherent demodulator of claim 15, wherein said gain controlled circuitry operates independently of the operation of said first and second automatic gain controlled circuits.
17. The incoherent demodulator of claim 16, wherein said averaging circuitry includes said phase rotation in the calculation of said first average value representing the average power of the scaled first digital signal and said second average value representing the average power of said second digital signal.
18. The incoherent demodulator of claim 16, wherein said gain controlled circuitry operates independently of the operation of said first and second automatic gain controlled circuits.
19. A demodulation method, comprising:
- incoherently demodulating a pair of modulated orthogonal signals with a pair of orthogonal carriers to produce a pair of analog orthogonal baseband signals, there being a phase rotation in said analog orthogonal baseband signals resulting from the incoherent demodulation of said modulated signals; converting said analog orthogonal baseband signals to first and second digital signals;
- scaling the first digital signal, to produce a first average value representing an average power of a scaled first digital signal, and a second average value representing an average power of said second digital signal, such that a difference which exists between the average power of the scaled first digital signal and the average power of the second digital signal reduces to zero; and
- removing said phase rotation which exists between the scaled first digital signal and the second digital signal.
20. The method of claim 19, wherein said scaling the first digital signal comprises: multiplying said first digital signal with a control signal to produce a scaled first digital signal; and deriving a signal from said first and second average values and using the signal as said control signal so that a difference which exists between said first and second average values reduces to zero.
21. The method of claim 19, wherein said deriving a signal from said first and second average values comprises making a comparison between the first and second average values and deriving said control signal from a result of the comparison.
22. The method of claim 21, wherein said deriving a signal from said first and second average values comprises determining a ratio between the first and second average values and deriving said control signal from said ratio.
23. The method of claim 19, wherein incoherently demodulating includes providing an adaptive filtering circuit.
24. The method of claim 23, wherein the adaptive filtering circuit is operable to cancel one of two adjacent interfering signals.
25. The method of claim 24, wherein the adaptive filtering circuit is operable to cancel both adjacent interfering signals.
26. The method of claim 25, wherein the adaptive filtering circuit is formed only from digital circuitry.
Type: Application
Filed: Nov 16, 2011
Publication Date: Jul 5, 2012
Applicant: STMICROELECTRONICS (CANADA), INC. (NEPEAN)
Inventors: JOSE AUGUSTO LIMA (STITTSVILLE), ANTONIO MASCIOLI (NEPEAN)
Application Number: 13/298,254
International Classification: H04L 27/06 (20060101);