Output Power Limiter in an Audio Amplifier

Abstract

An output power limiter system (PLS) for audio amplifiers may be designed as a feedback control system for protection of the load and/or quality of the audio experience. The PLS may use comparator to sense the output current, compare it to a specified threshold, and assert a signal when the output current reaches and exceeds the specified threshold. The output signal from the comparator may enable a counter that is clocked with a high frequency clock to begin counting to measure the pulse-width of the comparator output. The output of the counter may be averaged through a fast attack and slow release infinite impulse response (IIR) filter having programmable settings to generate a rate of attenuation or rate of release that adjusts a gain correction in terms of decibels (dB). The output of the IIR filter may then be used for attenuating the output current.

Description

PRIORITY CLAIM

This application claims benefit of priority of U.S. provisional application Ser. No. 61/543,998 titled “Circuits and Methods Used in Audio Signal Processing”, filed Oct. 6, 2011, which is hereby incorporated by reference in its entirety as though fully and completely set forth herein.

FIELD OF THE INVENTION

The present invention relates generally to signal processing and mixed signal circuits, and more particularly to limiting output power in an audio amplifier.

DESCRIPTION OF THE RELATED ART

Signal processing represents a combined application of electrical/computer engineering and mathematical principles, primarily directed to the analysis of and operation on either discrete or continuous time signals. Signals of interest can include sound, images, time-varying measurement values and sensor data, for example biological data such as electrocardiograms, control system signals, telecommunication transmission signals such as radio signals, and many others. Signals are typically analog and/or digital electrical representations of time-varying or spatial-varying physical quantities. Types of signal processing include analog, discrete time, and digital.

Analog signal processing is performed on signals that have not been digitized, for example signals that are used in classical radio, telephone, radar, and television systems. Analog signal processing typically makes use of linear electronic circuits such as passive filters, active filters, additive mixers, integrators and various types of delay lines, as well as non-linear circuits such as frequency mixers and voltage-controlled amplifiers, voltage-controlled filters, voltage-controlled oscillators and phase-locked loops. Discrete time signal processing is performed on sampled signals that are defined at discrete points in time, and as such are quantized in time, but not in magnitude. Analog discrete-time signal processing is based on electronic devices such as sample and hold circuits, analog time-division multiplexers, analog delay lines and analog feedback shift registers, and may be considered a predecessor of digital signal processing.

Digital signal processing involves the processing of digitized discrete-time sampled signals. Processing is typically performed by general-purpose computers or digital circuits such as application specific integrated circuits (ASICs), field-programmable gate arrays, or specialized digital signal processors (DSPs). Digital signal processing mostly includes performing arithmetic operations such as fixed-point and floating-point operations, real-valued and complex-valued operations, multiplication and addition. Many of these operations are implemented through the use of circular buffers and look-up tables. Examples of digital signal processing algorithms include Fast Fourier transforms (FFT), finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and adaptive filters such as the Wiener and Kalman filters.

Audio signal processing, sometimes referred to as audio processing, is the processing of electrical signals that correspond to auditory signals, or sound. Since audio signals may be electronically represented in either digital or analog format, audio signal processing may also take place in either the analog or digital domain. In analog audio signal processing, operations are performed directly on the electrical signals corresponding to the audio signals, while digital signal processing consists mostly of mathematical operations performed on digital representations of the electrical signals that correspond to respective audio signals. Typically, the digital representation of audio signals expresses the pressure waveform that characterizes the audio signal as a sequence of binary numbers. This permits signal processing using digital circuits such as microprocessors and computers, and while analog to digital conversion can be prone to loss, most modern audio systems use the digital approach because digital signal processing techniques are overall more powerful and efficient than signal processing in the analog domain.

Overall, since audio signals first need to be converted to electrical signals, digital audio processing systems include both analog and digital components in a full processing path that begins with the pressure waveforms that physically define the audio signal and ends with the digital representation of the corresponding electrical signals derived therefrom. Some of the most common components typically used in audio processing systems include pulse-width modulators, power limiters, start-up circuits, power regulators, comparators, amplifiers, oscillators, among others. The quality and operating precision of these components directly impacts the quality of audio signal processing systems, as designers have to continually overcome numerous difficult design challenges to meet required specifications and quality standards.

SUMMARY

Various embodiments of an amplifier feature the capability of limiting output power in the amplifier. The amplifier may include two or more pulse-width modulators (PWM) controlling respective sets of switches, and for large input signals the output load may become susceptible to potential damage. Therefore, it is desirable to attenuate the output of the amplifier in a controlled manner that protects the load without interrupting or compromising the quality of the audio signal in any way. In one set of embodiments, output power in the amplifier may be limited through a pseudo-power limiter, which may be operated to reduce the width of the PWM pulse to the gate of the high-side FET in a push-pull bridge configuration, to effectively limit the amount of current that passes through the load. The output power is defined as the product of the output voltage and output current, P=V*I.

The power limiter may include a mixed-signal system that uses a simple analog-to-digital converter (ADC) to sense the output current level of the corresponding audio output signal and compare this current level to a specified threshold current level. The power limiter may also include a digital circuit that samples the error output, filters out the error, and attenuates the output audio through direct gain scaling of the PWM output pulse. In one set of embodiments, the ADC with the built-in error detection threshold may be as simple as an analog comparator that asserts a signal when its input is greater than the error threshold. Subsequently, the output signal from the comparator may be used to enable a counter clocked with a high frequency clock to begin counting in order to measure the pulse width, and therefore essentially digitize the error (i.e. it obtains a numeric/digital value corresponding to the error). The digital filter may be a first, second or higher order infinite impulse response (IIR) filter to average the error. In some embodiments, the circuit used for attenuating the output audio may be a fast attack and slow release IIR filter with programmable settings, to generate a rate of attenuation or rate of release that adjusts a gain correction in terms of decibels (dB). The gain correction circuit, which attenuates the width of the PWM output pulse, may be a circuit similar to a volume adjustment circuit used in audio systems.

In one set of embodiments, the audio amplifier may be an open-loop amplifier or a closed-loop amplifier in terms of accepted industry audio performance specifications such as signal to noise ratio (SNR), total harmonic distortion plus noise (THD+N), cross-talk, etc. The limiter system may be designed as a feedback control system for either protection of the load or quality of the audio experience.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of embodiments of the present invention may be obtained when the following Detailed Description is considered in conjunction with the following drawings, in which:

FIG. 1 illustrates various exemplary systems or devices which may use the techniques described herein;

FIG. 2 is a block diagram of a portion of a system including a Class D amplifier;

FIG. 3 is an exemplary block diagram of an audio subsystem according to prior art;

FIG. 4 shows the partial block diagram of the audio subsystem of FIG. 3 driving a Half-Bridge topology, according to prior art;

FIG. 5 shows the partial block diagram of the audio subsystem of FIG. 4 featuring a current-fault protection circuit topology, according to prior art;

FIG. 6 shows waveforms of interest during a faulted shutdown event corresponding to the current fault protection implementation shown in FIG. 5, according to prior art;

FIG. 7 shows the partial block diagram of the audio subsystem of FIG. 5 featuring a power limiting circuit topology according to one embodiment;

FIG. 8 shows the relevant waveforms illustrating the circuit behavior for the power limiter implementation shown in FIG. 7, according to one embodiment;

FIG. 9a shows a graph illustrating the current threshold programming over the range resistance settings versus current for power limiting according to one embodiment, in which the outer comparator (fault protection) is set to an absolute fixed threshold, while the inner (power limiting) comparator threshold is programmed with a value of an external resistor;

FIG. 9b shows a graph illustrating the current threshold programming over the range resistance settings versus current, for power limiting, according to one embodiment in which the outer (fault protection) and inner (power limiting) comparators are programmed with absolute fixed thresholds;

FIG. 9c shows a graph illustrating the current threshold programming over the range resistance settings versus current, for power limiting, according to one embodiment in which the outer (fault protection) and inner (power limiting) comparators are programmed with a value of an external resistor;

FIG. 10 shows a partial logic diagram of the audio subsystem of FIG. 7 featuring an improved power limiting circuit topology with digital signal processing, according to one embodiment;

FIG. 11 shows the relevant waveforms illustrating the circuit behavior for PWM pulse scaling as determined by the power limiter implementation shown in FIG. 10, according to one embodiment;

FIG. 12 shows the control diagram of one embodiment of a fast attack and slow release IIR filter; and

FIG. 13 illustrates the ideal/calculated PWM pulses scaled by one-third to new PWM outputs, for variable pulse-width common-mode voltage modulation according to one embodiment.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION

FIG. 1 illustrates exemplary systems, which may utilize the techniques described above. More specifically, FIG. 1 illustrates exemplary systems, which may utilize an audio subsystem, (which may include an amplifier such as a Class D amplifier), featuring various improvements. As shown, embodiments of the techniques disclosed herein may be used in any one ore more of various systems which involve the amplification of signals. For example, embodiments of the invention may be used in various systems that operate to amplify audio signals for provision to a loudspeaker for audible presentation. As shown, the exemplary systems may include a display device 102; an audio system 104, such as a stereo amplified docking station for a portable music player, CD player, etc.; or a telephone 106 and 108, such as a smart phone, e.g., an iPHONE™ or other similar type of smart phone. It should be noted that FIG. 1 is provided by way of example, and is by no means intended to be exhaustive. Accordingly, various embodiments disclosed herein may equally be used in other applications and systems not shown in FIG. 1, where limiting the output power is desired. It is also noted that the various terms or designations for circuits, such as “signal processing”, “power limiting”, etc. are merely names or identifiers used to distinguish among these circuits, and these terms are not intended to connote any specific meaning.

FIG. 2 illustrates an example of an Audio subsystem 120 which may be present in the systems of FIG. 1. In one set of embodiments, audio subsystem may be an amplifier subsystem, which may more specifically be a class D amplifier subsystem. In one or more of the devices of FIG. 1, at least one Audio subsystem 120 may be present in the audio output section of the device, and more specifically in the amplifier portion of the audio section of the device. As shown in FIG. 2, an audio input signal 118 may be received at an input to the Audio subsystem 120. The Audio subsystem 120 receives the audio input signal 118 and operates to amplify the received audio input signal to produce amplified audio output signal 122. The amplified audio output signal 122 may then be provided to loudspeaker 124 for audible presentation.

FIG. 3 is an exemplary block diagram of an audio subsystem (which, in some embodiments, may be one implementation of a Class D amplifier), according to prior art. As shown in FIG. 3, the audio subsystem comprises an input that receives digital audio data, which is an N-bit pulse code modulated (PCM) input signal. The audio subsystem also includes a digital signal processor, referred to as Audio Signal Processor ASP 202, which receives the input signal and generates output data that is configured for use in generating a pulse train driver signal that corresponds to the input signal. The ASP 202 receives the N-bit input signal, and generates an M-bit output, which is provided to a Digital PWM (Pulse Width Modulator) block 204.

The Digital PWM block 204 includes a PWM Controller 212, two PWM driver blocks labeled PWM0 (232) and PWM1 (234), and may contain other logic as well. The PWM Controller 212 calculates edge locations of the pulse train to be generated, and produces two (M−1)-bit outputs. In particular, each of the two (M−1)-bit outputs may represent respective edges of pulses to be generated. The two (M−1)-bit outputs are used by individual pulse width modulators PWM0 and PWM1 to produce the final differential PWM outputs PWM_OUTP and PWM_OUTN. In general, PWM block 204 may comprise a small signal-processing block that operates on the M-bit input data and separates the M-bit input data into two individual streams of M−1 bits each. These (M−1)-bit streams may be independent, or, more specifically, they may have some correlation to each other, while the actual data may differ on an instantaneous pulse-by-pulse basis.

Block 222 comprises logic for handling dead time, as well as a MOSFET Power Output Stage and gate drivers for controlling the MOSFET Power Output Stage. The MOSFET Power Output Stage portion of block 222 may include high power switches, preferably MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The high power switches generate a high-power (amplified) replica of the received pulse train. The MOSFET Power Output Stage portion provides the amplified pulse train to low pass filter 224. As shown, the Output Stage provides a differential pair of output signals, referred to as OUTP and OUTN, which provide two differential pulses per PWM period. The low pass filter 224 performs a low pass filter operation on the differential pulses and provides the two outputs, referred to as OUTP_FILT and OUTN_FILT, to a load, e.g., to a loudspeaker 124.

Adaptive Output Power Limiter

For large input signals, the output load, for example loudspeaker 124 may become susceptible to potential damage. Therefore, it may be desirable to attenuate the output of the amplifier in a controlled manner to protect the load, but without interrupting or compromising the quality of the audio signal. In general, power limiting is used in audio applications to protect the loudspeakers from failures. However, it might be equally desirable to limit output power in a controlled manner in other applications, for example at the output of a switching power supply, or other similar circuits. In audio applications, the aforementioned failures may occur when excessive power is driven into the loudspeaker (e.g. speaker 124) for an extensive amount of time. Traditionally, true power limiting has been implemented by restricting the power delivered to the loudspeaker by measuring the actual current and actual voltage at the output of the amplifier. In one set of embodiments, an adaptive audio power limiter provides a very low cost alternative to present day power limiters.

Output power is determined by equation P=V*I, where V is the output voltage and I is the output current. It follows from the above equation that output power may be limited if either the voltage or the current is used as a feedback variable to limit the total power in the system. In one set of embodiments, a power limiting circuit may be used to measure the output current, generate a control output based on the measured output current, and use the control output to adaptively limit the output power. For example, the control output may be converted to a single signal, e.g. a digital signal, which may be processed by a digital circuit to adaptively limit the power to the loudspeaker without fear of immediate shutdown. Various embodiments of the adaptive power limiter may be used in various applications, for example in an audio subsystem. FIG. 4 shows a more detailed diagram of the audio subsystem shown in FIG. 3, to provide an example of a system/circuit that might benefit for adaptive output power limiting. As shown in FIG. 4, circuit block 222 includes a dead time circuit 422, which provides respective high-side and low-side PWM signals to gate drivers 422, which drive H-Bridge circuit 442, which in turn drives the loudspeaker 124 through external low-pass filter 224.

Traditionally, power stages associated with audio amplifiers have included a fault detection circuit operated to shut down the PWM signals OUTP and OUTN to the H-Bridge 442 based on an over-current event. As a result of this action, the loudspeakers are protected from excessive power. Typically, a fixed threshold is set for the current, above which the current would cause the device to shut down. One example of such a prior art current-shutdown circuit topology is shown in FIG. 5. Latches 514 and 518 are used to provide an overcurrent detection signal OC_DET for the OUTP and OUTN signals, respectively. Current detection circuitry 512 and 516 are used to detect overcurrent conditions based on a comparison of the current in the power stage (I_PWRSTAGE) and the specified current threshold value (I_THRESHOLD). The detection signal is used to respectively gate—in logic gates 520 and 522—the PWM control signals provided from dead time block 422, before the PWM control signals reach the gate drive circuitry 432, resulting in the gate drive signals turning off when the overcurrent condition is detected. As shown in FIG. 5, once the detection signal is latched, the output of gates 520 and 522 remains unasserted (that is, the PWM signals remain low) until the latches 514 and 518 are reset, regardless of the instantaneous state of the OC_DET signal.

The waveforms of interest corresponding to the power limiting implementation, shown in FIG. 5, are illustrated in the timing diagrams of FIG. 6. As illustrated in FIG. 6, the waveform for the expected PWM signal corresponds to the outputs of drivers 232 and 234, and the waveform for the actual PWM signal corresponds to the outputs of logic gates 520 and 522. When the current (i.e. the current in the load, in this case loudspeaker 124) reaches an upper limit threshold, and exceeds that upper limit threshold, the device shuts down. That is, when the current in the power stage reaches an upper limit, the expected PWM value being gated with the overcurrent detection signal results in the actual PWM signal reaching the gate drive circuit 432 residing at a low (deasserted) level, preventing further current from flowing in the power stage.

FIG. 7 shows the circuit diagram of one embodiment of an audio subsystem that includes an improved power limiter circuitry with provisions for adjusting the respective widths of the PWM signal pulses driving the H-Bridge (or half-bridge) 442 circuits, based on the current measured in the power stage. The PWM pulse widths may be adjusted in a variety of different ways. For example, current-control may be used to limit the output power by adjusting the width of the PWM pulses based on the current-level detected in the power stage. In the embodiment shown in FIG. 7, the power limiting circuit may include two current-detection circuits, 512/812 and 516/814, respectively, which may be operated to detect the current through each half of the H-Bridge circuit 442, and compare this current relative to two current-thresholds for each half, instead of just one current-threshold. One comparator, referred to as the outer comparator (512 and 516), may have its threshold set at a fault shutdown level (I_THRESHOLD_OUTER), and may permanently shutdown the output when the output current reaches that threshold level, until the shutdown is lifted or cleared. The other comparator, referred to as the inner comparator (812 and 814), may have its threshold set at a warning level (I_THRESHOLD_INNER), and may provide a control signal to adjust the respective widths of the PWM signal pulses driving the H-Bridge 442 circuits.

As shown in FIG. 7, the output of inner comparator 812 is used to gate—at logic gate 822—the OUTP output provided from dead time circuit 422, while the output of inner comparator 814 is used to gate—at logic gate 820—the OUTN output provided from dead time circuit 422. The respective outputs of gates 822 and 820 are provided as inputs to gates 826 and 824, respectively, which are respectively gated by the outputs from latches 514 and 518 based on the respective comparison results from outer comparators 512 and 516. Because the respective outputs of inner comparators 812 and 814 are not latched, they may be effectively used to clip or scale the PWM signals provided from dead time block 422 for as long as the current is higher than the warning level (I_THRESHOLD_INNER). This is illustrated in FIG. 8, which shows the relevant waveforms for the signals of interest of the embodiment of the output power limiting circuit shown in FIG. 7. The waveform labeled “PWM (Expected)” corresponds to the PWM signal outputs of drivers 232 and 234, while the waveform labeled “PWM (Actual)” corresponds to the PWM signal outputs from logic gates 822 and 820. As seen in FIG. 8, when the output current reaches the lower limit, labeled I_THRESHOLD_INNER in FIG. 7, the output of the inner comparator is asserted, resulting in the instantaneous value of the actual PWM output signal being clipped, in effect scaling the width of the PWM pulse for the duration of the output PWM period. On the next output PWM cycle, if the output current is below the lower limit threshold, the output of the inner comparator is not asserted, therefore the instantaneous value of the actual PWM output signal is not clipped/scaled, until the output current again reaches the lower limit threshold. Accordingly, the inner comparators may be used to scale the PWM pulses in real time per PWM clock cycle. Of course if the output current reaches the upper limit threshold, the output of the outer comparator may set the control latch, and zero out the PWM signals, just as shown in FIG. 6.

In one set of embodiments, each of the thresholds may be programmable. For example, the outer and inner comparators may be programmed with absolute fixed thresholds, as illustrated by diagram 706 in FIG. 9b. In such embodiments, the inner and outer thresholds have a set, specified value against which the current in the power stage may be compared to determine an overcurrent condition. In another set of embodiments, the outer and inner comparators may be programmed relative to an external resistor, as illustrated by diagram 704 in FIG. 9c. In these embodiments, the actual value of the inner and outer threshold current may depend on an external component, such as an external resistor, and may therefore be programmed according to the value of the external component. In yet some other embodiments, the outer comparator may be set to an absolute fixed threshold, while the inner comparator threshold may be programmed according to the value of an external resistor, as illustrated by diagram 702 in FIG. 9a. In these embodiments, the outer threshold may have a set, specified value, while the value of the inner threshold may be programmed according to the value of the external component. Overall, the thresholds may be set as desired, based on the specific requirements of the system. Additional thresholds may also be configured, and/or added as desired.

The topology of a further improved and even more flexible power limiting circuit according to another embodiment is illustrated in FIG. 10. The power limiting circuitry shown in FIG. 10 may also include warning current-detection blocks 812 and 814 in addition to detection blocks 512 and 516, to monitor the current and detect when the current rises above a specified warning threshold level, again designated as an inner threshold (I_THRESHOLD_INNER) as previously described. Comparison, blocks 812 and 814 may generate a digital feedback signal indicative of the current having exceeded the inner threshold value, and further indicative of the length of time the current has exceeded the inner (warning) threshold. However, instead of using the respective outputs of blocks 812 and 814 to simply gate the PWM outputs provided by dead time circuit 422, the signals generated by blocks 812 and 814 are provided to respective controllers, e.g. respective digital controllers 934 and 944 for further action.

The digital controller (934/944), labeled “pulse-width detector” may be a digital signal processor (DSP) or a microprocessor, or it may be implemented as glue logic, or a combination of hardware and software, and may operate to measure the width of the signal provided by blocks 812/814. The resulting signals from pulse-width detectors 934/944 are then filtered by respective filters 932 and 942, which are coupled to processing elements 934/944 to receive the respective outputs therefrom. In the embodiment shown in FIG. 10, filters 932 and 942 are shown as averaging infinite impulse response (IIR) filters. Other embodiments may use other filters. The filtered results are provided to respective scalers 936 and 946 to scale the PWM pulse accordingly. Scaler/calculators 936 and 946 may perform the scaling operation(s) using a SAR (successive approximation register) algorithm, a linear reduction, or any other specified suitable algorithm. The respective outputs from scaler/calculators 936/946 may be multiplied with the audio signal, which may thus be digitally attenuated based on the length of time the output current exceeds the inner threshold.

As shown in FIG. 10, when the current exceeds the upper limit, the device may be immediately shut off, by gating the outputs from dead time block 422 with the overcurrent detection signals generated through blocks 512/516 and 514/518. Specifically, the high-side control signal from dead time block 422 may be gated at logic gate 922 by the output of latch 514, and the low-side control signal from dead time block 422 may be gated at logic gate 920 by the output of latch 518. However, if the lower limit (I_THRESHOLD_INNER) is exceeded, then the power limiting circuit may attempt to scale the pulse either until the current does not exceed the lower limit (I_THRESHOLD_INNER) or until the duty cycle of the PWM pulse is equal to zero, based on the current. Effectively, the power limiting circuit may clip/scale the PWM signal for the PWM period where the first current excursion occurred, and may release the PWM pulse for the next cycle. The scaling of the PWM signals may include scaling the common-mode between the signals, illustrated in FIG. 13, which shows the timing diagrams for the expected and scaled PWM signals.

As previously mentioned, to obtain the effect illustrated in FIG. 13, a current detection circuit may be implemented in a power limiting circuit, for example in the switching power stage. FIG. 10 shows detection blocks 512/812 and 516/814. In some embodiments, the current detection for the inner threshold, i.e. the current detection in block 812 and 814 may be performed through the use of a multi-bit analog-to-digital converter (ADC). To save area and power, the ADC circuit may be a current comparator that outputs a pulse when/while the detected/measured current is higher than a programmable threshold, in this case the inner threshold. The pulses generated by detection blocks 812/814 may be edge-detected, and their respective widths measured relative to a higher frequency clock in blocks 934 and 944, respectively. The output of the ADC (i.e. detection blocks 934 and 944) may be filtered by filter blocks 932 and 942, respectively, to remove any high frequency noise.

FIG. 11 shows the relevant waveforms illustrating the behavior of the power limiter circuit implementation shown in FIG. 10, according to one embodiment. The expected PWM signal in this case represents the PWM signals, as PWM controller 212 would produce them if the signals were not scaled/adjusted. The CurLimitPulse signal corresponds to the output from the detection block for the inner threshold. That is, it is representative of the output produced by detection block 812 and detection block 814. As mentioned above, in one set of embodiments, CurLimitPulse is a pulse having a width that corresponds to the duration of the time period during which the detected/measured current is higher than the inner threshold. As seen in FIG. 11, when the output current is over the lower limit threshold, the CurLimitPulse signal is asserted. However, unlike the actual PWM waveform shown in FIG. 8, the actual PWM waveform shown in FIG. 11 indicates that the expected PWM signal/pulse isn't simply clipped for the remainder of the PWM clock signal as soon as the output current reaches the lower threshold limit, but is instead scaled according to the output of scaler calculator 936/946 (generated based on the CurLimitPulse signal), by adjusting/modifying the output from audio signal processor 202, and providing the adjusted value to PWM controller 212. The gradual and programmable time to scale the PWM signal rather than a hard clip of the PWM signal will dampen the undesired audible artifacts of a power limiting circuit. The actual PWM signal in FIG. 11 corresponds to the outputs provided by PWM driver blocks 232 and 234.

In one set of embodiments, the filters 932 and 942 may also serve as the scaler control. That is, filters 932/942 and scaler calculators 936/946 may respectively be implemented as a single processing block to provide the multiplier value with which the output from audio signal processor 202 is multiplied to scale the PWM pulses. The type of filter used in this instance may be a fast attack and slow release filter. The power limiter may attack fast to ensure that the fault shutdown event does not occur. The undesired audible effects will be less audible, since the actual audio may be loud when the protection afforded by the power limiter circuit is required. The release may be slow to ensure that the volume change is less noticeable or audible since the actual audio will be less loud because there will be less current required to support the actual audio. The architecture of this fast attach and slow release filter may be implemented with a single, reprogrammable IIR filter in which the value of the integrator 952 is shifted by a factor of 2, either smaller or larger, depending on the instantaneous change of modes, which include attack to release and release to attack. This is show in the embodiment of the IIR filter in FIG. 12, where the attack and release bandwidth is determined in block 954. This ability to instantaneously change the state of the integrator 952 either accelerates the IIR processing, hence fast attack, or configures the IIR as a decelerator, hence a slow attack rate, with the adjustment made (taking place) at the beginning of a filter mode change. However, two IIR filters and/or other filtering techniques may also be used. The filter output Z(n) may be ‘1’ when there is no scaling necessary, which may infer a multiply by 1. However, when the filter is active, the output Z(n) may compress or attenuate the audio to a smaller value.

Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. A signal processing system comprising:

signal processing circuitry configured to receive an input signal, generate a driver signal representative of the input signal, and use the driver signal to generate an output signal; and

power limiting circuitry configured to:

assert a first signal in response to an output current reaching a first threshold, wherein the output current is produced by the output signal;

derive a control value from the first signal, wherein the control value corresponds to a time duration for which the first signal is asserted;

attenuate the output signal by scaling the driver signal according to the control value.

2. The signal processing system of claim 1, wherein the signal processing circuitry is an amplifier circuit, wherein the input signal is an audio signal, and wherein the output signal is an amplified version of the audio signal.

3. The signal processing system of claim 1, further comprising a speaker coupled as a load to the signal processing circuitry, wherein the output current is conducted by the speaker.

4. The signal processing system of claim 1, wherein the power limiting circuitry comprises:

a comparator having an output configured to provide the first signal responsive to the comparator comparing the output current to the first threshold;

a digital circuit configured to generate a numeric value based on the first signal, wherein the numeric value corresponds to the time duration for which the first signal is asserted; and

a filter circuit configured to generate the control value from the numeric value.

5. The signal processing system of claim 4, wherein the digital circuit is a counter that is clocked with a clock signal having a specified frequency higher than a frequency of the driver signal;

wherein the counter is configured to: count when the first signal is asserted; stop counting when the first signal is deasserted; and provide a result of the count as the numeric value.

6. The signal processing system of claim 4, wherein the filter circuit is an infinite impulse response (IIR) filter configured to average the numeric value, and provide the control value based on the averaged numeric value.

7. The signal processing system of claim 6, wherein the IIR filter is a fast attack and slow release IIR filter.

8. The signal processing system of claim 7, wherein the IIR filter comprises programmable settings for generating a rate of release.

9. The signal processing system of claim 1, wherein the power limiting circuitry is further configured to:

deassert the driver signal in response to the output current reaching a second threshold.

10. The signal processing system of claim 9, wherein the second threshold is higher than the first threshold.

11. The signal processing system of claim 1, wherein the driver signal is a pulse-width modulated (PWM) signal;

wherein in scaling the driver signal according to the control value, the power limiting circuit is configured to adjust a pulse-width of the PWM signal.

12. A power limiting circuit for limiting output power associated with an output current resulting from an output signal generated according to a driver signal, which is derived from an input signal, the power limiting circuit comprising:

a comparator configured to assert a comparator output responsive to the output current exceeding a first threshold value; and

a scaler circuit configured to: derive a scaler value from the comparator output; and attenuate the output signal by multiplying the scaler value with the input signal.

13. The power limiting circuit of claim 12, wherein the scaler circuit is configured to generate the scaler value based on a time duration for which the comparator output is asserted.

14. The power limiting circuit of claim 12, wherein the scaler comprises:

a digital circuit configured to generate a numeric value corresponding to a time duration for which the comparator output is asserted; and

a filter circuit configured to generate the scaler value from the numeric value.

15. The power limiting circuit of claim 14, wherein the digital circuit is a counter that is clocked with a clock signal having a specified frequency higher than a frequency of the driver signal;

wherein the counter is configured to: count when the comparator output is asserted; stop counting when the comparator output is deasserted; and provide a result of the count as the numeric value.

16. The power limiting circuit of claim 14, wherein the filter circuit is an infinite impulse response (IIR) filter configured to average the numeric value, and provide the scaler value based on the averaged numeric value.

17. The power limiting circuit of claim 16, wherein the IIR filter is a fast attack and slow release IIR filter.

18. The power limiting circuit of claim 17, wherein the IIR filter comprises programmable settings for generating a rate of release.

19. The power limiting circuit of claim 14, further comprising:

a second comparator configured to deassert the driver signal in response to the output current reaching a second threshold.

20. The power limiting circuit of claim 19, wherein the second threshold is higher than the first threshold.

21. A method for limiting output power in an audio amplifier, the method comprising:

generating an output signal based on an input signal;

the output signal resulting in an output current;

asserting a control signal when the output current is over a specified first threshold;

generating a numeric value corresponding to a time duration for which the control signal is asserted;

averaging the numeric value;

scaling the averaged numeric value; and

attenuating the output signal by multiplying the scaled averaged numeric value with the input signal.

22. The method of claim 21, wherein said generating the numeric value comprises:

counting cycles of a clock signal while the control signal is asserted; and

providing a number of counted clock cycles as the numeric value.

23. The method of claim 21, wherein said averaging the numeric value comprises filtering the numeric value using an infinite impulse response (IIR) filter.

24. The method of claim 21, wherein said scaling the averaged numeric value comprises performing one of:

a successive approximation register algorithm using the averaged numeric value as input; and

a linear reduction using the averaged numeric value as input.

25. The method of claim 21, wherein said generating the output signal based on the input signal comprises:

generating a pulse train representative of the input signal; and

generating the output signal by driving a power stage with the pulse train;

wherein the method further comprises adjusting the pulse train responsive to said multiplying the scaled averaged numeric value with the input signal.