Abstract: A feedback control system, e.g. a voltage regulator, may include a control stage controlling an output stage that generates an output. The control stage may generate a control signal, e.g. a pulse-width modulated signal, having a duty-cycle and a switching frequency, and adjust the switching frequency when a present value of the duty-cycle differs from a most recent previous value of the duty-cycle, until the duty-cycle starts increasing, while also adjusting the duty-cycle according to the output. By adjusting the switching frequency, the (power) efficiency of the system may be optimized also regulating the output. The feedback system may also adjust the switching frequency according to an alternate algorithm to improve but not necessarily optimize the power efficiency by scaling a programmed frequency value using a scaling factor that is a function of a maximum duty-cycle value, a present frequency value, the programmed frequency value, and a minimum frequency value.

Abstract: An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the absolute moment in time of the edge transition of the controlling signals to the respective sets of switches. The PWMs may include a decrementor that counts down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count when the next sample is present. The PWM output may correspond to the counter value, outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the delay mechanism may be based on adjusting the decode value to determine when the PWM should initialize to the next data sample.

Abstract: An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the respective edge transitions of the controlling signals provided to the respective sets of switches. The PWMs may count down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count for each new sample, with the PWM outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the decode value may be adjusted to determine when the PWM should initialize to the next data sample.

Abstract: An amplifier may include two or more pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A positive DC-offset based on the source signal may be applied to the pulse-width modulator controlling one respective set of switches, and an equal value negative DC-offset may be applied to the pulse-width modulator controlling the other respective set of switches, to provide an effective offset between the respective points in time of the rising/falling edges of the different pulse-width modulated control signals. The addition of alternating positive and negative DC-offset values doesn't affect the output load, and doesn't degrade the signal. The DC-offsets may be added at a frequency selected to be beyond the signal baseband, and the value of the small input signal level may be determined using an RMS level comparator or similar measurement technique.

Abstract: Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.

Abstract: A distributed power management system may include a communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus, and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus.

Abstract: A switching audio amplifier may include a modulation enhancement feature, in which the pulse-width modulated (PWM) signals driving the output stage are reduced or increased by identical step sizes to create an auxiliary PWM scheme representative of an idle (low-power) state of the input signal. The PWM signals, provided to a full-bridge power stage circuit for example, may be thereby reduced to another state to reduce power dissipation in a switch-mode power supply. By incrementally adjusting the PWM duty-cycle identically in all PWM signals to a value less than (or up to) 50%, the amount of current dissipated in the output load may be effectively controlled. The PWM pulses may be adjusted up or down, while checking for saturation corresponding to both minimum and maximum pulse-widths. A dampener circuit may be used to set the time between incremental adjustments, to further reduce audible pops and clicks.

Abstract: An amplifier may include two or more pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A positive DC-offset based on the source signal may be applied to the pulse-width modulator controlling one respective set of switches, and an equal value negative DC-offset may be applied to the pulse-width modulator controlling the other respective set of switches, to provide an effective offset between the respective points in time of the rising/falling edges of the different pulse-width modulated control signals. The addition of alternating positive and negative DC-offset values doesn't affect the output load, and doesn't degrade the signal. The DC-offsets may be added at a frequency selected to be beyond the signal baseband, and the value of the small input signal level may be determined using an RMS level comparator or similar measurement technique.

Abstract: An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the respective edge transitions of the controlling signals provided to the respective sets of switches. The PWMs may count down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count for each new sample, with the PWM outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the decode value may be adjusted to determine when the PWM should initialize to the next data sample.

Abstract: An output power limiter system (PLS) for audio amplifiers may be designed as a feedback control system for protection of the load and/or quality of the audio experience. The PLS may use comparator to sense the output current, compare it to a specified threshold, and assert a signal when the output current reaches and exceeds the specified threshold. The output signal from the comparator may enable a counter that is clocked with a high frequency clock to begin counting to measure the pulse-width of the comparator output. The output of the counter may be averaged through a fast attack and slow release infinite impulse response (IIR) filter having programmable settings to generate a rate of attenuation or rate of release that adjusts a gain correction in terms of decibels (dB). The output of the IIR filter may then be used for attenuating the output current.

Abstract: Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.

Abstract: Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.

Abstract: A distributed power management system may include a communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus. The plurality of POL regulators may autonomously arbitrate a new master assignment, when a POL regulator operating as a master device drops out of regulation when a fault occurs, the respective phase of the master device is dropped, and/or the communication interface of the master device to the communication bus fails.

Abstract: A distributed power management system may include a digital communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and each POL regulator may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus. Each POL regulator may autonomously add and drop its phase as required by the system, by sequentially manipulating a pulse width of a couple of gate signals configured to respectively control a high-side field effect transistor (FET) and low-side FET in the POL regulator's output stage.

Abstract: The operation of a voltage regulator (or point-of-load regulator) may be optimized, by performing diode emulation using the low-side output transistor (LS FET). The voltage regulator may be monitored for a specified trigger event, which may include an averaged value of the load current dropping below a threshold value, and upon recognizing the trigger event, one or more of a number of possible diode emulation algorithms may be enabled. In one algorithm, the duty-cycle of the LS FET control signal may be set to a specified value, then adjusted until the duty-cycle of the high-side output transistor (HS FET) control signal settles and steady state is reached. The duty-cycle of the LS FET control signal may then be adjusted, and the duty-cycle of the HS FET control signal monitored, until the monitoring indicates that the duty-cycle of the HS FET control signal has reached a minimum value, thereby optimizing operation of the voltage regulator with respect to power loss.

Abstract: A method for optimizing operation of a feedback system may include generating a control signal according to a control parameter, regulating an output of the feedback system via the control signal, and monitoring the control parameter. In response to the monitoring indicating that the present value of the control parameter is outside a specific range of values, a first parameter that impacts an operating characteristic of the feedback system may be adjusted until the present value of the control parameter is within the specific range of values. The specific range of values of the control parameter may correspond to a target level of the operating characteristic of the feedback system with respect to the first parameter.

Abstract: Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.

Abstract: A distributed power management system may include a communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus, and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus.

Abstract: A distributed power management system may include a communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus. The plurality of POL regulators may autonomously arbitrate a new master assignment, when a POL regulator operating as a master device drops out of regulation when a fault occurs, the respective phase of the master device is dropped, and/or the communication interface of the master device to the communication bus fails.

Abstract: A distributed power management system may include a digital communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current. Each POL regulator may have a respective phase in the current sharing configuration, and each POL regulator may transmit and receive information over the bus according to a bus communication protocol corresponding to the bus. Each POL regulator may autonomously add and drop its phase as required by the system, by sequentially manipulating a pulse width of a couple of gate signals configured to respectively control a high-side field effect transistor (FET) and low-side FET in the POL regulator's output stage.