TURBO DECODER METRICS INITIALIZATION

Abstract

Disclosed are various embodiments that provide turbo decoding implemented as at least a portion of baseband processing circuitry. A turbo decoder may obtain a data block associated with a transmission time interval, the data block comprising a sequence of bits, the data block being encoded according to a coding rate. An alpha operation is performed on the data block for a first decoding iteration to generate first alpha decode data, the alpha operation for the first decoding iteration being performed continuously. An alpha operation is performed on the data block for a second decoding iteration to generate second alpha decode data, the alpha operation for the second decoding iteration being performed according to a set of alpha evaluation windows. The initialization of the alpha windows during the second alpha decode may be derived from the alpha state data that is stored in memory from the first alpha decode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to, and the benefit of, U.S. Provisional patent application entitled “CELLULAR BASEBAND PROCESSING,” having Ser. No. 61/565,864, filed on Dec. 1, 2011, and U.S. Provisional patent application entitled “CELLULAR BASEBAND PROCESSING,” having Ser. No. 61/568,868, filed on Dec. 9, 2011, both of which are incorporated by reference in their entirety.

BACKGROUND

Cellular wireless communication technology involves many wireless mobile devices communicating over a cellular network through base stations. For a wireless mobile device communicating in a cellular network, various channel conditions may affect the quality of the wireless signal received at the wireless mobile device. Wireless signals may be encoded and redundantly transmitted to a wireless mobile device to address varying channel conditions. Accordingly, wireless mobile devices may be equipped to decode the encoded wireless signals transmitted over the cellular network. The decoding process requires resources, such as memory and computing resources.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a drawing of a receiver system according to various embodiments of the present disclosure.

FIG. 2 is a drawing of an example of an operation of a turbo decoder module implemented within the receiver system of FIG. 1 according to various embodiments of the present disclosure.

FIG. 3 is a drawing of an example of an operation of a turbo decoder module implemented within the receiver system of FIG. 1 according to various embodiments of the present disclosure.

FIG. 4 is a flowchart illustrating one example of functionality implemented as portions of baseband processing circuitry of the receiver system of FIG. 1 according to various embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure relates to performing a turbo decoding process on data received in a wireless receiver system. The turbo decoding process may involve performing complete decoding of a data block for multiple times, each time constituting a decoding iteration. Each iteration involves completely decoding the data block by implementing an alpha operation and beta operation. Alpha operations and/or beta operations may be implemented as either a continuous process or as a windowed process.

Various embodiments of the present disclosure are directed to alternating between a continuous process and a windowed process for the alpha operations as well as alternating between a continuous process and a windowed process for the beta operations. Furthermore, state value data derived from a current iteration may be used to initialize state value data for subsequent iteration. As at least one benefit of the subject matter in the present disclosure, processing resources and or memory resources may be reduced or otherwise minimized.

With reference to FIG. 1, shown is a receiver system 100 according to various embodiments. The receiver system 100 may be implemented as at least a portion of a wireless communication system of a wireless device. The wireless device may be, for example, a laptop computer, notepad, notebook, ultrabook, tablet, cellular device, or any other device configured to receive wireless signals over a network. The receiver system 100 may be configured to receive wireless signals transmitted over a network. Wireless signals, for example, may express digitally formatted information that has been mixed and modulated by carrier signals to facilitate wireless communication. To this end, the receiver system 100 is configured to convert received wireless signals into a digital format. The receiver system 100 comprises a receiver filter module 104, an antenna 107, a low noise amplifier (LNA) 111, a down conversion module 114, a filtering/gain module 116, an analog-to-digital converter (ADC) 119, baseband processing circuitry 123, or any other component that facilitates wireless reception.

The antenna 107 may receive inbound wireless signals transmitted from a remote device such as, for example, a base station. The base station may comprise a portion of a remote transmitter system. The receiver filter module 104 is communicatively coupled to the antenna such that the receiver filter module 104 filters out frequencies to facilitate wireless communication. The LNA 111 receives the filtered wireless signal and amplifies this signal to produce an amplified inbound wireless signal. The LNA 111 provides the amplified inbound wireless signal to the down conversion module 114 which produces a low intermediate frequency (IF) signal or baseband signal. For example, the down conversion module 114 may use a local oscillator to down convert the amplified inbound wireless signal. The filtering/gain module 116 may adjust the gain and/or filter the IF or baseband signal. The ADC 119 may format the IF or baseband signal to the digital domain. The ADC 119 produces a digital signal that contains the information expressed by the inbound wireless signal.

The baseband processing circuitry 123 demodulates, demaps, descrambles, and/or decodes the digital signal to recapture the information expressed in the inbound wireless signal in accordance with a wireless communication standard or standards used in the receiver system 100. In various embodiments, the baseband processing circuitry 123 is implemented as at least a portion of a microprocessor. The baseband processing circuitry 123 may be implemented using one or more circuits, one or more microprocessors, application specific integrated circuits, dedicated hardware, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, or any combination thereof. In yet other embodiments, the baseband processing circuitry 123 may include one or more software modules executable within one or more processing circuits. The baseband processing circuitry 123 may further include memory configured to store instructions and/or code that causes the baseband processing circuitry 123 to execute data communication functions.

The baseband processing circuitry 123 may comprise a turbo decoder module 139, memory, and any other component or module for facilitating the functionality of the baseband processing circuitry 123.

The turbo decoder module 139 is configured to process data blocks. A data block may express information received from the antenna 107, where the information is formatted as a sequence of bits in the digital domain. A data block may be associated with data received during a transmission time interval (TTI). A data block may represent all the data received for a given TTI or a portion of the data received for a given TTI. The size of the data block may be dictated by one or more wireless protocols that facilitate data communication of the receiver system 100.

A data block may be encoded according to a number of turbo encoding protocols. For example, a data block may be encoded according to a number of finite states. Decoding such a data block may require performing a number of decoding iterations based on the number of finite states used in the encoding process. As another example, each data block may be associated with a particular coding rate. The coding rate indicates the amount of coding used to encode a particular data block. For example, a high coding rate may indicate that a large number of parity bits were punctured after encoding a particular data block. High coding rates may be used in response to good signal conditions to provide higher throughput. To this end, a receiver system 100 that receives a data block associated with a high coding rate may be required to perform decoding operations that require more processing resources.

In various embodiments, the turbo decoder module 139 is configured to perform a Bahl, Cocke, Jelinek, Raviv (BCJR) algorithm for decoding the data block. The turbo decoder module 139 may perform forward probabilities (alpha) operations and backward probabilities (beta) operations on each processed on a data block. Alpha operations are performed in order that corresponds to the order of sequence of bits starting from a beginning bit of the data block to an ending bit of the data block. Beta operations are performed in an order that corresponds to a reverse direction with respect to the sequence of bits of the data block. That is to say, the beta operation begins with an ending bit of the data block and ends with a beginning bit of the data block.

A complete decoding operation performed by the turbo decoder module 139 comprises performing an alpha operation and a beta operation on the entire data block. Furthermore, the turbo decoder module 139 may be configured to perform a number of decoding iterations on the data block. Each iteration is a complete decoding operation. To execute a full decoding operation, a decoding iteration is divided into a first half-iteration operation and a second half-iteration operation. The first half-iteration operation may be implemented by operating on received data associated with a first constituent encoder and the second half-iteration operation may be implemented by operating on received data associated with a second constituent encoder. The number of decoding iterations performed by the turbo decoder module 139 may correlate with the quality of the radio channel.

In response to performing a decoding iteration, the results of alpha operation and the results of the beta operations are combined to generate likelihood data for facilitating error detection. For example, likelihood data may be log likelihood ratio (LLR) data. The likelihood data effectively allows a turbo decoder module 139 to make a best guess of the data intended to be transmitted to the receiver system 100 based on the data block that was actually received by the receiver system 100.

The turbo decoder module 139 may comprise an error detection module. In various embodiments, the error detection module is configured to perform a cyclic redundancy check (CRC) on a decoded data block data such as, for example, LLR data. A CRC operation may be performed to determine whether a retransmission of the data block is required or whether new, subsequent data block is to be transmitted to the receiver system 100. For example, if the CRC is passed, new data represented in a subsequent TTI is processed. However, of the CRC is failed, then data represented by the current TTI may be retransmitted and analyzed by the baseband processing circuitry 123. In various embodiments, the receiver system 100 continues to request retransmissions until a maximum number of CRC failures occur.

The baseband processing circuitry 123 comprises memory 146. The memory 146 may be configured to store a data block subject to turbo decoding by a turbo decoder module 139. Furthermore, the memory 146 may be configured to store the results of alpha and beta operations, alpha and beta state values, LLR calculations, or any other output data generated by the turbo decoder module 139. To this end, the turbo decoder module 139 is communicatively coupled to the memory 146 to facilitate various read/write operations in the execution of turbo decoding processes.

Turning now to FIG. 2, shown is a drawing of an example of an operation of a turbo decoder module 139 implemented within the receiver system 100 of FIG. 1 according to various embodiments of the present disclosure. FIG. 2 provides a non-limiting example of performing turbo decoding on a data block 209.

The non-limiting example of FIG. 2 depicts an alpha operation 214 and a beta operation 217. By performing the alpha operation 214 and the beta operation 217 on the data block 209, one complete decoding iteration 223 is performed. To this end, a full iteration includes two half iterations and includes decoding operations associated with the received data associated with both the first and section constituent encoders. As seen in the non-limiting example of FIG. 2, the alpha operation 214 is performed continuously for the data block 209. In this respect, the alpha operation 214 is an un-windowed operation performed without the use of any evaluation windows. Furthermore, the alpha operation 214 is performed in a direction that correlates with the direction associated with the sequence of bits in the data block 209.

The beta operation 217 depicted in the non-limiting example FIG. 2 represents a discontinuous operation. A discontinuous operation is one that employs a series of evaluation windows 227. To this end, a data block 209 is segmented into a series of portions, each portion being associated with an evaluation window 227. Each evaluation window 227 evaluates sequential segments of a data block 209. By segmenting the data block 209 into a set of evaluation windows 227, the beta operation 217 is performed on the data block 209 in a manner that is discontinuous or otherwise windowed. As seen in FIG. 2, each evaluation window 227 of the beta operation 217 is performed in a reverse direction with respect to the direction associated with the sequence of bits of the data block 209.

In various embodiments, the size of each evaluation window 227 is a fixed length in terms of a number of bits. For example, if the evaluation window 227 as a length of 100 bits and then the first evaluation window 227 of the beta operation 217 begins with bit number 99 and ends with bit number zero. The next evaluation window 227 begins with bit number 199 and ends with bit number 100. The last evaluation window 227 has a length of a remaining number of bits to complete the processing of the data block 209.

When implementing a windowed beta operation 217, each evaluation window 227 may need to be initialized with an initial state value. In the non-limiting example of FIG. 2 each evaluation window 227 of the beta operation 217 is initialized by using a training window 233. The training window 233 may be referred to as a warm-up window or an initializing window. The length of the training window 233 may correlate with the coding rate associated with the data block 209. For example, a data block 209 associated with a high coding rate employs a small number of parity bits. To this end, a larger training window 233 may be required to initialize each evaluation window 227. Through the use of training windows 233, an increase in computing resources may be needed.

While FIG. 2 provides one non-limiting example of using evaluation windows 227 for beta operations 217, various embodiments are not so limited. In various embodiments, evaluation windows 227 may be used for alpha operations 214, as is discussed in further detail below.

Moving to FIG. 3, shown is an example of an operation of a turbo decoder module 139 implemented within the receiver system 100 of FIG. 1 according to various embodiments of the present disclosure. FIG. 3 provides a non-limiting example of performing turbo decoding on a data block 209 for series of decoding iterations 307.

For example, FIG. 3 depicts a turbo decoder module 139 that performs four decoding iterations 307a-d. Furthermore, each decoding iteration 307a-d may represent a half-iteration operation associated with the first constituent encoder and a half-iteration operation associated with the second constituent encoder.

Each decoding iteration 307 includes performing an alpha operation 214 and a beta operation 217 on the data block 209. For example, the first decoding iteration 307a includes a first alpha operation 214a and a first beta operation 217a. In the non-limiting example of FIG. 3, for the first decoding iteration 307a, the alpha operation 214a is performed continuously or otherwise without the use of evaluation windows 227 (FIG. 2) and the beta operation 217a is performed discontinuously using evaluation windows 227. Furthermore, in the non-limiting example of FIG. 3, the second decoding iteration 307b involves performing a second alpha operation 214b and a second beta operation 217b. The second alpha operation 214b is performed discontinuously using evaluation windows 227 and the second beta operation 217b is performed continuously or otherwise performed without the use of evaluation windows 227.

In various embodiments of the present disclosure, alpha operations 214a, c are performed continuously for even decoding iterations 307a, c and alpha operations 214b, d are performed discontinuously using evaluation windows 227 for odd decoding iterations 307b, d. Furthermore, beta operations 217b, d are performed continuously for odd decoding iterations 307b, d and beta operations 217a, c are performed discontinuously using evaluation windows 227 for even decoding iterations 307a, c. To this end, the use of continuous alpha operations 214a, c and discontinuous alpha operations 214b, d alternate for each decoding iteration 307a-d. And, the use of continuous beta operations 217b, d and discontinuous beta operations 217a, c alternate for each decoding iteration 307a-d.

In various embodiments of the present disclosure, the performance of windowed alpha operations 214b-d and windowed beta operations 217a, c on the data block 209 excludes the use of a preceding training window 233 (FIG. 2). Put another way, each evaluation window 227 is not initialized according to a corresponding training window 233, as seen in the non-limiting example of FIG. 2. In various embodiments, each evaluation window 227 is initialized according to a default state value or a state value derived from a previous decoding iteration.

For example, for the first decoding iteration 307a, each beta evaluation window 227 is initialized according to a default state value 341. In various embodiments, the default state value 341 is a constant value used to initialize each evaluation window 227 of a beta operation 217a of the first decoding iteration 307a. In this respect, the default state value 341 is a predetermined value used to initialize an evaluation window 227.

In various embodiments of the present disclosure, decoding iterations 307b-d, subsequent to the first decoding iteration 307a, may use windowed alpha operations 214b, d or windowed beta operations 217c with evaluation windows 227 that are initialized according to state values derived from previous decoding iterations 307a-c. For example, alpha state values 343 associated with the continuous alpha operation 214a of the first decoding iteration 307a may be used to initialize the evaluation windows 227 of the windowed alpha operation 214b of the second decoding iteration 307b. Beta state values 346 associated with the continuous beta operation 217b of the second decoding iteration 307b may be used to initialize the evaluation windows 227 of the windowed beta operation 217c of the third decoding iteration 307c. Alpha state values 349 associated with the continuous alpha operation 214c of the third decoding iteration 307c may be used to initialize the evaluation windows 227 of the windowed alpha operation 214d of the fourth decoding iteration 307d.

In various embodiments of the present disclosure, the turbo decoder module 139 is configured to determine state value data 343, 346, 349 by indexing the decoding results derived from the continuous alpha operations 209a-c or continuous beta operations 217b, d. For example, in the first decoding iteration 307a, the turbo decoder module 139 identifies a set of positions associated with performing the continuous alpha operation 214a. Each position in the set of positions corresponds to a start point of a respective evaluation window 227 of the windowed alpha operation 214b of the following decoding iteration 307b. Each position is indexed in order to identify a set of alpha state values 343. A position of a particular state value 343, 346, 349 may be expressed in terms of a bit number associated with the sequence of bits of a particular data block 209. Thus, the start position of each evaluation window 227 corresponds to a particular bit position of the sequence of bits of the data block 209.

Each state value 343, 346, 349 may be stored as state value data 343, 346, 349 in memory 146 (FIG. 1) accessible to the turbo decoder module 139 of the baseband processing circuitry 123 (FIG. 1). When performing a subsequent decoding iteration 307b-d, state value data 343, 346, 349 may be loaded from memory 146 to the turbo decoder module 139 in order to initialize windowed alpha operations 214b, d and/or windowed beta operations 217c. To this end, each evaluation window 227 excludes a preceding training window 233 used for initializing the corresponding evaluation window 227.

In various embodiments of the present disclosure, for a particular evaluation window 227, decode data generated from a continuous alpha operation 214a, c is stored in a memory 146. This alpha decode data associated with the particular evaluation window 227 is combined with corresponding decode data generated from a windowed beta operation 217a, c to generate log likelihood ratio data associated with the particular window. Moreover, the beta decode data associated with the particular evaluation window 227 is not stored in the memory 146. Rather, the beta decode data is combined with the stored alpha decode data “on the fly.” That is to say, only results from the continuous operation are stored in the memory 146.

Furthermore, it is sufficient for the size of the memory 146 to be large enough to store decode data associated with the execution of a single evaluation window process. In various embodiments, the memory 146 is cleared of decode data associated with a current evaluation window 227 to provide memory capacity for processing a portion of the data block 209 associated with the next evaluation window 227.

Similarly, for a particular evaluation window 227, decode data generated from a continuous beta operation 217b, d is stored in a memory 146. This beta decode data associated with the particular evaluation window 227 is combined with corresponding decode data generated from a windowed alpha operation 214b, d to generate log likelihood ratio data associated with the particular window.

Although the non-limiting example of FIG. 3 depicts a first decoding iteration 307a to include a continuous alpha operation 214a and a discontinuous beta operation 217a, various embodiments of the present disclosure are directed to implementing a discontinuous alpha operation 214 and a continuous beta operation 217 for the first decoding iteration 307.

The non-limiting example of FIG. 3 also depicts an order for applying evaluation windows 227. Evaluation windows 227 may effectively slide from one end of the data block 209 to the other end of the data block 209. In this respect, the evaluation window 227 facilitates performing an alpha/beta operation 214, 217 in sequence across a data block 209. As the evaluation windows 227 slide across the data block 209, the evaluation windows 227 may be configured to slide from the beginning of the data block 209 to the end of the data block 209 or slide from the end of the data block 209 to the beginning of the data block 209. Whether an evaluation window 227 performs a forward alpha operation 214 or a reverse beta operation 217, the order of applying evaluation windows 227 is independent of the type of operation 214, 217 performed by the evaluation windows 227.

In various embodiments of the present disclosure, the windowed beta operations 217a, c of the first decoding iteration 307a and third decoding iteration 307c are performed using evaluation windows 227 that are ordered according to a direction that correlates with the direction of the sequence of bits of the data block 209. That is to say, the evaluation windows 227 of the beta operations 217a,c slide from the beginning of the data block 209 to the end of the data block 209.

In various embodiments of the present disclosure, the windowed alpha operations 214b, d of the second decoding iteration 307b in the fourth decoding iteration 307d are performed using evaluation windows 227 that are ordered according to a direction that is reverse with respect to the sequence of bits of the data block 209. In this respect, the evaluation windows 227 of the alpha operations 214b, d slide from the end of the data block 209 the beginning of a data block 209.

Turning now to FIG. 4, shown is a flowchart illustrating one example of functionality implemented as portions of the baseband processing circuitry 123 in a receiver system 100 of FIG. 1 according to various embodiments of the present disclosure. It is understood that the flowchart of FIG. 4 provides merely an example of the many different types of functional arrangements that may be employed to implement the operation of the portion of the logic executed by the baseband processing circuitry 123 as described herein. As an alternative, the flowchart of FIG. 4 may be viewed as depicting an example of steps of a method implemented in the baseband processing circuitry 123 according to one or more embodiments. The baseband processing circuitry of 123 may be implemented using a turbo decoder module 139 (FIG. 1) in data communication with memory 146 (FIG. 1).

Beginning with reference number 403, the baseband processing circuitry 123 obtains a data block such as, for example, the data block 209 of FIG. 2. The data block 209 may be received in accordance with a particular TTI. The data block 209 is encoded according to a particular coding rate specified by a transmitter system that is configured to wirelessly communicate with the receiver system 100. The encoding process used to encode the data block 209 may employ a finite state machine that encodes the data block 209 according to a predetermined number of states. The baseband processing circuitry 123 is configured to apply a turbo decoder module 139 to decode the data block 209.

At reference number 406, the baseband processing circuitry 123 performs a first decoding iteration on the data block 209. The first decoding iteration 307 (FIG. 3) may be an even decoding iteration 307 that includes an alpha operation 214 (FIG. 2). The alpha operation 214 is performed on the data block 209 in a forward direction with respect to the sequence of bits in the data block 209. Furthermore, the alpha operation 214 is performed continuously. That is to say, the alpha operation 214 excludes the use of evaluation windows 227 (FIG. 2) such that the alpha operation 214 of the first decoding iteration 307 is un-windowed.

At reference number 409, the baseband processing circuitry 123 stores alpha state values 343, 349 (FIG. 3). Each alpha state value 343, 349 is associated with a respective position of the data block 209. The alpha state values 343, 349 are derived from performing a continuous alpha operation 214 on the data block 209. The position associated with each alpha state value 343, 349 corresponds to a start position of an alpha evaluation window 227 of the subsequent decoding iteration 307. To this end, alpha state values 343, 349 are determined based on the indexing of each alpha evaluation window range of the subsequent decoding iteration 307. The alpha state values 343, 349 may be stored in memory 146 that is accessible to a turbo decoder module 139 that executes the decoding iterations 307.

At reference number 412, the baseband processing circuitry 123 initializes each beta evaluation window 227. In various embodiments of the present disclosure, the initialization of each beta evaluation window 227 is based on a default state value. For example, the default state value may be a constant value used for each of the beta evaluation windows 227 for the even decoding iteration 307. To this end, the beta operation 217 of the even decoding iteration 307 excludes the use of training windows 233. At reference number 415, the baseband processing circuitry 123 performs a beta operation 217 (FIG. 2) for the current, even decoding iteration 307. The beta operation 217 of the even decoding iteration 307 uses beta evaluation windows 227. Put another way, the beta operation 217 of the even decoding iteration 307 is windowed or otherwise discontinuous.

At reference number 418, the baseband processing circuitry 123 stores the results generated from performing the alpha operation 214 and/or the beta operation 217. These results may be stored in memory 146. Furthermore, the results generated from performing the alpha operation 214 and performing the beta operation 217 may be combined or otherwise summed together to generate likelihood data such as, for example, log likelihood ratio data (LLR). The LLR may indicate a likelihood that a particular bit in the sequence of bits of the data block 209 expresses a binary one or a binary zero. Thus, the baseband processing circuitry 123 completes a full decoding iteration 307.

At reference number 421, the baseband processing circuitry 123 performs a beta operation 217 for the current, odd decoding iteration 307. The beta operation 217 is performed continuously or otherwise without the use of evaluation windows 227. Thus, the beta operation 217 is performed in a manner that is different than the beta operation 217 of the previous decoding iteration 307. Furthermore, the beta operation 217 of the odd decoding iteration 307 is performed in a manner that is different than the alpha operation 214 of the same odd decoding iteration 307. At reference number 424, the baseband processing circuitry 123 stores beta state values 346 (FIG. 3) derived from the continuous beta operation 217. These beta state values 346 are stored according to an indexing of the start positions of beta evaluation windows 227 of the subsequent decoding iteration 307. Thus, the beta state values 346 may be used to initialize corresponding beta evaluation windows 227 of the subsequent decoding iteration 307.

At reference number 427, the baseband processing circuitry 123 initializes each alpha evaluation window 227 using the alpha state values 343, 349 derived from the previous decoding iteration 307. Each alpha evaluation window 227 is initialized with a corresponding alpha state value 343, 349 that corresponds to the starting position of the alpha evaluation window 227. At reference number 430, the baseband processing circuitry 123 continues to the next decoding iteration 307. Specifically, an alpha operation 214 for the odd decoding iteration 307 is performed on the data block 209. Moreover, the alpha operation 214 for the odd decoding iteration 307 uses alpha evaluation windows 227 such that the alpha operation 214 is performed discontinuously. To this end, the alpha operation 214 is performed in a manner that is different than the alpha operation 214 of the previous decoding iteration 307.

In reference number 433, the baseband processing circuitry 123 stores the results generated from performing the alpha operation 214 and/or the beta operation 217 of the odd decoding iteration 307. These results may be stored in memory 146. Furthermore, the results generated from performing the alpha operation 214 and performing the beta operation 217 of the odd decoding iteration 307 may be combined or otherwise summed together to generate likelihood data. The odd decoding iteration 307 is then complete.

At reference number 436, the baseband processing circuitry 123 determines whether all decoding iterations 307 are complete. All decoding 307 iterations are complete when a predetermined number of decoding iterations are performed on the data block 209. If additional decoding iterations 307 are required, the baseband processing circuitry 123 continues to perform alpha operations 214 and beta operations 217 by initializing the alpha operation 214 or the beta operation 217 based on the state values 343, 346, 349 derived from the previous decoding iteration 307.

When all decoding iterations 307 are performed on the data block 209 then, at reference number 439, the baseband processing circuitry 123 performs an error detection operation on the decoding results of the turbo decoder module 139. For example, the baseband processing circuitry 123 may perform a CRC or any other error detection check on the decoder result. The decoder result expresses the turbo decoder module's 139 best guess of the information expressed in the data block 209.

The baseband processing circuitry 123 implemented in the receiver system 100 (FIG. 1), and other various systems described herein may be embodied in software or code executed by general purpose hardware. As an alternative, the same may also be embodied in dedicated hardware or a combination of software/general purpose hardware and dedicated hardware. If embodied in dedicated hardware, each can be implemented as a circuit or state machine that employs any one of or a combination of a number of technologies. These technologies may include, but are not limited to, discrete logic circuits having logic gates for implementing various logic functions upon an application of one or more data signals, application specific integrated circuits having appropriate logic gates, or other components, etc. Such technologies are generally well known by those skilled in the art and, consequently, are not described in detail herein.

The flowchart of FIG. 4 shows the functionality and operation of an implementation of portions of the baseband processing circuitry 123 implemented in the receiver system 100. If embodied in software, each block, indicated by a reference number, may represent a module, segment, or portion of code that comprises program instructions to implement the specified logical function(s). The program instructions may be embodied in the form of source code that comprises human-readable statements written in a programming language or machine code that comprises numerical instructions recognizable by a suitable execution system such as a processor in a computer system or other system. The machine code may be converted from the source code, etc. If embodied in hardware, each block, indicated by a reference number, may represent a circuit or a number of interconnected circuits to implement the specified logical function(s).

Although the flowchart of FIG. 4 shows a specific order of execution, it is understood that the order of execution may differ from that which is depicted. For example, the order of execution of two or more blocks may be scrambled relative to the order shown. Also, two or more blocks shown in succession in FIG. 4 may be executed concurrently or with partial concurrence. Further, in some embodiments, one or more of the blocks shown in FIG. 4 may be skipped or omitted. In addition, any number of counters, state variables, warning semaphores, or messages might be added to the logical flow described herein, for purposes of enhanced utility, accounting, performance measurement, or providing troubleshooting aids, etc. It is understood that all such variations are within the scope of the present disclosure.

Also, any logic or application described herein, including the baseband processing circuitry 123 that comprises software or code can be embodied in any non-transitory computer-readable medium for use by or in connection with an instruction execution system such as, for example, a processor in a computer system or other system. In this sense, the logic may comprise, for example, statements including instructions and declarations that can be fetched from the computer-readable medium and executed by the instruction execution system. In the context of the present disclosure, a “computer-readable medium” can be any medium that can contain, store, or maintain the logic or application described herein for use by or in connection with the instruction execution system.

The computer-readable medium can comprise any one of many physical media such as, for example, magnetic, optical, or semiconductor media. More specific examples of a suitable computer-readable medium would include, but are not limited to, magnetic tapes, magnetic floppy diskettes, magnetic hard drives, memory cards, solid-state drives, USB flash drives, or optical discs. Also, the computer-readable medium may be a random access memory (RAM) including, for example, static random access memory (SRAM) and dynamic random access memory (DRAM), or magnetic random access memory (MRAM). In addition, the computer-readable medium may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or other type of memory device.

It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

1. A method comprising:

obtaining a data block associated with a transmission time interval, the data block comprising a sequence of bits, the data block being encoded according to a coding rate;

performing on the data block an alpha operation for a first decoding iteration to generate first alpha decode data, the alpha operation for the first decoding iteration being performed continuously; and

performing on the data block an alpha operation for a second decoding iteration to generate second alpha decode data, the alpha operation for the second decoding iteration being performed according to a set of alpha evaluation windows.

2. The method of claim 1, wherein the alpha operation for the second decoding iteration comprises ordering the set of alpha evaluation windows according to a direction that is reversed with respect to the sequence of bits.

3. The method of claim 1, wherein each evaluation window in the set of alpha evaluation windows corresponds to a respective start position.

4. The method of claim 3, wherein performing the alpha operation for the first decoding iteration comprises storing an alpha state values for each respective start position, wherein each evaluation window corresponds to an alpha state value.

5. The method of claim 4, wherein performing the alpha operation for the second decoding iteration comprises initializing each evaluation window according to the corresponding alpha state value.

6. The method of claim 1, further comprising:

performing on the data block a beta operation for the first decoding iteration to generate first beta decode data, the beta operation for the first decoding iteration being performed according to a set of beta evaluation windows.

7. The method of claim 6, wherein the beta operation for the first decoding iteration comprises ordering the set of beta evaluation windows according to a direction correlating with the sequence of bits.

8. A system comprising:

a memory buffer configured to store a data block associated with a transmission time interval; and

a turbo decoder module in data communication with the memory buffer, the turbo decoder module being configured to: perform complete decode operations on the data block for a predetermined number of iterations, each complete decode operation comprising performing an alpha operation and a beta operation; continuously perform the beta operation for a first iteration; discontinuously perform the beta operation for a second iteration according to a set of beta evaluation windows; and generate likelihood data based at least upon performing a combination of the alpha operations and the beta operations.

9. The system of claim 8, wherein the turbo decoder module is further configured to store beta state values calculated from the first iteration.

10. The system of claim 9, wherein each beta state value corresponds to a start position associated with each beta evaluation window of the second iteration, wherein the turbo decoder module is further configured to initialize each beta evaluation window according to the corresponding beta state value.

11. The system of claim 9, wherein each beta evaluation window excludes a preceding training window configured to initializing the beta evaluation window.

12. The system of claim 8, wherein the turbo decoder module is further configured to discontinuously perform the alpha operation for the first iteration according to a set of alpha evaluation windows.

13. The system of claim 12, wherein the turbo decoder module is further configured to continuously perform the alpha operation for the second iteration.

14. The system of claim 12, wherein each alpha evaluation window of the first iteration is configured to be initialized according to a default state value.

15. A system comprising:

processing circuitry configured to: obtain a data block associated with a transmission time interval, the data block comprising a sequence of bits; perform on the data block an un-windowed alpha operation for a first decoding iteration; perform on the data block a beta operation for the first decoding iteration according to a set of beta evaluation windows of the first decoding iteration; perform on the data block an un-windowed beta operation for a second decoding iteration; and generate log likelihood data based at least upon the un-windowed alpha operation for the first decoding iteration and the beta operation for the first decoding iteration.

16. The system of claim 15, wherein the processing circuitry is further configured to perform on the data block an alpha operation for the second decoding iteration according to a set of alpha evaluation windows of the second decoding iteration.

17. The system of claim 16, wherein the processing circuitry is further configured to initialize each alpha evaluation window according to state value data generated from the un-windowed alpha operation for the first decoding iteration.

18. The system of claim 15, wherein the processing circuitry is further configured to:

perform on the data block a beta operation for a third decoding iteration according to a set of beta evaluation windows of the third decoding iteration; and

initialize each beta evaluation window for the third decoding iteration according to state value data generated from the un-windowed beta operation for the second decoding iteration.

19. The system of claim 18, wherein the processing circuitry is further configured to initialize each beta evaluation window for the first decoding iteration according to a default state value.

20. The system of claim 15, wherein each beta evaluation window excludes a preceding training window configured to initializing the beta evaluation window.