CIRCUIT AND METHOD FOR PROVIDING A REFERENCE SIGNAL
An integrated circuit for providing a reference signal to a regulator includes a comparison circuit and a first reference signal adjustor. The comparison circuit is configured to output a control signal based on a difference between levels of a constraint signal of the regulator, such as an input voltage signal or a supply voltage signal, and the reference signal. The regulator has a feedback control loop maintained by the reference signal. The first reference signal adjustor is operatively coupled to the comparison circuit and is configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
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The disclosure relates generally to a circuit and method for providing a reference signal to a regulator.
A regulator in electronic devices is designed to automatically maintain a constant level of an output signal, e.g., a voltage or current signal, by a feed-forward design or a negative feedback control loop.
In an ideal situation, with control of the slew-rate of the reference voltage signal Vref within the control loop bandwidth of the voltage regulator 100, the feedback voltage Vfb, and eventually the output voltage Vout, will follow the reference voltage Vref and rise toward the preset voltage level Vset with minimal or no overshoot. However, in the event that the slew-rate of either the input voltage signal Vin or supply voltage (bias) signal Vdda of the voltage regulator 100 is slower than the slew-rate required for proper regulation of the output voltage Vout to follow the reference voltage signal Vref, as shown in
Known solutions to solve the overshooting problem include (1) designing the slew-rate of the reference signal to be slower than that of the input signal and (2) applying an external capacitor based on the known slew-rate of the input signal. For the former solution, it typically requires more silicon area to achieve a slower slew-rate for the reference signal and may encounter a practical limitation on the lowest slew-rate that can be implemented. As to the latter solution, it is costly as it uses an extra external capacitor and I/O pin. Further, if the slew-rate of the input signal is slower than its recommended value based on a chosen capacitor, an overshoot may still occur for the latter solution. Moreover, neither solution can be applied if the input signal of the regulator has a wide varying rise-time.
Accordingly, there exists a need for an improved circuit and method for providing a reference signal to a regulator.
The embodiments will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein:
The present disclosure describes a circuit and method for providing a reference signal to a regulator. In one example, an integrated circuit for providing a reference signal to a regulator is provided. The integrated circuit includes a comparison circuit and a first reference signal adjustor. The comparison circuit is configured to output a control signal based on a difference between levels of a constraint signal of the regulator, such as an input voltage signal or a supply voltage signal, and the reference signal. The regulator has a feedback control loop maintained by the reference signal. The first reference signal adjustor is operatively coupled to the comparison circuit and is configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
In another example, an apparatus including an adaptive reference signal generator is provided. The apparatus further includes a regulator, a circuit, and a power source. The regulator is configured to provide an output signal and regulate the output signal at a certain level. The regulator has a feedback control loop maintained by a reference signal. The circuit is operatively coupled to the regulator and is configured to receive the output signal and perform one or more functions based on the output signal at the certain level. The power source is operatively coupled to the regulator and is configured to provide a constraint signal, such as an input voltage signal or a supply voltage signal, to the regulator. The adaptive reference signal generator is operatively coupled to the regulator and is configured to generate the reference signal based on the constraint signal.
In still another example, a method for providing a reference signal to a regulator is provided. A constraint signal of a regulator, such as an input voltage signal or a supply voltage signal, is first received. The regulator has a feedback control loop maintained by the reference signal. A control signal is then outputted based on a difference between levels of the constraint signal and the reference signal. Based on the control signal, the level of the reference signal is adjusted such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
In yet another example, a computer readable medium storing instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit is provide. The designed integrated circuit includes a comparison circuit and a first reference signal adjustor. The comparison circuit is configured to output a control signal based on a difference between levels of a constraint signal of a regulator, such as an input voltage signal or a supply voltage signal, and a reference signal. The regulator has a feedback control loop maintained by the reference signal. The first reference signal adjustor is operatively coupled to the comparison circuit and is configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
DETAILED DESCRIPTIONReference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with the embodiments, it will be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications, and equivalents, which may be included within the spirit and scope of the present disclosure as defined by the appended claims.
Furthermore, in the following detailed description of embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be recognized by one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments of the present disclosure.
Embodiments in accordance with the present disclosure provide a circuit and method for providing a reference signal to a regulator, such as a voltage regulator or a current regulator. Compared with the fixed or externally preset reference signal shown in
The adaptive reference signal generator 302 is operatively coupled to the regulator 304 and is configured to generate the reference signal Vref based on the constraint signal Vin/Vdda. For example, the adaptive reference signal generator 302 adjusts the rise-time (slew-rate) of the reference signal Vref to be adaptive to the rise-time (slew-rate) of the constraint signal Vin/Vdda. That is, the adaptive reference signal generator 302 may slow down the ramping-up of the reference signal Vref to follow the slew-rate of the constraint signal Vin/Vdda while maintaining a maximum slew-rate by a feedback control loop to avoid overshooting. The apparatus 300 may include any other suitable components, including, for example, a display, one or more storages, a communication platform, a sensing module, any other suitable I/O modules, etc.
In this example, the adaptive reference signal generator 302 may further include a second reference signal adjustor 404 operatively coupled to the first reference signal adjustor 402. The second reference signal adjustor 404 may be configured to maintain the reference signal Vref at the preset level Vset when the regulator 304 is in a steady-state phase. In other words, the maximum level of the reference signal Vref is limited at the preset level Vset and is reached when the regulator 304 turns into the steady-state phase. The transition from the start-up phase to the steady-state phase is smoother compared with known solutions, such as the one shown in
The adaptive reference signal generator 302 in this example includes a first reference signal adjustor 500, which adjusts the slew-rate of the reference signal Vref by adapting a charging current signal for a capacitor 506. The first reference signal adjustor 500 includes the capacitor 506 configured to provide the reference signal Vref at one end as the capacitor 506 is charged by the charging current signal Ic. In this example, the capacitance of the capacitor 506 may be from about 10 pF to about 100 pF. It is understood that different capacitance values may be applied and more than one capacitor or any other energy storage element may be applied in other examples. The first reference signal adjustor 500 also includes a charging controller 508 operatively coupled to the capacitor 506. The charging controller 508 is configured to control the slew-rate of the reference signal Vref by adjusting the charging of the capacitor 506 based on the control signal Vg1 from the comparison circuit 400. In this example, the charging controller 508 includes a current source 510 configured to generate a constant current signal I0 and a transistor 512, e.g., an n-channel MOSFET, operatively coupled to the comparison circuit 400, current source 510, and capacitor 506. In this example, for an input voltage signal Vin with a slew-rate from about 1 ms to about 10 ms and a capacitor 506 with a capacitance from about 10 pF to about 100 pF, the constant current signal I0 may be in the range of tens or hundreds of nA, depending on the preset voltage level Vset.
In this example, the transistor 512 acts as a switch between the current source 510 and the capacitor 506 to adjust the charging current signal lc based on the control signal Vg1. The gate of the transistor 512 is connected to the output node of the error amplifier 504 such that the control signal Vg1 controls the gate voltage of the transistor 512. If the level of the reference signal Nref does not exceed the level of the input voltage signal Vin at the non-inverting node of the error amplifier 504, the control signal Vg1 (gate voltage of the transistor 512) causes the transistor 512 to operate in the saturation mode such that the level of the charging current signal applied to the capacitor 506 is substantially equal to the level of the constant current signal I0. The reference signal Vref ramps-up at a slew-rate determined by
where C is the capacitance of the capacitor 506. If the level of the reference signal Vref exceeds the level of the input voltage signal Vin, the control signal Vg1 (gate voltage of the transistor 512) causes the transistor 512 to operate in the linear mode such that the level of the charging current signal Ic applied to the capacitor 506 is adjusted in accordance with the difference between the levels of the reference signal Vref and input voltage signal Vin. That is, in this case, the transistor 512 works as a voltage-controlled variable resistor whose resistance is adjusted by the control signal Vg1, i.e., by the difference between the levels of the reference signal Vref and input voltage signal Vin. As the resistance of the transistor 512 increases, the charging current signal Ic decreases accordingly and thus, causes the slew-rate of the reference signal Vref to reduce.
Referring now to the timing diagram on
In this example, the adaptive reference signal generator 302 may further include the second reference signal adjustor 502 operatively coupled to the first reference signal adjustor 500. The second reference signal adjustor 502 acts as a switching module configured to turn off the first reference signal adjustor 500 when the level of the reference signal Vref is within an offset range Voffset from the preset level Vset. As shown in
Compared with
In one example, the current controller 1004 includes a current source, which has an amplifier 1008, a transistor 1010, and a resistor 1012, configured to determine the initial level of the control current signal Ictrl based on a control voltage signal Vctrl. The initial level of the control current signal Ictrl may be determined by
where R is the resistance of the resistor 1012. The selection of Vctrl and R is arbitrary and may be programmed depending on the design requirement of the initial slew-rate of the reference signal Vref. The current controller 1004 also includes the transistor 512 configured to switch between the saturation mode and linear mode for adjusting the level of the control current signal Ictrl based on the difference between the levels of the reference signal Vref and the input voltage signal Vin, as noted above. The current mirror 1006 is then responsible for generating a charging current signal Ic at a level substantially equal to the level of the control current signal Ictrl. That is, the initial control current signal Ictrl flows through the transistor 512, which is adjusted accordingly by the feedback control loop, and is mirrored by the current mirror 1006 to charge the capacitor 506. The initial slew-rate of the reference signal Vref before it is adjusted by the transistor 512 is determined by
where C is the capacitance of the capacitor 506. It is understood that the first reference signal adjustor 1000 in this example may replace the first reference signal adjustors 500, 700 in
Also, integrated circuit design systems (e.g., work stations) are known that create wafers with integrated circuits based on executable instructions stored on a computer readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the circuits described herein may also be produced as integrated circuits by such systems using the computer readable medium with instructions stored therein. For example, an integrated circuit with the aforedescribed circuits may be created using such integrated circuit fabrication systems. The computer readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit. The designed integrated circuit includes a comparison circuit, a first reference signal adjustor, as well as other circuits as disclosed herein. The comparison circuit is configured to output a control signal based on a difference between levels of a constraint signal of a regulator and a reference signal. The regulator has a feedback control loop maintained by a reference signal. The first reference signal adjustor is operatively coupled to the comparison circuit and is configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
While the foregoing description and drawings represent embodiments of the present disclosure, it will be understood that various additions, modifications, and substitutions may be made therein without departing from the spirit and scope of the principles of the present disclosure as defined in the accompanying claims. One skilled in the art will appreciate that the present disclosure may be used with many modifications of form, structure, arrangement, proportions, materials, elements, and components and otherwise, used in the practice of the disclosure, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present disclosure. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the present disclosure being indicated by the appended claims and their legal equivalents, and not limited to the foregoing description.
Claims
1. An integrated circuit for providing a reference signal to a regulator, comprising:
- a comparison circuit configured to output a control signal based on a difference between levels of a constraint signal of the regulator and the reference signal, the regulator having a feedback control loop maintained by the reference signal; and
- a first reference signal adjustor operatively coupled to the comparison circuit, configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
2. The integrated circuit of claim 1, wherein the first reference signal adjustor comprises:
- a capacitor configured to provide the reference signal at one end thereof; and
- a charging controller operatively coupled to the capacitor, configured to control a slew-rate of the reference signal by adjusting charging of the capacitor based on the control signal from the comparison circuit.
3. The integrated circuit of claim 2, wherein the charging controller comprises:
- a current source configured to generate a constant current signal; and
- a transistor operatively coupled to the comparison circuit, the current source, and the capacitor, configured to: operate in a saturation mode such that a level of a charging current signal applied to the capacitor is substantially equal to a level of the constant current signal if the level of the reference signal does not exceed the level of the constraint signal, and operate in a linear mode such that the level of the charging current signal applied to the capacitor is adjusted based on the difference between the levels of the reference signal and the constraint signal if the level of the reference signal exceeds the level of the constraint signal.
4. The integrated circuit of claim 2, wherein the charging controller comprises:
- a current controller operatively coupled to the comparison circuit, configured to: provide a control current signal at an initial level if the level of the reference signal does not exceed the level of the constraint signal, and adjust a level of the control current signal based on the difference between the levels of the reference signal and the constraint signal if the level of the reference signal exceeds the level of the constraint signal; and
- a current mirror operatively coupled to the current controller and the capacitor, configured to generate a charging current signal at a level substantially equal to the level of the control current signal.
5. The integrated circuit of claim 4, wherein the current controller comprises:
- a current source comprising an amplifier, a first transistor, and a resistor, the current source configured to determine the initial level of the control current signal based on a control voltage signal; and
- a second transistor operatively coupled to the current source, configured to switch between a saturation mode and a linear mode for adjusting the level of the control current signal based on the difference between the levels of the reference signal and the constraint signal.
6. The integrated circuit of claim 1, wherein
- the constraint signal includes an input voltage signal of the regulator; and
- the level of the reference signal is adjusted based on the control signal such that the level of the reference signal does not exceed the level of the input voltage signal.
7. The integrated circuit of claim 1, wherein
- the constraint signal includes a supply voltage signal of the regulator whose level is adjusted based on a headroom requirement of the feedback control loop of the regulator; and
- the level of the reference signal is adjusted based on the control signal such that the level of the reference signal does not exceed the adjusted level of the supply voltage signal.
8. The integrated circuit of claim 2, further comprising a second reference signal adjustor operatively coupled to first reference signal adjustor, configured to maintain the reference signal at the preset level when the regulator is in a steady-state phase.
9. The integrated circuit of claim 8, wherein the second reference signal adjustor comprises a switching module configured to turn off the first reference signal adjustor when the level of the reference signal is within an offset range from the preset level.
10. The integrated circuit of claim 8, wherein the second reference signal adjustor comprises a voltage source at the preset level operatively coupled to the charging controller such that a maximum voltage level at the capacitor is the preset level when the capacitor is fully charged.
11. An apparatus comprising:
- a regulator configured to provide an output signal and regulate the output signal at a certain level, the regulator having a feedback control loop maintained by a reference signal;
- a circuit operatively coupled to the regulator, configured to receive the output signal and perform one or more functions based on the output signal at the certain level;
- a power source operatively coupled to the regulator, configured to provide a constraint signal to the regulator; and
- an adaptive reference signal generator operatively coupled to the regulator, configured to generate the reference signal based on the constraint signal.
12. The apparatus of claim 11, wherein the adaptive reference signal generator comprises:
- a comparison circuit configured to output a control signal based on a difference between levels of the constraint signal and the reference signal; and
- a first reference signal adjustor operatively coupled to the comparison circuit, configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
13. The apparatus of claim 12, wherein the first reference signal adjustor comprises:
- a capacitor configured to provide the reference signal at one end thereof; and
- a charging controller operatively coupled to the capacitor, configured to control a slew-rate of the reference signal by adjusting charging of the capacitor based on the control signal from the comparison circuit.
14. The apparatus of claim 12, wherein
- the constraint signal includes an input voltage signal of the regulator; and
- the level of the reference signal is adjusted based on the control signal such that the level of the reference signal does not exceed the level of the input voltage signal.
15. The apparatus of claim 12, wherein
- the constraint signal includes a supply voltage signal of the regulator whose level is adjusted based on a headroom requirement of the feedback control loop of the regulator; and
- the level of the reference signal is adjusted based on the control signal such that the level of the reference signal does not exceed the adjusted level of the supply voltage signal.
16. The apparatus of claim 12, wherein the adaptive reference signal generator further comprises a second reference signal adjustor operatively coupled to first reference signal adjustor, configured to maintain the reference signal at the preset level when the regulator is in a steady-state phase.
17. The apparatus of claim 11, wherein
- the regulator is one of a voltage regulator and a current regulator;
- the circuit is a processor; and
- the power source is a battery.
18. A method for providing a reference signal to a regulator comprising:
- receiving a constraint signal of the regulator, the regulator having a feedback control loop maintained by the reference signal;
- outputting a control signal based on a difference between levels of the reference signal and the constraint signal; and
- adjusting the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
19. The method of claim 18, further comprising maintaining the reference signal at the preset level when the regulator is in a steady-state phase.
20. The method of claim 18, wherein
- the constraint signal includes an input voltage signal of the regulator; and
- the level of the reference signal is adjusted based on the control signal such that the level of the reference signal does not exceed the level of the input voltage signal.
21. The method of claim 18, wherein
- the constraint signal includes a supply voltage signal of the regulator whose level is adjusted based on a headroom requirement of the feedback control loop of the regulator; and
- the level of the reference signal is adjusted based on the control signal such that the level of the reference signal does not exceed the adjusted level of the supply voltage signal.
22. A computer readable medium storing instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit comprising:
- a comparison circuit configured to output a control signal based on a difference between levels of a constraint signal and a reference signal of a regulator, the regulator having a feedback control loop maintained by the reference signal; and
- a first reference signal adjustor operatively coupled to the comparison circuit, configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase.
Type: Application
Filed: Dec 19, 2011
Publication Date: Jun 20, 2013
Patent Grant number: 8598861
Applicant: O2MICRO INC. (Santa Clara, CA)
Inventor: Cheng Hwa Teh (The Riverdale)
Application Number: 13/329,520