DRIVING CIRCUIT OF DISPLAY PANEL CAPABLE OF ELIMINATING FLASH

Abstract

The present invention relates to a driving circuit of display panel capable of eliminating flash, which comprises a scan driving circuit and a data driving circuit. The scan driving circuit produces a plurality of scan signals for scanning a plurality of pixel structures of the display panel. The data driving circuit produces a plurality of data signals for transmitting the plurality of data signals to the plurality of pixel structures when the plurality of pixel structures are scanned. When the data driving circuit transmits the plurality of data signals to the plurality of pixel structures, the data driving circuit adjusts the voltage levels of the data signals of the plurality of pixel structures to be symmetrical to a common voltage of the plurality of pixel structures.

Description

REFERENCE TO RELATED APPLICATION

This Application is based on Provisional Patent Application Ser. No. 61/636,833, filed 23 Apr. 2012, currently pending.

FIELD OF THE INVENTION

The present invention relates generally to a driving circuit of display panel, and particularly to a driving circuit of display panel capable of eliminating screen flash (flicker) phenomenon and thus enhancing the displaying quality.

BACKGROUND OF THE INVENTION

Modern technologies are developing prosperously. Novel information products are introduced daily for satisfying people's various needs. Early displays are mainly cathode ray tubes (CRTs). Owing to their huge size, heavy power consumption, and radiation hazardous to the heath of long-term users, traditional CRTs are gradually replaced by liquid crystal displays (LCDs). LCDs have the advantages of small size, low radiation, and low power consumption, and thus becoming the mainstream in the market.

LCDs control the transmittance of liquid crystal cells according to data signals for displaying images. FIG. 1 shows a schematic diagram of the display panel and its plurality of pixel structures according to the prior art. As shown in FIG. 1, the display panel comprises a plurality of pixel structures 10′ and a driving chip 20′. The driving chip 20′ produces a driving signal for driving the plurality of pixel structures 10′. Where each of the pixel structures 10′ includes a thin film transistor (TFT) 12′ and a storage capacitor 14′. The gate of the TFT 12′ is coupled to a scan line; the source of the TFT 12′ is coupled to the driving chip 20′; and the drain of the TFT 12′ is coupled to the storage capacitor 14′. Because an active-matrix LCD adopts active switching devices, it is advantageous in displaying moving pictures. TFTs 12′ are mainly used as the switching devices in active-matrix LCDs.

In addition, the applications of TFT LCDs are extensive. Their driving method is to turn on the internal cell using the gate. Then the source is used for supplying the accurate voltage for controlling the orientation of the liquid crystal in the display panel for displaying images. FIG. 2 shows a schematic diagram of the plurality of pixel structures of the display panel and FIG. 3 shows waveform of the driving signal for the plurality of pixel structures according to the prior art. As shown in the figures, the driving chip 20′ will produce a plurality of scan signals G0, G1, . . . , Gn and transmit the plurality of scan signals G0, G1, . . . , Gn sequentially to a plurality of scan lines Ga1, Ga2, . . . , Gan of the plurality of pixel structures. As any of the scan lines is activated, namely, the scan signal reaching VGH, a plurality of data lines S0, S1, . . . , Sn supply the corresponding voltages of image data to the pixel structures 10′ of the display panel and thus displaying the image.

There exists a parasitic capacitor 16′ between the TFT 14′ of the plurality of pixel structures 10′ and the storage capacitor 14′ such as Cs1, Cs2, Cs3, and Cs4 in FIG. 2. Thereby, when the scan signal G0 is cut off, the storage voltages across the storage capacitors Cs1, Cs2 will be shifted downwards by a shift voltage Vsft owing to the parasitic capacitors 16′, which is approximately 1 volt. The driving chip 20′ will provide a reference voltage DC to a common electrode 18′ of the plurality of pixel structures according to the shift voltage Vsft, which is used as a common voltage. Hence, when the scan signal G0 is cut off and the storage voltages across the storage capacitors Cs1, Cs2 are shifted by a shift voltage Vsft owing to the parasitic capacitors 16′, the storage voltages across the storage capacitors Cs1, Cs2 are still symmetrical to the common voltage of the common electrode 18′ while displaying identical grayscale voltages.

Nonetheless, the parasitic capacitors 16′ vary over the display panel. As the storage voltages across the storage capacitors Cs1, Cs2 are shifted by a shift voltage Vsft, the shift voltage Vsft will be slightly different. Thereby, while displaying identical grayscale voltages, the storage voltages across the storage capacitors Cs1, Cs2 tend to be not symmetrical to the common voltage of the common electrode 18′ and thus producing the flash phenomenon. Moreover, as the scan signal G0 switches TFTs, as shown in FIG. 3, the voltage level of the common voltage on the common electrode of the pixel structures are influenced, which further influences the displaying quality.

Accordingly, the present invention provides a novel driving circuit of display panel capable of eliminating flash. When the adjacent pixel structures are displaying identical grayscale voltages, the storage voltages across the storage capacitors tend to be asymmetrical to the common voltage of the common electrode and resulting in the flash phenomenon. The present invention provides a driving circuit of display panel to solve the problem.

SUMMARY

An objective of the present invention is to provide a driving circuit of display panel capable of eliminating flash, which uses a data driving circuit to adjust the voltage levels of the data signals of a plurality of adjacent pixel structures to be symmetrical to a common voltage of the plurality of pixel structures for eliminating the screen flash phenomenon.

The driving circuit of display panel according to the present invention comprises a scan driving circuit and a data driving circuit. The scan driving circuit produces a plurality of scan signals for scanning a plurality of pixel structures of the display panel. The data driving circuit produces a plurality of data signals for transmitting the plurality of data signals to the plurality of pixel structures when the plurality of pixel structures are scanned. When the data driving circuit transmits the plurality of data signals to the plurality of pixel structures, the data driving circuit adjusts the voltage levels of the data signals of the plurality of pixel structures to be symmetrical to a common voltage of the plurality of pixel structures. Accordingly, by using the data driving circuit to adjust the voltage levels of the data signals of a plurality of adjacent pixel structures to be symmetrical to the common voltage of the plurality of pixel structures, the screen flash phenomenon can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of the display panel and its plurality of pixel structures according to the prior art;

FIG. 2 shows a schematic diagram of the plurality of pixel structures of the display panel according to the prior art;

FIG. 3 shows waveforms of the driving signal for the plurality of pixel structures according the prior art;

FIG. 4 shows a schematic diagram of the display device according to an embodiment of the present invention;

FIG. 5 shows a schematic diagram of the pixel structures of the display panel of the display device in FIG. 4 according to an embodiment of the present invention;

FIG. 6A shows schematic diagrams of the display panel of the display device and the pixel structures thereof in FIG. 4 according to an embodiment of the present invention;

FIG. 6B shows schematic diagrams of the display panel of the display device and the pixel structures thereof in FIG. 4 according to another embodiment of the present invention;

FIG. 6C shows schematic diagrams of the display panel of the display device and the pixel structures thereof in FIG. 4 according to another embodiment of the present invention;

FIG. 7A shows waveforms of the driving circuit in FIG. 6A driving the display panel according to the present invention;

FIG. 7B shows waveforms of the driving circuit in FIGS. 6A and 6B driving the display panel according to the present invention;

FIG. 8 shows a circuit diagram of the data driving circuit according to an embodiment of the present invention;

FIG. 9 shows a circuit diagram of the data driving circuit according to another embodiment of the present invention; and

FIG. 10 shows a circuit diagram of the data driving circuit according to still another embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the structure and characteristics as well as the effectiveness of the present invention to be further understood and recognized, the detailed description of the present invention is provided as follows along with embodiments and accompanying figures.

FIGS. 4, 5, and 6A show schematic diagrams of the display panel, the display device, and a plurality of pixel structures thereof according to an embodiment of the present invention. As shown in the figures, the display device according to the present invention comprises a display panel I and a driving circuit 2. The display panel includes a plurality of pixel structures 10, which are located at the intersections of the scan lines and the data lines of the display panel 1, as shown in FIG. 5. The plurality of pixel structures 10 include a first pixel structure P1, a second pixel structure P2, a third pixel structure P3, and a fourth pixel structure P4. The first pixel structure P, the second pixel structure P2, the third pixel structure, and the fourth pixel structure P4 are arranged in a matrix. In other words, the first and second pixel structures P1, P2 are arranged horizontally; the first and third pixel structures P1, P3 are arranged vertically; the second and fourth pixel structures P2, P4 are arranged vertically; and the third and fourth pixel structures are arranged horizontally. The first and second pixel structures P1, P2 are controlled by a first scan line G0; the third and fourth pixel structures P3, P4 are controlled by a second scan line G1; the first and third pixel structures P1, P3 are coupled to a data line S0; and the second and fourth pixel structures P2, P4 are coupled to a second data line S1. Each pixel structure 10 includes a transistor 12 and a storage capacitor 14.

The transistor 12 has a gate, a source, and a drain. The transistor 12 is a switch. The gate of the transistor 12 is coupled to the scan line of the display panel 1 for controlling the turning on and cutoff of the transistor 12. The source of the transistor 12 is coupled to the data line of the display panel 1 for receiving the data signal according to the turning on of the transistor 12. The drain of the transistor 12 is coupled to a terminal of the storage capacitor 14. The other terminal of the storage capacitor 14, namely, the common electrode COM, is coupled to a ground. Here the storage capacitor 14 is a liquid crystal capacitor.

In addition, the driving circuit 2 of the display device according to the present invention includes a scan driving circuit 20 and a data driving circuit 30. The scan driving circuit 20 produces a plurality of scan signals for scanning the plurality of pixel structures 10 of the display panel 1. The data driving circuit 30 produces a plurality of data signals and transmits the plurality of data signals to the plurality of pixel structures 10 corresponding to the plurality of scan signals. That is to say, when the plurality of pixel structures 10 are scanned, the data driving circuit 30 transmits the plurality of data signals to the plurality of pixel structures 10. When the data driving circuit 30 transmits the plurality of data signals to the plurality of adjacent pixel structures 10, the data driving circuit 30 adjusts the voltage levels of the data signals of the plurality of adjacent pixel structures 10 to be symmetrical to the common voltage VCOM of the plurality of pixel structures 10. Taking FIGS. 5 and 7A for example, the scan driving circuit 20 produces and transmits the scan signal to the first scan line G0, the first pixel structure CS1 and the adjacent second pixel CS2, the data driving circuit 20 produces and transmits the plurality of data signals to the first pixel structure CS1 and the adjacent second pixel CS2, respectively. The polarities of the plurality of data signals transmitted by the data driving circuit 20 to the first pixel structure CS1 and the adjacent second pixel CS2, respectively, are opposite. Thereby, when the first pixel structure CS1 and the adjacent second pixel CS2 are displaying identical grayscale voltages, the voltage levels of the plurality of data signals transmitted by the data driving circuit 30 to the first pixel structure CS1 and the adjacent second pixel CS2 are symmetrical to the common voltage VCOM of the plurality of pixel structures 10. Namely, the storage voltage across the storage capacitor 14 of the first pixel structure CS1 and the storage voltage across the storage capacitor 14 of the second pixel structure CS2 are still symmetrical to the common voltage VCOM of the common electrode COM of the plurality of pixel structures 10. Accordingly, the present invention can eliminate the screen flash phenomenon.

Besides, the driving circuit 2 according to the present invention further includes a common-electrode power supply circuit 60, which is coupled to the common electrode COM of the plurality of pixel structures 10 for supplying the common voltage VCOM.

FIGS. 6B and 7B show schematic diagrams of the display panel of the display device and the pixel structures thereof in FIG. 4 and waveforms of the driving circuit driving the display panel according to another embodiment of the present invention. As shown in the figures, the difference between the present embodiment and the one according to the previous one is that the common electrode COM of the plurality of pixel structures 10 according to the present embodiment is coupled to a ground. When the data driving circuit 30 transmits the plurality of data signals to the plurality of adjacent pixel structures 10, the data driving circuit 30 adjusts the voltage levels of the data signals of the plurality of adjacent pixel structures 10 to be symmetrical to the common voltage VCOM of the plurality of pixel structures 10, as shown in FIGS. 5 and 7B. When the scan driving circuit 20 transmits the scan signal to the first scan line G0, the data driving circuit 30 transmits the plurality of data signals, respectively, to the first pixel structure CS1 and the second pixel structure CS2. When the level of the scan signal of the first scan line G0 is high and the first and second pixel structures CS1, CS2 are displaying identical grayscale voltages, the voltage levels of the plurality of data signals of transmitted to the first and second pixel structures CS1, CS2 by the data driving circuit 30 are symmetrical to the common voltage VCOM of the plurality of pixel structures 10. In other words, the data signal of the first pixel structure CS1 and the data signal of the second pixel structure CS2 are symmetrical to the ground voltage. As the voltage level of the scan signal of the first scan line G0 is low, after the parasitic-capacitor effect of the first and second pixel structures CS1, CS2, the plurality of data signals are still symmetrical to the common voltage VCOM, which is the ground voltage in the present embodiment.

FIG. 6C shows schematic diagrams of the display panel of the display device and the pixel structures thereof in FIG. 4 according to another embodiment of the present invention. As shown in the figure, the difference between the present embodiment and the one in FIG. 6B is that the common electrode COM of the plurality of pixel structures 10 according to the present embodiment is not coupled to the ground directly. Instead, it is coupled to the ground via the driving circuit 20. In other words, the common electrode COM of the plurality of pixel structures 10 of the display panel 1 is coupled to any ground of the driving circuit 20 for making the common voltage VCOM of the common electrode COM zero.

FIG. 8 shows a circuit diagram of the data driving circuit of the display panel according to an embodiment of the present invention. As shown in the figure, the data driving circuit 30 of the display device according to the present invention comprises a compensation circuit 32, a gamma voltage generating circuit 34, a plurality of digital-to-analog converters (DACs) 36, and a plurality of buffer units 38. The compensation circuit 32 produces a compensation signal. The gamma voltage generating circuit 34 generates a plurality of gamma voltages according the compensation signal and gamma curve data. The compensation signal produced by the compensation circuit 32 is used for adjusting the signal levels of the plurality of gamma voltages output by the gamma voltage generating circuit 34.

The plurality of DACs 36 select a portion of the plurality of gamma voltages according to a plurality of display signals. In other words, after the plurality of DACs 36 receive the display signals, respectively, they will determine to select one of the plurality of gamma voltages, respectively, according to the display signals and output the determined gamma voltage. For example, the gamma voltage generating circuit 34 generates 64 gamma voltages to the plurality of DACs 36. When the display signal received by the first DAC 36 is 15, the first DAC 36 will select the 15th gamma voltage for outputting. When the display signal received by the fifth DAC 36 is 55, the fifth DAC 36 will select the 55th gamma voltage for outputting.

The plurality of buffer units 38 correspond to the plurality of DACs 36 and produce a plurality of data signals according to the plurality of gamma voltages output by the plurality of DACs 36 for driving the display panel 1. Namely, the plurality of buffer units 38 are coupled to the plurality of DACs 36, respectively, for buffering the plurality of gamma voltages output by the plurality of DACs 36, and hence producing and outputting the plurality of data signals for driving the display panel 1. Accordingly, by using the compensation signal produced by the compensation circuit 32, the signal levels of the plurality of gamma voltages output by the gamma voltage generating circuit 34 can be adjusted. Thereby, as the scan signal is cut off and the storage voltage across the storage capacitor 14 is shifted downwards by a shift voltage Vsft owing to the parasitic capacitor, as shown in FIGS. 7A and 7B, the storage voltage across the storage capacitor 14 is still symmetrical to the common voltage VCOM of the common electrode COM while displaying identical grayscale voltages. Thus, the flash phenomenon can be eliminated. For example, the magnitude of compensation signal is the shift voltage Vsft. Then the signal levels of the plurality of gamma voltage are adjusted upwards or downwards by a shift voltage Vsft. When the scan signal is cut off and the storage voltage across the storage capacitor 14 is shifted downwards by a shift voltage Vsft owing to the parasitic capacitor, the storage voltage across the storage capacitor 14 is still symmetrical to the common voltage VCOM of the common electrode COM while displaying identical grayscale voltages. Thereby, by using the data driving circuit 30 to adjust the voltage levels of the data signals of a plurality of adjacent pixel structures to be symmetrical to the common voltage of the plurality of pixel structures, the screen flash phenomenon can be eliminated.

Refer again to FIG. 8. The gamma voltage generating circuit 34 according to the present invention comprises a voltage dividing circuit 340 and a gamma-voltage selection unit 342. The voltage dividing circuit 340 receives a power supply voltage GV_DD and produces a plurality of voltage dividing signals according to the compensation signal. The gamma-voltage selection unit 342 is coupled to the voltage dividing circuit 340 and generating the plurality of gamma voltages by selecting a portion of the voltage dividing signal of the plurality of voltage dividing signals according to the gamma curve data.

Moreover, the data driving circuit 30 of the display panel 1 according to the present invention further includes an input/output interface 40, a gamma curve data register 42, a display memory 44, a shift register 46, and a buffer circuit 48. The input/output interface 40 receives the gamma curve data and the display signal. The gamma curve data register 42 is coupled to the input/output interface 40, registers the gamma curve data, and transmitting the gamma curve data to the gamma voltage generating circuit 34. The display memory 44 is coupled to the input/output interface 40 and stores the display signal. The shift register 46 is coupled to the display memory 44, and receives and shifts the display signal. The buffer circuit 48 is coupled to the shift register 46. buffers the display signal, and transmits the display signal to the plurality of DACs 36.

FIG. 9 shows a circuit diagram of the driving circuit of the display panel according to another embodiment of the present invention. As shown in the figure, the difference between the present embodiment and the one in FIG. 8 is that the compensation circuit 32 according the present embodiment comprises a compensation unit 320, an adjusting circuit 322, and a switching circuit 324. The compensation unit 320 is used for producing a compensation signal. The adjusting circuit 322 receives a power supply voltage GVdd and dividing the voltage of the power supply voltage GVdd for producing a plurality of adjusting signal. The switching circuit 324 is coupled to the adjusting circuit 322. The switching circuit 324 selects the plurality of adjusting signals according to the compensation signal for producing a first reference voltage and a second reference voltage and transmits the first and second reference voltages to the gamma voltage generating circuit 34. Thereby, according to the present embodiment, by using the compensation signal produced by the compensation unit 32, the switching circuit 324 can select the plurality of adjusting signals produced by the adjusting circuit 322 for producing the first and second reference signals and thus adjusting the signal levels of the plurality of gamma voltages. Hence, the signal levels of the driving signals output by the data driving circuit 30 can be adjusted as well. Thereby, by using the data driving circuit 30 to adjust the voltage levels of the data signals of the plurality of adjacent pixel structures 10 to be symmetrical to the common voltage of the plurality of pixel structures 10, the screen flash phenomenon can be eliminated.

In addition, the compensation circuit 32 according to the present embodiment further comprises a first amplifying unit 326 and a second amplifying unit 328. The first amplifying unit 326 is coupled to the switching circuit 324, and buffers the first reference voltage and transmits it to the voltage dividing circuit 340. The second amplifying unit 328 is coupled to the switching circuit 324, and buffers the second reference voltage and transmits it to the voltage dividing circuit 340. Then the voltage dividing circuit 340 divides the voltage difference between the first and second reference voltage and gives the plurality of voltage dividing signals.

FIG. 10 shows a circuit diagram of the driving circuit of the display panel according to still another embodiment of the present invention. As shown in the figure, the difference between the present embodiment and the embodiments of FIGS. 8 and 9 is that the data driving circuit 30 according to the present embodiment 30 further includes an operational circuit 50, which is coupled to the gamma curve data register 42. The operational circuit 50 calculates the gamma curve data and the compensation signal, and produces an operational signal and transmits the operational signal to the gamma voltage generating circuit 34 for generating the plurality of gamma voltages. Namely, The compensation circuit 32 produces the compensation signal according to the magnitude of the downward shift voltage Vsft, which is coupled to the storage voltage across the storage capacitors 14 of the plurality of pixel structures 10 and caused by the parasitic capacitor of the transistors 12. Thereby, the operational circuit 50 first add the compensation signal to the gamma curve data. Then, as the scan signal is cut off and the storage voltage across the storage capacitor 14 is shifted downwards by a shift voltage Vsft owing to the parasitic capacitor, the storage voltage across the storage capacitor 14 is still symmetrical to the common voltage VCOM of the common electrode COM while displaying identical grayscale voltages. Thus, the flash phenomenon can be eliminated.

To sum up, the driving circuit of display panel according to the present invention comprises a scan driving circuit and a data driving circuit. The scan driving circuit produces a plurality of scan signals for scanning a plurality of pixel structures of the display panel. The data driving circuit produces a plurality of data signals for transmitting the plurality of data signals to the plurality of pixel structures when the plurality of pixel structures are scanned. When the data driving circuit transmits the plurality of data signals to the plurality of pixel structures, the data driving circuit adjusts the voltage levels of the data signals of the plurality of pixel structures to be symmetrical to a common voltage of the plurality of pixel structures. Accordingly, by using the data driving circuit to adjust the voltage levels of the data signals of a plurality of adjacent pixel structures to be symmetrical to the common voltage of the plurality of pixel structures, the screen flash phenomenon can be eliminated.

Claims

1. A driving circuit of display panel capable eliminating flash, comprising:

a scan driving circuit, producing a plurality of scan signals, and scanning a plurality of pixel structures of said display panel; and

a data driving circuit, producing a plurality of data signals, and transmitting said plurality of data signals to said plurality of pixel structures when said plurality of pixels structures are scanned; where when said data driving circuit transmits said plurality of data signals to said plurality of adjacent pixel structures, said data driving circuit adjusts the voltage levels of said data signals of said plurality of adjacent pixel structures to be symmetrical to a common voltage of said plurality of pixel structures.

2. The driving circuit of claim 1, wherein said data driving circuit comprises:

a compensation circuit, producing a compensation signal;

a gamma voltage generating circuit, generating a plurality of gamma voltages according to said compensation signal and gamma curve data; and

a plurality of digital-to-analog converters, selecting a portion of said plurality of gamma voltages according to a plurality of display signals for outputting and driving said display panel;

where said compensation signal of said compensation circuit adjusts the signal levels of said plurality of gamma voltages for adjusting the voltage levels of said data signals of said plurality of adjacent pixel structures to be symmetrical to said common voltage of said plurality of pixel structures.

3. The driving circuit of claim 2, wherein said data driving circuit further comprises a plurality of buffer units, corresponding to said plurality of digital-to-analog converters, producing a plurality of data signals according to said plurality of gamma voltages output by said plurality of digital-to-analog converters for driving said display panel.

4. The driving circuit of claim 2, wherein said gamma voltage generating circuit comprises:

a voltage dividing circuit, producing a plurality of voltage dividing signals; and

a gamma voltage selecting unit, coupled to said voltage dividing unit, and selecting a portion of said plurality of voltage dividing signals according to said gamma curve data for producing said plurality of gamma voltages.

5. The driving circuit of claim 2, and further comprising:

an input/output interface, receiving said gamma curve data and said display signal; and

a gamma curve data register, coupled to said input/output interface, registering said gamma curve data, and transmitting said gamma curve data to said gamma voltage generating circuit.

6. The driving circuit of claim 5, and further comprising:

a display memory, coupled to said input/output interface, and storing said display signal;

a shift register, coupled to said display memory, and receiving and shifting said display signal; and

a buffer circuit, coupled to said shift register, buffering and transmitting said display signal to said plurality of digital-to-analog converters.

7. The driving circuit of claim 4, wherein said compensation circuit comprises:

a compensation unit, producing a compensation signal;

an adjusting circuit, receiving a power supply voltage, and dividing said power supply voltage for producing a plurality of adjusting signals; and

a switching circuit, coupled to said adjusting circuit, selecting said plurality of adjusting signals for producing a first reference voltage and a second reference voltage, and transmitting said first reference voltage and said second reference voltage to said voltage dividing circuit so that said voltage dividing circuit producing said plurality of voltage dividing signals according to said first reference voltage and said second reference voltage.

8. The driving circuit of claim 7, wherein said gamma voltage generating circuit further comprises:

a first amplifying unit, coupled to said switching circuit, and buffering and transmitting said first reference voltage to said voltage dividing circuit; and

a second amplifying unit, coupled to said switching circuit, and buffering and transmitting said second reference voltage to said voltage dividing circuit.

9. The driving circuit of claim 2, and further comprising an operational circuit, calculating said gamma curve data and said compensation signal for producing an operational signal, and transmitting said operational signal to said gamma voltage generating circuit for generating said plurality of gamma voltages.