Abstract: A display device includes a plurality of pixels arranged in m rows and n columns, where the pixels receive write scan signals, data voltages and compensation scan signals, a plurality of write scan lines which provides the write scan signals to the pixels, a plurality of data lines which provides the data voltages to the pixels, and a plurality of compensation scan lines which provides the compensation scan signals to the pixels, wherein in h-th to p-th frames, the data voltages are applied to pixels arranged in first to i-th rows, and in h-th to (h+k)-th frames, the data voltages are applied to pixels of a row unit by increasing sequentially the number of the row unit to which the data voltages are applied in at least one row unit from an i-th row to an (i+1)-th row.

Abstract: Disclosed are an auxiliary display device of a light emitting diode (LED) module and an LED display. The auxiliary display device includes a shared hub provided with a dual input port and an independent output port. The dual input port is configured to receive a dual supply voltage, and the dual supply voltage includes a first voltage and a second voltage. The independent output port is connected to a common anode LED module and/or a common cathode LED module. A first LED of the common anode LED module and a second LED of the common anode LED module are configured to receive the first voltage; and a first LED of the common cathode LED module is configured to receive the first voltage, and a second LED of the common cathode LED module is configured to receive the second voltage.

Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1?k?K?N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n?i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2. K=12, the input signal terminal of the n-th stage is connected to an output signal terminal of a (n?6)-th stage, and the reset signal terminals of the n-th stage and the (n+1)-th stage are connected to an output signal terminal of a (n+8)-th stage or a (n+10) stage.

Abstract: A driving method of a display panel and a display panel are provided. Time for displaying one frame includes N times of first node potential adjustment stages, a data writing stage, and at least one first bias stress stage; the data writing stage is after the first node potential adjustment stage and before the first bias stress stage; the N times first node potential adjustment stage include N reset stages and N first adjustment voltage writing stages; and an i-th first voltage writing stage is after an i-th reset stage. In the reset stage, the first reset module is turned on to write a reset signal to the first node; in the first adjustment voltage writing phase, the first reset module is turned off, and the compensation module is turned on to write a first adjustment voltage into the first node to adjust the bias state of the driving transistor.

Abstract: A display device includes a substrate, a first insulating layer disposed on the substrate, a through portion passing through the substrate and the first insulating layer, a display unit disposed on the first insulating layer and including a plurality of pixels surrounding at least a portion of the through portion, and a dummy pixel unit. Each pixel includes a light-emitting element including a pixel electrode and an opposite electrode facing each other, and an emission layer disposed between the pixel electrode and the opposite electrode. The dummy pixel unit includes a plurality of dummy pixels disposed between the through portion and the display unit, and including a metal pattern including a same material as the pixel electrode. The dummy pixels are disposed adjacent to the display unit.

Abstract: Various examples are provided related to driving a light emitting display in which variations in image quality and brightness can be suppressed despite long-term use, without adding a complicated circuit configuration. In one example, a method includes applying a voltage based on image data to be displayed to a gate electrode of a vertical organic light emitting transistor and applying a voltage, having a polarity opposite to that of the voltage applied to the gate electrode of the vertical organic light emitting transistor, to the gate electrode of the vertical organic light emitting transistor based on a value of a voltage being applied to a source electrode of the vertical organic light emitting transistor.

Abstract: Provided are a drive method of a display panel, a storage medium, a drive device and a display device. The drive method includes: in an Nth frame, applying a first voltage to the second electrode and a first data signal matched with a first voltage to the first electrode through the pixel drive circuit based on grayscale data of the Nth frame; wherein N is a positive integer; in an (N+1)th frame applying a second voltage to the second electrode and a second data signal matched with the second voltage to the first electrode through the pixel drive circuit based on grayscale data of the (N+1)th frame, wherein the first voltage is different from the second voltage.

Abstract: A pixel for an organic light emitting display device includes an organic light emitting diode that emits light by a driving current, a driving transistor configured to control the driving current, a first transistor to connect the second node and the third node, a second transistor to apply a data voltage to the first node, a third transistor to apply a high-potential driving voltage to the second node, a fourth transistor that forms a current path between the driving transistor and the organic light emitting diode, a fifth transistor to apply an initial voltage to the driving transistor, a sixth transistor configured to apply a reset voltage to a fourth node which is an anode electrode of the organic light emitting diode, a seventh transistor configured to apply the high-potential driving voltage to the fifth node, and an eighth transistor configured to apply a reference voltage to the fifth node.

Abstract: A display device includes a display panel including a plurality of pixels, a power supply which provides a driving voltage to the pixels, and a controller which outputs a first signal by comparing a sensing driving current generated by sensing driving currents flowing through the pixels with a limit current, outputs a second signal by comparing a load of previous frame data with a limit load, and outputs a driving voltage control signal for controlling the driving voltage to the power supply based on the first signal and the second signal.

Abstract: A display device includes: a pixel connected to a first scan line, a second scan line, and a data line, and including a light emitting element and a storage capacitor; and a timing controller configured to drive the pixel in a normal mode in which a driving frequency is maintained constant or a frequency variable mode according to a variable frequency signal supplied from outside, wherein in the normal mode, a first electrode voltage of the light emitting element is initialized in response to a data voltage being supplied to the storage capacitor, and wherein in the frequency variable mode, the first electrode voltage of the light emitting element is not initialized in response to the data voltage being supplied to the storage capacitor.

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

Abstract: A display panel driver includes: a driving controller receiving input image data and converting the input image data into a data signal and a data driver converting the data signal into a data voltage. The driving controller includes a plurality of lookup tables storing data signal values corresponding to grayscale values of the input image data based on an input maximum luminance, and a total number of the data signal values stored in a first lookup table corresponding to a first input maximum luminance is different from a total number of the data signal values stored in a second lookup table corresponding to a second input maximum luminance.

Abstract: A pixel includes a light emitting element, a first transistor connected to the light emitting element, a second transistor connected between a data line and a first electrode of the first transistor, a third transistor connected between a gate electrode of the first transistor T1 and a second electrode of the first transistor, a fourth transistor connected between a gate electrode of the first transistor and an initialization power source, and a storage capacitor connected between the first power source and the gate electrode of the first transistor. A voltage provided through the data line is time divided into a data voltage provided to the gate electrode of the first transistor when both the second and third transistors turn on, and an on-bias voltage provided to the first electrode of the first transistor when the second transistor turns on and the third transistor turns off.

Abstract: The present disclosure relates to a display panel and a display device using the same, and includes a second pixel area in which pixels having a resolution or pixels per inch (PPI) lower than that of a first pixel area are arranged. A data voltage of pixel data to be written to a pixel in the second pixel area is applied to a first gate electrode of a driving element disposed in the second pixel area. A compensation voltage for increasing luminance of the second pixel area is applied to a second gate electrode of the driving element.

Abstract: A LCD and LED hybrid display screen has a LCD display screen, a LED display screen overlapping with the LCD display screen, and a drive device for driving the LCD display screen and the LED display screen. The LED display screen has at least one LED pattern and each LED pattern comprises a plurality of strokes is corresponding to at least one LED lamp. The drive device drives the LCD display screen to display at least one LCD display pattern and driving the LED lamp to emit light. A LED display pattern formed by a light emitted by the LED lamp and the LCD display pattern are in one-to-one correspondence. A LCD and LED clock with a LCD and LED hybrid display screen is further provided. Different ambient brightness can be adapted while the power consumption can be reduced through overlapping the LCD display screen with the LED display screen.

Abstract: A display device according to the present disclosure includes: a drive circuit array substrate including drive circuits arranged in an array pattern on a semiconductor substrate; and light emitting elements arranged in an array pattern over the drive circuits and driven by the drive circuits, in which in a drive circuit group including a plurality of the drive circuits that are adjacent to each other, a well tap is provided in a part of the drive circuits of the plurality of the drive circuits included in the drive circuit group.

Abstract: A display device can include a display panel having a plurality of subpixels; a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, and output a feedback voltage; a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines; a power management circuit configured to supply a plurality of driving voltages to the gate driving circuit and the data driving circuit, and supply a compensating high-potential gate voltage to the gate driving circuit based on the feedback voltage transferred from the gate driving circuit. The display device can further include a timing controller configured to control the gate driving circuit, the data driving circuit, and the power management circuit.

Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

Abstract: The present disclosure relates to a display driving device and an electronic apparatus, wherein the device comprises a power supply module for outputting a first power supply voltage and a second power supply voltage; and a display panel including a power interface electrically connected to the power supply module. The power supply module is further configured to output a first regulated voltage and/or a second regulated voltage for a target display region from which a distance to the power interface is greater than a preset distance, to regulate a first terminal voltage of a light-emitting transistor in the target display region via the first regulated voltage and/or regulate a second terminal voltage via the second regulated voltage.

Abstract: A comparator circuit according to the present embodiment: including a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit including a data input terminal to which a constant potential is supplied and a clock input terminal and configured to hold a value of the data input terminal based on a self-clock signal input to the clock input terminal; and a clock generation circuit configured to generate the self-clock signal based on the matching signal.

Abstract: A pixel circuit comprises a light emission element; a driving transistor including a first electrode connected to the first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a first transistor including a first electrode receiving a third voltage, a second electrode connected to the first node, and a gate electrode receiving a second light emission control signal; a first transistor including a first electrode connected to a first line transferring a first power voltage, a second electrode connected to the second node, and a gate electrode receiving a first light emission control signal; a first storage capacitor connected between the third node and a fourth node; and a switching transistor including a first electrode connected to a data line, a second electrode connected to the fourth node, and a gate electrode receiving a scan signal.

Abstract: The present disclosure provides a shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor; the second transistor has a first electrode coupled to a second node; the third transistor has a first electrode coupled to a first power terminal and a second electrode coupled to the second node; the fifth transistor has a control electrode coupled to a third node; the impedance transistor has a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

Abstract: In the field of liquid crystal display technology, a liquid crystal display device and a driving method thereof. The driving method includes steps of: detecting whether a light leakage has occurred in the liquid crystal display device; and adjusting a turn-off voltage output from a gate driver to a gate of a switch element to reduce an absolute value of a voltage difference between the turn-off voltage and a common voltage when the light leakage has occurred in the liquid crystal display device. In the embodiments, the phenomenon of light leakage at the dislocation caused by the dislocation between the color filter substrate and the array substrate when the liquid crystal display device is subjected to external pressure can be effectively improved, thereby improving the display effect of the liquid crystal display device.

Abstract: A display panel includes at least one pixel circuit and a light emitting element. One pixel circuit includes a driving transistor, and second and third transistors. The second transistor is connected between data line and a source of the driving transistor. The third transistor is connected between voltage adjusting signal line and the source. During a data writing phase, the second transistor is turned on, the data line provides data signal equal to VData to the source, a gate of the driving transistor receives the data signal, and voltage of the gate is VData+Vth. Vth denotes threshold voltage of the driving transistor. During a reset and adjustment phase, the third transistor is turned on, the voltage adjusting signal line provides adjusting voltage to the source, voltage of the source of the driving transistor is VJ, and the voltage of the gate remains VData+Vth. VData+Vth?VJ??2V.

Abstract: A display device is disclosed that includes a pixel. The pixel includes a first transistor connected between a second node and a third node and including a gate electrode connected to a first node. A first capacitor is formed between the first node and a fourth node. A second capacitor is formed between the fourth node and a first power line. A second transistor is connected between a data line and the fourth node. An eighth transistor is connected between the first power line and the second node. A ninth transistor is connected between the second node and a bias power line. A sixth transistor is connected between the third node and a fifth node. A light emitting element is electrically connected between the fifth node and a second power line. A gate electrode of the eighth transistor and a gate electrode of the sixth transistor are connected to different gate lines.

Abstract: A display device is disclosed that includes a display panel including a pixel and a scan driver to provide a first scan signal to a third scan signal to the pixel. The pixel includes a light emitting element, a first transistor connected between a first voltage line and the light emitting element, a second transistor connected between a data line and a first node, a gate electrode of the second transistor to receive a first scan signal, a third transistor connected between the second node and the first transistor, a gate electrode of the third transistor to receive a second scan signal, and a fourth transistor connected between a first initialization voltage line, which is to receive a first initialization voltage, and the second node, a gate electrode of the fourth transistor to receive a third scan signal. The first to third scan signals include first to third activation sections, and the first to third activation sections have an equal duration.

Abstract: A pixel compensation circuit and a driving method thereof are provided. The pixel compensation circuit includes a resetting unit, a write-in unit, a light-emitting unit, a storage capacitor and a driving transistor. The resetting unit is configured to receive a resetting signal and release electric energy on the storage capacitor and an electroluminescence element. The write-in unit is configured to receive a gate driving signal and write display data into a holding node coupled to the storage capacitor. The light-emitting unit is configured to receive a light-emitting signal and turn on the driving transistor to enable the electroluminescence element to emit light. A compensation unit is added between the holding node and a high potential end and configured to generate a reverse current for compensating a leakage current of the resetting unit.

Abstract: The application discloses a liquid crystal display panel and a display device. In the liquid crystal display panel, each pixel unit includes a first sub-pixel and a second sub-pixel. The polarities of the data voltages received by two adjacent pixel units sharing the same data line are opposite. In each pixel unit, the driving timing of the first sub-pixel is earlier than the driving timing of the second sub-pixel, and the duty cycle of the scan signal received by the first sub-pixel is greater than the duty cycle of the scan signal received by the second sub-pixel.

Abstract: According to some aspects of the disclosure, an organic light-emitting display device including a display panel including a driving thin film transistor (TFT), comprises a sensing unit configured to perform a sensing operation for external compensation of the display panel, and an analog-digital converter (ADC) configured to perform a conversion operation of converting an analog value held in the sensing unit into a digital value, wherein the sensing unit comprises a basic sensing unit configured to perform a sensing operation on the driving TFT, and a dummy sensing unit configured to perform a sensing operation on changes in a gain and an offset of the ADC, and the basic sensing unit and the dummy sensing unit are in a cascade connection to each other.

Abstract: The present disclosure, which relates to a technology for controlling power of a display device, allows reducing power consumption by driving circuits for a display operation and circuits for a touch sensing operation with low power depending on a display operation or a touch sensing operation of a display panel.

Abstract: An OLED display panel is provided. The OLED display panel includes a plurality of sub-pixels arranged in an array and a plurality of pixel drive circuits for driving the sub-pixels. At least one of the pixel drive circuits comprises a reset module, a data signal input module, a storage module, a light emitting device, and a drive module. The drive module drives a first light emitting device and a second light emitting device to emit light in a first display stage, and drives the first light emitting device to emit light in a second display stage, whereas the second light emitting device does not emit light.

Abstract: Provided are a pixel circuit, a driving method thereof and a display panel. The pixel circuit includes: multiple sub-pixel circuits in an array; each sub-pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a driving sub-circuit, a storage sub-circuit, a reading sub-circuit and a light emitting device; at least reading sub-circuits of the sub-pixel circuits of some rows are controlled by a same sensing control line; the first node control sub-circuit charges the storage sub-circuit in response to a first scan signal; the second node control sub-circuit writes a reference voltage signal into a second node in response to a second scan signal; the reading sub-circuit reads a potential of the second node in response to a sensing control signal written by a sensing control line; the driving sub-circuit drives the light emitting device to emit light.

Abstract: A display panel and a display device are disclosed. By disposing a binding film over a gap between adjacent circuit boards, and then forming connection wires on the binding film, connections between different circuit boards are achieved. The present disclosure solves a problem of high costs caused by traditional flexible circuit boards and connectors, thereby saving a large number of connectors and flexible circuit boards, and thereby reducing costs significantly.

Abstract: Presented herein are techniques in which a software-controlled load is embedded at an output of a point of load (POL) in parallel to a load that receives power from the POL. A small incremental load is applied to the POL using the software-controlled load. A transient response of the POL to the applied small incremental load is measured using an embedded analysis functionality.

Abstract: Disclosed is a lighting control system for directing a show. The system includes at least: a master device; and a plurality of slave devices that receive lighting control signals from the master device. The light control signals correspond to seats of a plurality of audiences in an auditorium. The plurality of slave devices receive position information indicating specific positions at which the plurality of slave devices emit a light, light-emitting status information including preset information to classify the plurality of slave devices into a plurality of groups, and group identification number information. The plurality of slave devices are grouped in accordance with received information. The master device controls the grouped plurality of slave devices to emit a light per group basis by broadcasting the lighting control signals including group light-emitting pattern information for each of the plurality of groups of the plurality of slave devices.

Abstract: A display apparatus including: a display panel including a plurality of display blocks; and a display panel driver configured to generate a power voltage based on a maximum grayscale value of input image data and a position of a maximum load block among the display blocks and configured to output the power voltage to the display panel, wherein the maximum load block has a largest load of the input image data among the display blocks.

Abstract: The present application discloses a display device capable of performing favorable display in which flicker is not visually recognized while the power consumption of a scanning-side drive circuit, as well as a data-side drive circuit, can be reduced sufficiently when pause driving is performed. A pixel circuit including emission control transistors M5, M6 in addition to a drive transistor M1 includes a switching element that is turned on based on a voltage of an emission control line Ei to initialize an organic EL element OL when the voltage of the emission control line Ei is at a level for turning off the emission control transistors M5, M6. For example, in some embodiments, the anode electrode of the organic EL element OL is connected to an initialization voltage line Vini via an N-channel transistor M7 serving as the switching element, and the emission control line Ei is connected to the gate terminal of the transistor M7.

Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: an input control circuit, configured to control a level of the first node; a first control circuit, configured to control a level of the second node; a second control circuit, configured to control the level of the second node under control of a fourth clock signal and an output signal; an output circuit, configured to control a level of the output terminal under control of the level of the first node and the level of the second node; and a first reset circuit, configured to control the level of the output terminal under control of the first enable signal, so as to allow the output terminal to stably output a non-operating level during a detection phase.

Abstract: A drive circuit of a display panel and a display device are provided in the disclosure. The drive circuit includes a voltage output module. The voltage output module includes a voltage input terminal, a voltage output terminal, a detection module, and an isolation module. The voltage input terminal is configured to receive a voltage signal. The voltage output terminal is electrically coupled with the display panel. The detection module is electrically coupled with the voltage input terminal and configured to determine whether a voltage value of the voltage signal received at the voltage input terminal is greater than or equal to a preset voltage threshold. The detection module is configured to output a second control signal when the voltage value of the voltage signal is less than the preset voltage threshold.

Abstract: A dimming method and device of a display panel, a storage medium, and a terminal equipment are provided. In a second dimming stage in a frame of one frame of an image, a grayscale of a light-emitting stage of the display is controlled by the light-emitting signal. In a first dimming stage in the frame of the image, the grayscale of the light-emitting stage of the display panel is controlled by superposing a control signal in the light-emitting signal. Therefore, in a low grayscale, the grayscale is realized by reducing an amplitude of the light-emitting signal.

Abstract: According to an aspect of the present disclosure, there is provided a gate driver and a display device. The display device includes: a display panel having a plurality of sub-pixels defined thereon, the sub-pixels being connected to a plurality of scan lines; and a gate driver comprising a plurality of stages for supplying first and second scan signals to each of the plurality of scan lines. Each of the plurality of stages may include: a first output unit for outputting the first scan signal; a second output unit for outputting the second scan signal; a logic unit connected to the first output unit and the second output unit; a low-clock signal line connected to the logic unit; and a high-clock signal line connected to the second output unit. Therefore, a first and a second scan signal can be output from a single stage, so that the structure of the gate driver can become simpler.

Abstract: A repair pixel and a display apparatus including the repair pixel, the display panel including a repair pixel for a pixel row or a plurality of repair pixels for a pixel row so that repair may be performed using the repair pixel when a bad pixel occurs in the corresponding pixel row. The bad pixel is repaired using the repair pixel so that the yield of the display panel may be enhanced.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: An electronic device including a panel, a Chip on Film and a flexible circuit board is disclosed. The panel includes a first gate driver, a switch transistor and a driving transistor. An output terminal of the switch transistor is coupled to a control terminal of the driving transistor. The first gate driver is used for receiving an AC signal and a DC signal and outputting a control signal to a control terminal of the switch transistor. The Chip on Film is electrically connected to the panel and used for transmitting a data signal to an input terminal of the switch transistor and transmitting the AC signal to the first gate driver. The flexible circuit board is electrically connected to the panel and used for transmitting a power signal to an input terminal of the driving transistor and transmitting the DC signal to the first gate driver.

Abstract: An electronic apparatus is provided.

Abstract: The present disclosure provides a display substrate, a manufacturing method and a display device. At least one of the plurality of shift register units in the scan driving circuit includes an output circuit including an output transistor and an output reset transistor; a length of the active layer of the output transistor/the output reset transistor in the first direction is a first length/a second length, and a sum thereof is an output active length; a smaller one of minimum width of the active layer of the output transistor and the output reset transistor in a second direction is a first output active width, the first direction intersects the second direction; a ratio of the output active length to the first output active width is within a first predetermined ratio range greater than or equal to 3 and less than or equal to 11.

Abstract: The display device includes a first data line group including data lines connected to pixels arranged at a first resolution; a second data line group including data lines connected to pixels arranged at the first resolution and pixels arranged at a second resolution; a first gamma compensation voltage generation unit that divides a first reference voltage and outputs a gamma compensation voltage; a second gamma compensation voltage generation unit that divides a second reference voltage and outputs gamma compensation voltages; a first data drive unit that converts pixel data into the gamma compensation voltage output from the first gamma compensation voltage generation unit and outputs a data voltage to the first data line group; and a second data drive unit that converts pixel data into the gamma compensation voltage output from the second gamma compensation voltage generation unit and outputs a data voltage to the second data line group.

Abstract: The present disclosure, which relates to a technology for controlling power of a display device, allows reducing power consumption by driving circuits for a display operation and circuits for a touch sensing operation with low power depending on a display operation or a touch sensing operation of a display panel.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a plurality of pixels and a data line formed adjacent to the pixels and configured to transfer a data voltage. The display also includes a driving voltage line formed substantially parallel to the data line and configured to transfer a driving voltage, and an initialization voltage line formed substantially parallel to the data line and configured transfer an initialization voltage. At least one of the pixels includes a driving transistor including a driving gate electrode and configured to receive the initialization voltage from the initialization voltage line. A driving connector is spaced apart from the data line and electrically connected to the driving gate electrode. An OLED is electrically connected to the driving transistor, at least one of the initialization voltage line and the driving voltage line interposed between the driving connector and the data line.