METHOD TO AUTOMATICALLY ADD POWER LINE IN CHANNEL BETWEEN MACROS
A method includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
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This application claims priority from and is a divisional application of U.S. patent application Ser. No. 12/270,475, filed Nov. 13, 2008, entitled “METHOD TO AUTOMATICALLY ADD POWER LINE IN CHANNEL BETWEEN MACROS,” the contents of which are incorporated by reference herein in its entirety.
FIELD OF THE DISCLOSUREThe present disclosure is generally directed to a method to automatically add at least one power line with proper polarity or at least two power lines with opposite polarities in a channel between at least two macros.
BACKGROUNDComplex application-specific integrated circuit (ASIC) and/or a system on a chip (SoC) designs use large numbers of hard macro cells, such as memory cells and/or mixed-signal devices. The macros are generally placed in clusters due to timing and/or physical constraints. The clustering of hard macro cells can be so large that signal delay on wire connections to, from and/or through the macro cell clusters becomes of concern for ASIC/SoC performance. Gaps between pairs of macro cells may be defined as channels when the gaps are smaller than certain threshold values. Buffering in the channels is an efficient way to speed up signals on wire connections. To enable buffering, the power grid integrity in the channels should be guaranteed. The power grid integrity in a channel may mean that there should be at least two power supply lines with opposite polarities (one power line and one ground line) existing in that channel. Typically, the size of the channels (width for vertical channels or height for horizontal channels) between the macro cells is not large enough to satisfy the power grid integrity requirement.
One conventional solution is to allocate larger channels to allow at least two power lines with opposite polarities to be present in the channels. However, this may lower the macro device placement density and therefore increase the size of the die chip, which increases the cost of the final products. Another conventional solution is to manually patch individual channels that are intended to be used. However, manual patching is a time-consuming, tedious and error-prone process, and the results may not be consistently repeatable.
SUMMARYIn a particular embodiment, a method is disclosed that includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a. threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
In another embodiment, an automated circuit design tool is disclosed that includes a non-transitory processor-readable medium having processor-executable instructions that are executable to cause a processor to detect channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The processor-executable instructions are also executable to cause the processor to automatically add at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
In another embodiment, an apparatus is disclosed that includes means for detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The apparatus also includes means for automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
In another embodiment, a computer-readable medium embodying computer-readable data comprising a data file that represents a circuit designed using an automated circuit design tool is disclosed. The circuit includes a first channel between at least two macros disposed in the circuit such that a shortest distance between the at least two macros satisfies a threshold value. The circuit also includes a first power line that is automatically added in the first channel by an automated circuit design tool in response to detecting a power integrity issue within the first channel. The power integrity issue is satisfied by two power lines having opposite polarity being coupled to provide power to a device within the first channel.
In another embodiment, a circuit designed using an automated circuit design tool is disclosed. The circuit includes a first channel between at least two macros disposed in the circuit such that a shortest distance between the at least two macros satisfies a threshold value. The circuit also includes a first power line that is automatically added in the first channel by the automated circuit design tool in response to detecting a power integrity issue within the first channel. The power integrity issue is satisfied by two power lines having opposite polarity being coupled to provide power to a device within the first channel.
One particular advantage provided by the disclosed embodiments is that a power grid integrity in channels to enable buffering in the channels can be accomplished by an automated design tool within regular machine run time.
Another advantage provided by the disclosed embodiments is that the automated design can be repeated with the same results consistently.
Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.
Referring to
The method may include automatically detecting the number of power supply lines in the channel 130, the polarities of the power supply lines in the channel, and then adding the first power line 160 with proper polarity in the channel 130 between at least two macros 110, 120 when less than two system power supply lines 150 with opposite polarities are detected within the channel 130. As used herein, “opposite” polarities indicate different voltages that are applied to the power supply lines. As illustrative, non-limiting examples, a positive voltage may be opposite to a ground voltage, a negative voltage may be opposite to a ground voltage, or a negative voltage may be opposite to a positive voltage, based on voltages that are used to power the ASIC/SoC. As used herein, a “proper” polarity of an automatically added line when a line is detected in the channel (such as the line 150) is a polarity opposite to the polarity of the detected line. A “proper” polarity of an automatically added line when no lines are detected in the channel (such as will be discussed with respect to
By using an automatic method, the power grid integrity in channels to enable buffering in the channels can be accomplished by an automated design tool within regular machine run time. In addition, by using an automatic method, the automated design can be repeated with the same results consistently.
Referring to
As depicted in the particular embodiments shown in
Referring to
in a particular embodiment, the first power line 160 has the polarity opposite to the polarity of the second power line 360. For example, if the polarity of the first power line 160 is positive, the polarity of the second power line 360 will be chosen to be ground. Similarly, if the polarity of the first power line 160 is ground, the polarity of the second power line 360 will be chosen to be positive.
Referring to
In a particular embodiment, the method to automatically add a power line to a channel may duplicate the methods of
Referring to
In general, a power line may be automatically added to a channel, such as in
Referring to
In operation, the processor 504 may be configured to access the circuit detection instructions 510, the threshold values 514, and the circuit layout 516 to detect whether there is a channel between at least two macros. If a channel is detected between a first macro and a second macro, the processor 504 may be configured to access the circuit detection instructions 510 and the circuit layout 516 to detect whether there are less than two system power supply lines with opposite polarities within the channel. If there are less than two system power supply lines with opposite polarities within the channel, the processor 504 may be configured to access the automated design tool instructions 508, the circuit tool instructions 512, and the circuit layout 516 to automatically add a first power line with proper polarity in the channel.
For example, the processor 504 may be configured to implement an automatic method to add the first power line 160 in the channel 130,430 as illustrated in
Referring to
The method 600 may further include determining whether the at least one channel is a vertical channel, as in
Referring to
As illustrated in
The system power supply line 150 and the additional power lines 160 and 360 shown in
The particular illustrative embodiment of automatically adding a power line in a vertical channel depicted and generally designated 700 is also applicable to the horizontal channel case, as shown in
Referring to
In a particular embodiment, automatically patching the power grid integrity issue for a horizontal channel may further include connecting a system power supply line disposed in an upper metal layer of the integrated circuit, such as the M6 layer 824 shown in
Referring to
The method 900 includes determining whether there is less than one system power supply line in the channel, as indicated at 914. If there is not less than one system power supply line in the channel, then another macro is considered, as indicated at 910, If there is less than one system power supply line 150 in the channel 130, then a second power line 360 with a polarity opposite to the polarity of the first power line 160 should be added to the channel 130. The method 900 includes adding the second power line in the channel automatically, as indicated at 916. The method 900 includes considering another macro, as indicated at 910. In a particular embodiment, the method 900 may be used to automatically consider substantially all macros in an integrated circuit.
Referring to
The method 1000 includes determining for vertical channels if at least one pair of power/ground stripes (two power supply lines with opposite polarities) exists in the vertical channel, as indicated at 1012 (as in the particular illustrative embodiments shown in
The method 1000 includes determining for horizontal channels if at least a pair of power/ground stripes exists in the horizontal channel, as indicated at 1008 (as in the particular illustrative embodiments shown in
If the M6 metal layer is to be used, then the method 1000 includes determining whether one or none of Vdd and Vss exists in the horizontal channel, as indicated at 1030 (as shown in
If the MS metal layer is to be used (as shown in
Referring to
In a particular embodiment, the processor executable instructions are further executable to add one or more additional devices between a first macro 110 and a second macro 120. In this particular embodiment, the additional devices between the first macro 110 and the second macro 120 may include decoupling capacitors, substrate well connectors, buffers, inverters, or any combination thereof, as shown by the device 200 in
In a particular embodiment, the processor executable instructions are further executable to determine whether the at least one channel is a vertical channel, as in
Referring to
The circuit 1400 may be designed using an automated circuit design tool. The circuit 1400 includes a first vertical channel 1402 between a first pair of macros 1404, 1406 with a first patch 1407 disposed in the first vertical channel 1402. The first patch includes at most one additional power line 1408 automatically added to the first vertical channel 1402. A first system power supply line 1410 is disposed in the first vertical channel 1402. The circuit 1400 includes a second vertical channel 1412 between a second pair of macros 1414, 1416 with a second patch 1417 disposed in the second vertical channel 1412. The second patch 1417 includes two additional power lines 1418, 1420 automatically added to the second vertical channel 1412. The circuit 1400 includes a first horizontal channel 1422 between a third pair of macros 1404, 1414 with a third patch 1427 disposed in the first horizontal channel 1422. The third patch 1427 includes at most one additional power line 1428 automatically added to the first horizontal channel 1422. A second system power supply line 1430 is disposed in the first horizontal channel 1422. The circuit 1400 includes a second horizontal channel 1432 between a fourth pair of macros 1406, 1446 with a fourth patch 1437 disposed in the second horizontal channel 1432. The fourth patch 1437 includes two additional power lines 1438, 1440 automatically added to the second horizontal channel 1432.
In a particular embodiment, the first patch 1407 and the second patch 1417 may connect a system power supply line disposed in an upper metal layer of an integrated circuit, such as the M6 layer 724 shown in
The circuit 1400 may include at least one device 1452 coupled to the additional first power line 1448 in the channel 1442. In a particular embodiment, the at least one device 1452 may also be coupled to an additional second power line 1450 in the channel 1442. In a particular embodiment, the at least one device 1452 is a decoupling capacitor, a substrate well connector, a buffer, or an inverter.
Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of Me present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a retrievable disk, a compact disk read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal in the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.
Claims
1. A method comprising:
- detecting channels between macros in an integrated circuit, wherein each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value; and
- automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel, wherein the power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
2. The method of claim 1, wherein the device is coupled to at least one of a macro or signals propagating through the at least one channel.
3. The method of claim 1, wherein the device is one of a decoupling capacitor to reduce power grid noise, a substrate well connector to prevent a latch-up violation, a buffer to reduce a propagation delay of signals in the at least one channel, or an inverter to reduce a propagation delay of signals in the at least one channel.
4. The method of claim 1, further comprising detecting a power grid integrity within the channels prior to adding the at least one power line within the at least one channel.
5. The method of claim 1, wherein the at least one channel is a vertical channel or a horizontal channel.
6. The method of claim 5, wherein a first system power supply line disposed in a first metal layer of the integrated circuit connects with a first power line of the two power lines, and wherein a second system power supply line disposed in a second metal layer of the integrated circuit connects with a second power line of the two power lines.
7. The method of claim 6, wherein the first power line and the second power line are disposed in a metal layer of the integrated circuit that is different than the first metal layer and the second metal layer.
8. An automated circuit design tool comprising a non-transitory processor-readable medium having processor-executable instructions that are executable to cause a processor to:
- detect channels between macros in a circuit layout, wherein each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value; and
- automatically add at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel, wherein the power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
9. The automated circuit design tool of claim 8, wherein the device is coupled to at least one of a macro or signals propagating through the at least one channel.
10. The automated circuit design tool of claim 8, wherein the device is one of a decoupling capacitor to reduce power grid noise, a substrate well connector to prevent a latch-up violation, a buffer to reduce a propagation delay of signals in the at least one channel, or an inverter to reduce a propagation delay of signals in the at least one channel.
11. The automated circuit design tool of claim 8, wherein the processor-executable instructions are further executable to cause the processor to detect a power grid integrity within the channels prior to adding the at least one power line within the at least one channel.
12. The automated circuit design tool of claim 8, wherein a first system power supply line disposed in a first metal layer of the circuit layout connects with a first power line of the two power lines, and wherein a second system power supply line disposed in a second metal layer of the circuit layout connects with a second power line of the two power lines.
13. The automated circuit design tool of claim 12, wherein the first power line and the second power line are disposed in a metal layer of the circuit layout that is different than the first metal layer and the second metal layer.
14. An apparatus comprising:
- means for detecting channels between macros in an integrated circuit, wherein each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value; and
- means for automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel, wherein the power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.
15. The apparatus of claim 14, wherein the device is coupled to at least one of a macro or signals propagating through the at least one channel.
16. The apparatus of claim 14, wherein the device is one of a decoupling capacitor, a substrate well connector, a buffer, or an inverter.
17. A non-transitory computer-readable medium embodying computer-readable data comprising a data file that represents a circuit designed using an automated circuit design tool, the circuit comprising:
- a first channel between at least two macro disposed in the circuit such that a shortest distance between the at least two macro satisfies a threshold value; and
- a first power line, wherein an automated circuit design tool automatically added the first power line in the first channel in response to detecting a power integrity issue within the first channel, wherein the power integrity issue is satisfied by two power lines having opposite polarity being coupled to provide power to a device within the first channel.
18. The non-transitory computer-readable medium of claim 17, wherein the device is coupled to at least one of a macro or signals propagating through the first channel.
19. The non-transitory computer-readable medium of claim 17, wherein the device is one of a decoupling capacitor, a substrate well connector, a buffer, or an inverter.
20. A circuit designed using an automated circuit design tool, the circuit comprising:
- a first channel between at least two macro disposed in the circuit such that a shortest distance between the at least two macro satisfies a threshold value; and
- a first power line, wherein the automated circuit design tool automatically added the first power line in the first channel in response to detecting a power integrity issue within the first channel, wherein the power integrity issue is satisfied by two power lines having opposite polarity being coupled to provide power to a device within the first channel.
21. The circuit of claim 20, wherein the device is coupled to at least one of macro or signals propagating through the first channel.
22. The circuit of claim 20, wherein the device is one of a decoupling capacitor, a substrate well connector, a buffer, or an inverter.
Type: Application
Filed: Sep 10, 2013
Publication Date: Jan 9, 2014
Applicant: QUALCOMM Incorporated (San Diego, CA)
Inventor: Li Qiu (Palo Alto, CA)
Application Number: 14/022,310