Abstract: A computer-implemented method of selecting a power-optimal compression scheme for transmitting digital control signals from a classical interface of a quantum computer to a quantum processing unit (QPU) of the quantum computer is disclosed. The method involves receiving static and dynamic power consumption values associated with operations performable by the QPU; determining compression schemes implementable by the QPU; calculating total power consumption values associated with receiving and decompressing a representative control signal at the QPU using the compression schemes; and selecting the compression scheme having the lowest total power consumption value. A corresponding method for transmitting control signals from a classical interface of the quantum computer to the QPU is also disclosed in which a compressed control signal is transmitted from the classical interface to the QPU with one or more delays.

Abstract: A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second outputs of the cell in the compiled circuit design replace a plurality of outputs of the plurality of circuit elements.

Abstract: Described are platforms, systems, and methods for real-time enrichment of vertices, edges, and related data within a graph database. The platforms, systems, and methods maintain a graph database comprising a representation of a current state of an automation environment comprising a plurality of data sources, wherein the data sources are represented as vertices in the graph database and relationships between the individual data sources are represented as edges in the graph database; operate a plurality of software agents, each software agent configured to perform operations comprising: applying an algorithm to identify patterns in the graph database; and generating a specific data enrichment based on one or more identified patterns; and contribute the generated data enrichment back to the graph database.

Abstract: Various implementations described herein refer to a method for providing a cell layout with a power grid distribution network. The method may include analyzing porosity of the cell layout to identify blocked tracks and unblocked tracks. The method may include marking the unblocked tracks as available sites for stitching power rails of the cell layout to the power grid distribution network. The method may include generating a porosity report for the cell layout, and the porosity report may list the available sites as modifiable to enhance power grid porosity of the cell layout.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: A system for controlling energy consumption. The system may incorporate devices configured on a floor map, a monitor that detects energy consumption by each device, a heat map shown on the floor map, a processor, and a user interface having a display connected to the processor. The heat map may indicate energy consumption in various areas of the floor plan. The floor map with the heat map may be a screen on the display. The energy consumption by each of the devices from the monitor may be calculated by the processor in time that each device is active and in a power rating of the respective device. The energy consumption by each of the devices may be converted by the processor into cost. From a screen, a user may define a virtual and dynamic zone to optimize and control the energy consumption.

Abstract: A semiconductor structure includes: a buried power rail disposed between a first fin structure and a second fin structure on a substrate extending in a first direction in a horizontal plane, the first fin structure located in a first cell, the second fin structure located in a second cell abutting the first cell at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal track disposed in a M1 layer extending in a second direction in the horizontal plane. At an intersection of the buried power rail and the M1 metal track, the semiconductor structure further includes an electrically conductive path to provide the first voltage to the M1 metal track, the electrically conductive path having a first metal zero (M0) metal track extending in the first direction over the boundary line.

Abstract: An inductive wireless power transfer apparatus includes a source coil coupled to a power source such that current flows through the source coil when the source coil is excited by the power source. The apparatus further includes a first capacitor coupled in series to the source coil. The apparatus further includes an intermediate coil surrounding the source coil and positioned within an identical plane as the source coil, and a second capacitor coupled in series to the intermediate coil. The capacitances of the first capacitor and the second capacitor are set to tune out self-inductances of the source coil and the intermediate coil. In embodiments, the source coil is to inductively power the intermediate coil, which is to inductively power a load coil positioned a distance away from the intermediate coil.

Abstract: A method is disclosed for optimizing the power flow in an electric power network including a plurality of buses interconnected by transmission lines, and locally connected to loads, generators, and storage devices, the method executing an interior point optimisation algorithm in a computer system to solve an optimal control problem, which is defined over a time period of interest T, and is associated with an objective function representing the total fuel consumption of the generators for the time period of interest T, wherein the objective function depends on a plurality of parameters of the network, such as bus voltages, generator, and storage device powers. the parameters of the network allowed to vary over a large number N of predefined time intervals, each of duration ?t, obtained by subdivisions of the time period of interest T and is subject to network constraints.

Abstract: A system and method generates cluster-based power architecture interfaces for an integrated circuit (IC) design under test (DUT) debugging by receiving design data for an IC DUT, determining power characteristic data for the IC DUT, generating display components within a graphical user interface (GUI) corresponding to individual components encompassed within a power intent hierarchy corresponding with the IC DUT, generating graphical links between displayed components, overlaying interactive elements corresponding with generated violation clusters over graphical links, and providing root-cause interactive elements within the generated GUI having visual associations with the interactive components corresponding with particular violation clusters.

Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Abstract: A system for controlling energy consumption. The system may incorporate devices configured on a floor map, a monitor that detects energy consumption by each device, a heat map shown on the floor map, a processor, and a user interface having a display connected to the processor. The heat map may indicate energy consumption in various areas of the floor plan. The floor map with the heat map may be a screen on the display. The energy consumption by each of the devices from the monitor may be calculated by the processor in time that each device is active and in a power rating of the respective device. The energy consumption by each of the devices may be converted by the processor into cost. From a screen, a user may define a virtual and dynamic zone to optimize and control the energy consumption.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.

Abstract: A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.

Abstract: A method generates scan patterns for testing an electronic device called DUT having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. A scan test interface has a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern. The method determines at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode, and generates, in addition to the scan pattern, a scan clock pattern indicative of stretching the power shift cycle. Advantageously, a relatively high scan shift frequency may be used while avoiding detrimental effects of said voltage drop by extending the respective power shift cycle, whereby test time and yield loss are reduced.

Abstract: This application discloses a computing system to identify an interconnection between portions of a circuit design corresponding to different power domains. The computing system can select a subset of power state tables in the circuit design based, at least in part, on power supplies associated with the interconnection, and generate a composite power state table from the selected subset of power state tables. The computing system can analyze the interconnection to identify electrical characteristics based, at least in part, on power states in the composite power state table, and determine whether a power intent specification in the circuit design can prompt synthesis of interface circuitry capable of implementing the electrical characteristics for the interconnection.

Abstract: Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

Abstract: A method for dynamically reconfiguring logic circuits on an FPGA includes the steps of: classifying a general function into sets of static functions and modal functions to be implemented on the FPGA; for each of the modal functions, generating a list of one-active actions; devising a circuit topology including at least a subset of look-up tables (LUTs) such that any one of the modal functions can be implemented at a time on the devised circuit topology; for each modal function, associating the devised circuit topology with a controller adapted to load a LUT configuration corresponding to a prescribed one of the one-active actions; implementing a single fixed circuit on the FPGA including devised circuit topologies for each of the modal functions; and updating contents of LUTs corresponding to the LUT configuration in the devised circuit topology when a change in modal function to be implemented on the FPGA is required.

Abstract: An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the fabrication process. Target clock drive strengths are determined to reduce skew along the clock-distribution network, and the standard size cells are combined to produce clock-driving components substantially equal to the target clock drive strengths. The cells are combined using VIA programming, by electrically coupling them by adding or removing vias connecting the cells. In hybrid tree-mesh clock distribution networks, VIA programming ensures that the binary tree portions of the network are not affected by the tuning. Preferably, the clock-driving elements are clock inverters or buffers, though other elements are able to be used to drive clock signals on the clock distribution network.

Abstract: A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a second pass gate. The first pass gate is between the first data line and the data node. The second pass gate is between the second data line and the data node. The clamping unit is electrically coupled to the first data line and configured to pull a voltage level of the first data line toward a clamped voltage level when the clamping unit is enabled, and to function as an open circuit to the first data line when the clamping unit is disabled. The clamping unit is disabled when a first control signal indicates that a voltage level of the second data line is pulled toward a reference voltage level.

Abstract: A method uses time-domain reflectometry to measure a signal reflection delay in a conductive trace formed on a specific passive printed circuit board, and uses the measured signal reflection delay as an index into a table storing a predetermined association between signal reflection delay and passive printed circuit board manufacturing information, wherein the table includes a plurality of predetermined signal reflection delay values, and wherein each of the predetermined signal reflection delay values is associated with unique passive printed circuit board manufacturing information. During manufacturing of the passive printed circuit board, a hole is drilled through the passive printed circuit board so that the hole intersects with the conductive trace and divides the conductive trace into a proximal segment extending from the connector to the hole and a distal segment that is electrically isolated from the proximal segment by the hole.

Abstract: A method of designing a fin-based transistor for power optimization includes following steps. A planar field-effect transistor (planar-FET) design including a plurality of planar semiconductor devices is received. An initial fin field-effect transistor (FinFET) design including a plurality of fin-based semiconductor devices corresponding to the planar semiconductor devices is generated. A timing analysis is performed to the initial FinFET design to recognize at least a critical path and at least a non-critical path in the initial FinFET design. The non-critical path includes at least one of the fin-based semiconductor devices. The fin-based semiconductor device on the non-critical path is adjusted and thus a refined FinFET design is generated. A current required by the refined FinFET design is lower than a current required by the initial FinFET design.

Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Abstract: An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit.

Abstract: One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

Abstract: In one aspect, a technique for performing signal activity extraction in an integrated circuit an integrated circuit is described. The integrated circuit includes multiple nodes. The technique includes compiling a design of the integrated circuit, estimating signal activities at the nodes, determining a node of interest from the nodes, and connecting a signal activity circuit to the node of interest. The determination of the node of interest and the connection of the signal activity circuit to the node of interest first compared to the remaining nodes of the integrated circuit improves efficiency in determining nodes of the integrated circuit at which signals can be analyzed first. Such signal activity extraction may involve power analysis and power optimization.

Abstract: A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS.

Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.

Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.

Abstract: A method of constructing an RF filter comprises designing an RF filter that includes a plurality of resonant elements disposed, a plurality of non-resonant elements coupling the resonant elements together to form a stop band having a plurality of transmission zeroes corresponding to respective frequencies of the resonant elements, and a sub-band between the transmission zeroes. The non-resonant elements comprise a variable non-resonant element for selectively introducing a reflection zero within the stop band to create a pass band in the sub-band. The method further comprises changing the order in which the resonant elements are disposed along the signal transmission path to create a plurality of filter solutions, computing a performance parameter for each of the filter solutions, comparing the performance parameters to each other, selecting one of the filter solutions based on the comparison of the computed performance parameters, and constructing the RF filter using the selected filter solution.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.

Abstract: An energy consumption simulation and evaluation system for embedded device in energy consumption evaluation technology for electronic devices, which solves the problem that the energy consumption cannot be simulated under tasks operation condition with the existing systems.

Abstract: A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.

Abstract: An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.

Abstract: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: Automatically accesses, from a database, the rate of power consumption of each object on a displayed list and automatically calculating the power consumption of each object over a planned period time of use of the object. Then, during actual use, the actual power consumption of each object on the list is automatically tracked over the planned period of time of use and the difference between the planned and actual power consumption of each object on the list is automatically calculated. The difference for each object on the list is displayed so that the user may take action interactively.

Abstract: Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.

Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes. In some embodiments, multiple adjacent devices as identified as interface devices for purposes of the analysis. One situation where it may be useful to analyze a larger portion of the circuitry in this way where the analysis is being performed on a netlist having a power gate.

Abstract: A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a memory cell array; calculating power supply noise of a power supply system that occurs when a current is supplied to an equivalent circuit of the power supply system under a predetermined condition, the power supply system including a power supply line and an element for supplying a power supply voltage from a voltage source to a semiconductor device; calculating, from the variation characteristics, the electric potential obtained when the power supply noise is equal to a specific magnitude; and determining, by comparing the calculated electric potential with a threshold, whether memory latch-up will occur in the specific memory cell.

Abstract: Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.

Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification.

Abstract: A retention synthesis application provides a means of analyzing a circuit design, functional test sequences, and the associated power specification to identify registers that do not need retention when a block is powered down. Reducing the number of retention registers reduces power consumption and chip area. The retention synthesis application is based, at least in part, upon symbolic simulation. In symbolic simulation, a symbol is used to represent a value that can be either 0 or 1 and the propagation of symbols is traced through the simulation.