DRIVING CIRCUIT
A driving circuit for connecting a display module is provided. The driving circuit includes a polarity control module, an output control module, and a detecting module. The polarity control module provides a polarity control signal. The output control module is connected with the polarity control module and provides a plurality of output control signals. The detecting module is coupled with the polarity control module and the output control module, wherein the detecting module detects the polarity control signal and selectively controls the output control module to operate in at least one of a first control mode and a second control mode to control the output control signals.
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This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 101137742 filed in Taiwan, R.O.C. on Oct. 12, 2012, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to a driving circuit; particularly, the present invention relates to a source driving circuit having a judgment mechanism and capable of decreasing the noise.
2. Description of the Prior Art
In general, displays are widely used in computers, ATMs, TVs, electrical billboards, cellphones, etc. For instance, the types of displays include cold-cathode fluorescent lamps (CCFLs), plasma displays, LCDs, LED displays, or other displays. In practical applications, the LCD has advantages such as light weight, thin dimension, highly energy saving, low price, etc., and further becomes the most popular display. In addition, R&D (research and development) people try to study more excellent display technology so as to increase efficiency and specification of displays.
Particularly, the conventional display has a driving circuit and a display module, wherein the driving circuit generates a plurality of polarity control signals, a plurality of output control signals, and a plurality of display driving signals, and the display module can be a panel. In practical applications, the driving circuit outputs the signals through a buffer of an output end to control the display module so as to display images.
It is noted that the conventional display device generates or releases an analog current (AVDD-AGND current) when connected with the external circuit. It is noted that the conventional display device has a plurality of driving channels, and the driving circuit utilizes the buffer of the output end to transmit the display driving signals to the driving channels. Because the display specification of the conventional display device is higher and higher, the amount of the driving channels becomes more and more, resulting in the generation of noise on the output end that affects the driving efficiency. In addition, during the switch of polarity control signals, the analog signal is easy to generate noise to impair the stability of the driving circuit and raise the EMI issue.
For the above reasons, it is desired to design a display driving circuit for decreasing noise and increasing the driving stability.
SUMMARY OF THE INVENTIONIn view of prior art, the present invention provides a driving circuit which has a judgment mechanism and is capable of decreasing noise.
It is an object of the present invention to provide a driving circuit which detects a polarity control signal to determine a driving mechanism.
It is another object of the present invention to provide a driving circuit which adjusts a driving current to prevent an analog current from generating noise.
It is another object of the present invention to provide a driving circuit which controls a driving timing to decrease noise.
The present invention provides a driving circuit which is provided for connecting a display module and includes a polarity control module, an output control module, and a detecting module. In an embodiment, the polarity control module provides a polarity control signal and the output control module is connected with the polarity control module and provides a plurality of output control signals. In addition, the detecting module is coupled with the polarity control module and the output control module. The detecting module detects the polarity control signal and selectively controls the output control module to operate in at least one of a first control mode and a second control mode to control the output control signals.
It is noted that the driving circuit further includes a driving buffer module, wherein the driving buffer module generates and stores a plurality of driving signals according to the polarity control signal and the output control signals, and each driving signal has a rise/fall time and drives the display module. It is noted that the detecting module, in the first control mode, generates an extension control signal to the driving buffer module to extend the rise/fall time.
In addition the detecting module, in the second control mode, generates a time-sharing control signal, and the time-sharing control signal controls the output control signals to be outputted from the output control module by an asynchronous timing.
Compared to prior arts, the driving circuit of the present invention utilizes the detecting module to detect the polarity control signal and control the output control module to operate in at least one of the first control mode and the second control mode according to a variation of the polarity control signal. In practical applications, the detecting module generates the extension control signal or the time-sharing control signal to control a driving status of the driving circuit so as to decrease noise and increase system stability effectively.
The detailed descriptions and the drawings thereof below provide further understanding about the advantage and the spirit of the present invention.
According to an embodiment of the present invention, a driving circuit is provided for decreasing noise. In the embodiment, the driving circuit can be a driving circuit used in a liquid crystal display, but not limited to the embodiment.
Please refer to
In practical applications, the time control module 2 respectively transmits a plurality of control signals to the driving circuit 1 and the gate driving circuit 3, wherein the driving circuit 1 is a source driving circuit, and the driving circuit 1 and the gate driving circuit 3 drive the display module 2 to operate according to the control signals.
Generally, the driving circuit 1 includes a receiver, a data latch module, a signal controller, a shift register module, a level shifter, and a digital/analog converter, wherein these modules process and convert the control signals outputted from the time control module 2 into a plurality of analog data. In addition, the driving circuit 1 transmits the analog data to the display module 4 to control the liquid crystal elements, so that the display module 4 displays images.
As shown in
In the embodiment, the detecting module 30 detects the polarity control signal and selectively controls the output control module 20 to operate in at least one of a first control mode and a second control mode to control the output control signals. In other words, the detecting module 30 can control the output control module 20 to operate in the first control mode, the second control mode, or to operate in the first control mode and the second control mode in the meantime.
Please refer to
In addition, the polarity control signal has a first polarity level 210 and a second polarity level 220, and the detecting module 30 selectively controls the output control module 20 to operate in at least one of the first control mode and the second control mode when the polarity control signal switches between the first polarity level 210 and the second polarity level 220. It is noted that the detecting module 30 controls the output control module 20 to operate in at least one of the first control mode and the second control mode when the polarity control signal switches from the first polarity level 210 to the second polarity level 220 or when the polarity control signal switches from the second polarity level 220 to the first polarity level 210.
With the following descriptions, the present invention utilizes the embodiment of
As shown in
In practical applications, the driving circuit 1 has an analog current, and the analog current is the driving current between an analog power-level (AVDD) and an analog ground-level (AGND). As shown in
In the present invention, the driving circuit 1 adjusts the rise/fall time by controlling the current amplitude of the driving signal, but not limited to the embodiment. For instance, as shown in
In addition, the driving circuit 1 can utilize the detecting module 30 to detect the polarity control signal to control the output control module 20 to operate in the second control module so as to control the output control signals.
In addition, the present invention utilizes the embodiment of
Moreover, the time-sharing control signal 300 has a plurality of time-sharing control timings, and the time-sharing timings are different. As shown in
For instance, the time-sharing buffer unit 230A has a first time-sharing control timing, so that the output control signal 400 is converted into an output control signal 400A having the first time-sharing control timing; the time-sharing buffer unit 230B has a second time-sharing control timing, so that the output control signal 400 is converted into an output control signal 400B having the second time-sharing control timing; the time-sharing buffer unit 230C has a third time-sharing control timing, so that the output control signal 400 is converted into an output control signal 400C having the third time-sharing control timing; the time-sharing buffer unit 230D has a fourth time-sharing control timing, so that the output control signal 400 is converted into an output control signal 400D having the fourth time-sharing control timing.
Please refer to
In the embodiment, the output control signals 400A through 400D divide 1000 output channels into 4 output groups, wherein each output group has different control timing (the first time-sharing control timing through the fourth time-sharing control timing), so that the driving signals in the output channels are not driven in the same timing, the driving signals driven in the same timing are further dispersed so as to decrease noise. In other words, the driving buffer module 40 outputs the driving signals 400A through 400D to the display module 4 according to the time-sharing control signal 300 having the time-sharing control timings, wherein the time-sharing control timing is the asynchronous timing. In practical applications, the detecting module 30 utilizes the time-sharing control signal 300 to control the output control signals 400A through 400D of the output control module 20 to adjust the variation degree of the analog current so as to prevent the analog current from generating the noise. It is noted that the embodiment divides the output channels into 4 output groups with equal amount of channels; however, in other embodiments, the driving circuit 1 divides the output channels into groups having different amount of channels according to practical requirement and is not limited to the embodiment.
In the above embodiment, the driving circuit 1 of the present invention can be driven to operate in the first control module or the second control mode alternatively. It is noted that in other embodiments, the driving circuit 1 of the present invention can be driven to operate in the first control mode and the second control mode simultaneously.
In another embodiment, the driving circuit can simultaneously control the driving buffer module 40 and the output control module 20 to operate simultaneously in the first control mode and the second control mode. Furthermore, the detecting module 30, according to the polarity control signal as well as the variation of the polarity control signal, controls the driving buffer module 40 and the output control module 20 to operate in the first control mode and the second control mode simultaneously. In other words, the detecting module 30 can generate the extension control signal to the driving buffer module 40 and generates the time-sharing control signal to the output control module 20, so that the driving buffer module 40 extends the rise/fall time according to the extension control signal, and the output control module 20, according to the time-sharing control signal, outputs the output control signal 400A through 400D having asynchronous timing to the driving buffer module 40 to disperse the timings of the driving signals. In practical applications, the driving circuit of the present invention simultaneously controls the rise/fall time and the driving timing of the driving signals to prevent the analog current from generating the noise so as to improve the operation efficiency.
In the embodiment, the present invention provides a third control mode which can perform the functions of the first control mode and the second control mode. In other words, the driving circuit can simultaneously control the driving buffer module 40 and the output control module 20 to operate simultaneously in the third control mode. That is, the detecting module 30, according to the polarity control signal as well as the variation of the polarity control signal, controls the driving buffer module 40 and the output control module 20 to operate in the third control mode.
Compared to prior arts, the driving circuit of the present invention utilizes the detecting module to detect the polarity control signal and control the output control module to operate in at least one of the first control mode and the second control mode according to a variation of the polarity control signal. In practical applications, the detecting module generates the extension control signal or the time-sharing control signal to control a driving status of the driving circuit so as to decrease noise and increase system stability effectively.
Although the preferred embodiments of the present invention have been described herein, the above description is merely illustrative. Further modification of the invention herein disclosed will occur to those skilled in the respective arts and all such modifications are deemed to be within the scope of the invention as defined by the appended claims.
Claims
1. A driving circuit for connecting a display module, the driving circuit comprising:
- a polarity control module providing a polarity control signal;
- an output control module connected with the polarity control module and providing a plurality of output control signals; and
- a detecting module coupled with the polarity control module and the output control module, wherein the detecting module detects the polarity control signal and selectively controls the output control module to operate in at least one of a first control mode and a second control mode to control the output control signals.
2. The driving circuit of claim 1, further comprising:
- a driving buffer module coupled with the polarity control module and the output control module, wherein the driving buffer module generates and stores a plurality of driving signals according to the polarity control signal and the output control signals, and each driving signal has a rise/fall time and drives the display module.
3. The driving circuit of claim 2, wherein the driving buffer module is further coupled with the detecting module; in the first control mode, the detecting module generates an extension control signal to the driving buffer module to extend the rise/fall time.
4. The driving circuit of claim 3, wherein the detecting module comprises:
- a variable current unit adjusting a current amplitude of the driving signal according to the extension control signal to extend the rise/fall time.
5. The driving circuit of claim 1, wherein in the second control mode, the detecting module generates a time-sharing control signal and transmits the time-sharing control signal to the output control module, and the time-sharing control signal controls the output control signals to be outputted from the output control module by an asynchronous timing.
6. The driving circuit of claim 1, wherein in the second control mode, the detecting module generates a time-sharing control signal and transmits the time-sharing control signal to the output control module, wherein the time-sharing control signal has a plurality of time-sharing control timings, and the time-sharing timings are different.
7. The driving circuit of claim 6, wherein the output control module comprises:
- a plurality of time-sharing buffer units respectively receiving the time-sharing control signal having the time-sharing control timings and outputting the output control signals to the driving buffer module in the corresponding time-sharing control timings.
8. The driving circuit of claim 7, wherein the driving buffer module outputs the driving signals to the display module according to the time-sharing control signal having the time-sharing control timings.
9. The driving circuit of claim 2, wherein the driving circuit has an analog current, the analog current varies according to the polarity control signal and the output control signals, and the detecting module controls the output control signals or the driving signals to adjust a variation degree of the analog current.
10. The driving circuit of claim 1, wherein the polarity control signal has a first polarity level and a second polarity level, and the detecting module selectively controls the output control module to operate in at least one of the first control mode and the second control mode when the polarity control signal switches between the first polarity level and the second polarity level.
Type: Application
Filed: Oct 11, 2013
Publication Date: Apr 17, 2014
Patent Grant number: 9449570
Applicant: Raydium Semiconductor Corporation (Hsinchu)
Inventors: Chih-Chuan Huang (Kaohsiung), Chien-Ming Chen (Tainan)
Application Number: 14/052,372
International Classification: G09G 3/36 (20060101);