TRENCH TYPE POWER TRANSISTOR DEVICE
The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.
This application is a divisional application of and claims the benefit of U.S. patent application Ser. No. 13/543,877, filed Jul. 8, 2012.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to the field of semiconductor power devices. More particularly, the present invention relates to a trench type power transistor device having super-junction structures and a method thereof.
2. Description of the Prior Art
Power devices are used in power management; for example, in switchable power supplies, management integrated circuits in the core or in the peripheral region of computers, backlight power supplies, and in electric motor controls. The type of power devices described above include an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT) and so forth.
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In order to enhance the voltage sustaining ability of trench type power transistor devices, in some cases, N-type and P-type epitaxial layers are alternately disposed so that several parallel PN junctions are formed on the N-type substrate. Power transistor devices having above-mentioned parallel PN junctions are also called super-junction power transistor devices. However, since an overlapped area between a gate structure and an N-type epitaxial layer (also called drain region) in this power transistor device is relatively high, and the thickness of a gate dielectric layer between the gate structure and the N-type epitaxial layer is relatively thin, these will cause relatively high Miller capacitance and produce inevitable switching losses. As a result, the performance of the devices is lowered.
In light of the above, there is still a need to invent an improved power transistor device which is capable of overcoming the shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTIONIt is therefore one objective of the invention to provide a trench type power transistor device and a method thereof so that a power transistor device with low Miller capacitance and high voltage sustaining ability can be obtained.
To this end, the invention provide a trench type power transistor device including a substrate, an epitaxial layer, a first doped diffusion region, a doped source region, a gate structure, a second doped diffusion region, and a terminal conductive layer. The substrate has a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has at least a first through hole and at least a second through hole respectively penetrating the epitaxial layer, wherein the first through hole is located in the active region, and the second through hole is located in the termination region. The first doped diffusion region is disposed in the epitaxial layer at one side of the first through hole and in direct contact with the substrate, wherein the first doped diffusion region has the first conductivity type. The doped source region is disposed in the epitaxial layer right above the first doped diffusion region, wherein the doped source region has the first conductivity type. The gate structure is disposed in the first through hole between the first doped diffusion region and the doped source region. The second doped diffusion region is disposed on one side of the second through hole in the epitaxial layer and in directly contact with the substrate, wherein the second doped diffusion region has the first conductivity type. And the terminal conductive layer is disposed in the second through hole right above the second doped diffusion region.
According to another aspect, the present invention provides a method for fabricating a trench type power transistor device, which includes the following steps. First, a substrate having a first conductivity type is provided, wherein the substrate has an active region and a termination region. Then, an epitaxial layer is formed on the substrate, wherein the substrate has a second conductivity type different from the first conductivity type. At least a first through hole and at least a second through hole respectively penetrating the epitaxial layer are formed in the epitaxial layer, wherein the first through hole is located in the active region and the second through hole is located in the termination region. After the formation of the through holes, a dopant source layer is filled into the first through hole and the second through hole respectively. A first doped diffusion region is formed at one side of the first through hole in the epitaxial layer and a second doped diffusion region is formed in the epitaxial layer at one side of the second through hole, wherein the first doped diffusion region and the second doped diffusion region have the first conductivity type. Then, a gate structure is formed in the first through hole. Finally, a doped source region is formed at one side of the first through hole in the epitaxial layer which is right above the first doped diffusion region. The doped source region has the first conductivity type and the gate structure is disposed between the first doped diffusion region and the doped source region.
The present invention provides a method for fabricating a trench type power transistor device, which has first doped diffusion layers partially overlapped by the gate conductive layer along a vertical direction. The first doped diffusion layers can be fabricated by first filling a first through hole with electrically insulating dopant source layer and then performing a thermal drive-in process so that conductive dopants inside the dopant source layer can diffuse into an epitaxial layer. As a result, the first doped diffusion layers with the first conductivity type and the epitaxial layer with the second conductivity type are alternately arranged and can construct a super junction structure. In addition, since the dopant source layer having insulating properties is located under the gate conductive layer, a parasitical capacitor between the gate and the drain of the trench type power transistor device can be reduced, and the Miller capacitance and switching losses in the device can be reduced effectively. As a result, the performance of the device is improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
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A chemical mechanical polishing (CMP) process or an etching back process is performed, as shown in
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P-type source doped region 128 is located in the N-type epitaxial layer 104 right above each P-type first doped diffusion region 116 and can serve as a source in the device. Additionally, the gate structure 124 is disposed in the corresponding first through hole 104a between the P-type first doped diffusion region 116 and the corresponding P-type doped source region 128. A channel region (not shown) vertical to the P-type substrate 102 is in the N-type well 106 along the gate dielectric layer 114a, which is between the P-type first doped diffusion region 116 and the corresponding P-type doped source region 128. Therefore, based on the description in the above paragraphs, the power device described in this embodiment belongs to a vertical type power transistor device.
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To summarize, the present invention provides a method for fabricating a power transistor device. The power transistor device has a super junction structure which can be fabricated by first filling a first through hole with an electrically insulating dopant source layer and then performing thermal drive-in processes so that conductive dopants inside the dopant source layer can diffuse into an epitaxial layer. The electrically insulating dopant source layer is located under gate conductive layer and can be regarded as a thick electrical insulation layer. Thanks to the existence of the dopant source layer, Miller capacitance and switching losses which occur in the device can be reduced effectively and, as a result, the performance of the device is improved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A trench type power transistor device, comprising:
- a substrate having a first conductivity type, wherein the substrate has an active region and a termination region;
- an epitaxial layer disposed on the substrate and having a second conductivity type different from the first conductivity type, wherein the substrate has at least a first through hole and at least a second through hole respectively penetrating the epitaxial layer, the first through hole is located in the active region, and the second through hole is located in the termination region;
- a first doped diffusion region disposed in the epitaxial layer at one side of the first through hole and in directly contact with the substrate, wherein the first doped diffusion region has the first conductivity type;
- a doped source region disposed in the epitaxial layer and right above the first doped diffusion region, wherein the doped source region has the first conductivity type;
- a gate structure disposed in the first through hole between the first doped diffusion region and the doped source region;
- a second doped diffusion region disposed on one side of the second through hole in the epitaxial layer and in direct contact with the substrate, wherein the second doped diffusion region has the first conductivity type; and
- a terminal conductive layer disposed in the second through hole right above the second doped diffusion region.
2. The trench type power transistor device according to claim 1, further comprising a first isolation layer disposed in the first through hole below the gate structure, wherein the first isolation layer electrically isolates the first doped diffusion region from the gate structure.
3. The trench type power transistor device according to claim 1, wherein the gate structure comprises a gate conductive layer and a gate dielectric layer, and the gate dielectric layer is disposed between the gate conductive layer and the epitaxial layer.
4. The trench type power transistor device according to claim 1, further comprising a well disposed in the epitaxial layer above the first doped diffusion layer and the second doped diffusion layer, wherein the well has a second conductivity type.
5. The trench type power transistor device according to claim 1, further comprising a second isolation layer located in the second through hole below the terminal conductive layer.
6. The trench type power transistor device according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.
Type: Application
Filed: Jul 14, 2014
Publication Date: Nov 6, 2014
Inventors: Yung-Fa Lin (Hsinchu City), Shou-Yi Hsu (Hsinchu County), Meng-Wei Wu (Hsinchu City), Chia-Hao Chang (Hsinchu City)
Application Number: 14/331,202
International Classification: H01L 29/06 (20060101); H01L 29/739 (20060101);