With Extended Latchup Current Level (e.g., Comfet Device) Patents (Class 257/139)
  • Patent number: 11152466
    Abstract: A semiconductor device includes a semiconductor body; a first electrode on the semiconductor body; control electrodes provided in the semiconductor body along the surface thereof; and first films electrically insulating the control electrodes from the semiconductor body. The semiconductor body includes first, third, sixth layers of a first conductivity type, and second, fourth, fifth layers of a second conductivity type. The second to sixth layers are provided between the first electrode and the first layer. The second and third layers are positioned between two adjacent control electrodes. The fourth to sixth layers are positioned between other two adjacent control electrodes. The sixth layer positioned between the fourth layer and the fifth layer. The sixth layer includes a major portion and a boundary portion between the major portion and one of the first films. An impurity concentration in the boundary portion is lower than that in the major portion.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 19, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11133398
    Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 28, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 11133393
    Abstract: The semiconductor device includes, in plan view, a gate electrode having a first portion located on a side surface portion where a plurality of emitter regions are formed, and a gate electrode having a second portion located between the plurality of emitter regions. The second portion of the gate electrode has a length shorter than first portion in the direction from the main surface to the back surface of the gate electrode of the semiconductor substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobue Maekawa
  • Patent number: 11121242
    Abstract: A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Johannes Laven, Hans-Joachim Schulze
  • Patent number: 11114528
    Abstract: A power transistor having a semiconductor barrier region is presented. A power unit cell of the power transistor has at least two trenches that may both extend into the semiconductor barrier region. The semiconductor barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The semiconductor barrier region can be electrically floating. Further, the at least two trenches may both increase in width along their respective extension into the semiconductor body.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 7, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Matteo Dainese, Markus Beninger-Bina, Alexander Philippou
  • Patent number: 11107740
    Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 31, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Jürgen Schuderer, Umamaheswara Vemulapati, Marco Bellini, Jan Vobecky
  • Patent number: 11094810
    Abstract: There is provided a semiconductor device comprising: a semiconductor substrate; an emitter region of a first conductivity type provided inside the semiconductor substrate; a base region of a second conductivity type provided below the emitter region inside the semiconductor substrate; an accumulation region of the first conductivity type provided below the base region inside the semiconductor substrate, and containing hydrogen as an impurity; and a trench portion provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 17, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11094691
    Abstract: A semiconductor device includes a semiconductor substrate, and the semiconductor substrate is divided into an IGBT region, a diode region, and a MOSFET region. A drift layer of n?-type is provided in the semiconductor substrate. The drift layer is shared among the IGBT region, the diode region, and the MOSFET region. In the semiconductor substrate, the diode region is always disposed between the IGBT region and the MOSFET region to cause the IGBT region and the MOSFET region to be separated from each other without being adjacent to each other.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: August 17, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Shinya Soneda
  • Patent number: 11081544
    Abstract: A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 ?m to 60 ?m. The semiconductor body is annealed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Oana Julia Spulber, Stephan Voss
  • Patent number: 11081576
    Abstract: A method of manufacturing an insulated-gate semiconductor device, includes: digging a gate trench and a dummy trench; burying a dummy electrode in the dummy trench via a gate insulating film and burying a gate electrode in the gate trench via the gate insulating film; exposing an upper portion of the dummy electrode and selectively forming an insulating film for testing so as to cover the gate electrode; depositing a conductive film for testing on the dummy electrode and the insulating film for testing; and selectively testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the conductive film for testing and the charge transport, region.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 3, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takamasa Ishikawa, Seiji Noguchi
  • Patent number: 11081575
    Abstract: An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 3, 2021
    Assignee: ZHONG SHAN HONSON ELECTRONIC TECHNOLOGIES LIMITED
    Inventors: Johnny Kin On Sin, Hao Feng, Song Yuan
  • Patent number: 11075291
    Abstract: According to an embodiment of a semiconductor device, the device includes a semiconductor substrate having a transistor region and a diode region. The transistor region includes a plurality of IGBT cells, and a charge carrier compensation region configured to expel or admit drift zone minority charge carriers based on an on-state or an off-state of the IGBT cells. The diode region includes a plurality of diode cells. An isolation structure is provided between the transistor region and the diode region. The isolation structure includes a first trench extending lengthwise along at least part of a periphery of the diode region and a second trench interposed between the first trench and the transistor region. The charge carrier compensation region extends to the second trench of the isolation structure but not the first trench such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: July 27, 2021
    Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.
    Inventors: Matteo Dainese, Canhua Li, Andreas Moser, Wolfgang Wagner
  • Patent number: 11069770
    Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 20, 2021
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Patent number: 11063143
    Abstract: A method of manufacturing an insulated-gate semiconductor device includes: digging a dummy trench and digging a gate trench so as to have a U-like shape in a planar pattern to surround the dummy trench into the U-like shape; forming a dummy electrode and a gate electrode in the dummy trench and the gate trench via a gate insulating film; forming a projection for testing connected to the dummy electrode via an opening of the U-like shape and a wiring layer for testing; and testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the wiring layer for testing and a charge transport region.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 13, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takamasa Ishikawa, Noriaki Yao, Seiji Noguchi
  • Patent number: 11054088
    Abstract: This disclosure discloses a light-emitting bulb. The light-emitting bulb includes a cover, an electrical associated with the cover, a board arranged between the cover and the electrical connector, and a first light-emitting device disposed on the board. The first light-emitting device includes a carrier having a first side and a second side, a first electrode part disposed near the first side and extending to the second side, a bended part disposed near to the second side and spaced apart from the first electrode part, and a second electrode part extending from the bended part to the first side. No light-emitting diode unit is arranged on the second electrode part.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 6, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chiu-Lin Yao, Min-Hsun Hsieh, Been-Yu Liaw, Wei-Chiang Hu, Po-Hung Lai, Chun-Hung Liu, Shih-An Liao, Yu-His Sung, Ming-Chi Hsu
  • Patent number: 11049941
    Abstract: A semiconductor device is provided comprising: a semiconductor substrate; a drift region having a first conductivity type formed in the semiconductor substrate; a collector region having a second conductivity type, in the semiconductor substrate, formed between the lower surface of the semiconductor substrate and the drift region; and a high concentration region having a first conductivity type, in the semiconductor substrate, formed between the drift region and the collector region and having higher doping concentration than that in the drift region, wherein a doping concentration distribution of the high concentration region in the depth direction of the semiconductor substrate comprises one or more peaks, wherein a distance between a first peak closest to the lower surface side of the semiconductor substrate among the peaks of the doping concentration distribution of the high concentration region and the lower surface of the semiconductor substrate is 3 ?m or less.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 29, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kota Ohi, Yuichi Onozawa, Yoshihiro Ikura
  • Patent number: 11038020
    Abstract: A silicon carbide semiconductor device includes a semiconductor substrate and a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a gate electrode provided opposing at least a surface of the second semiconductor layer between the first semiconductor region and the first semiconductor layer, across a gate insulating film; and a first electrode provided on surfaces of the first semiconductor region and the second semiconductor layer. Protons are implanted in a first region of the semiconductor substrate, spanning at least 2 ?m from a surface of the semiconductor substrate facing toward the first semiconductor layer; and in a second region of the first semiconductor layer, spanning at least 3 ?m from a surface of the first semiconductor layer facing toward the semiconductor substrate. The protons having a concentration in a range from 1×1013/cm3 to 1×1015/cm3.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 15, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takumi Fujimoto
  • Patent number: 11037863
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 15, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidetoshi Kuraya, Satoshi Hattori, Kyo Tanabiki
  • Patent number: 11031465
    Abstract: A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile formed in the field stop zone includes varying, non-constant doping levels. In some embodiments, the enhanced doping profile includes one of an extended graded doping profile, a multiple stepped flat doping profile, or a multiple spike doping profile. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Lei Zhang, Karthik Padmanabhan, Lingpeng Guan, Jian Wang, Lingbing Chen, Wim Aarts, Hongyong Xue, Wenjun Li, Madhur Bobde
  • Patent number: 11029216
    Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 8, 2021
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Frederick A. Ware
  • Patent number: 10998403
    Abstract: A power device includes a gate, and a segmented source adjacent to the gate, wherein the segmented source includes segments having a first threshold voltage and includes segments having a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 4, 2021
    Assignee: INFINEON TECHNOLOGIES AMERICAS CORP.
    Inventor: Praveen Shenoy
  • Patent number: 10996260
    Abstract: A semiconductor test circuit, apparatus, and method having a first relay disposed between a power supply and a switching element, a second relay disposed between a connection point of the switching element and a reverse conducting-insulated gate bipolar transistor (RC-IGBT) chip and a snubber circuit, a third relay disposed between the switching element and the RC-IGBT chip and a coil, and a fourth relay disposed between a diode and the switching element. A turn on/off test of an IGBT portion is performed by turning on the second and fourth relays. An avalanche test of the IGBT portion is performed by turning on the second relay. A short-circuit test of the IGBT portion is performed by turning on the first relay. A recovery test of an FWD portion is performed by turning on the first and third relays. At this time probes are brought into contact with electrodes once.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 4, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuru Yoshida
  • Patent number: 10985546
    Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Excelitas Technologies Corp.
    Inventors: John E. Waldron, Kenneth Brandmier, James K. Azotea
  • Patent number: 10950446
    Abstract: Provided is a semiconductor device including: a semiconductor substrate doped with an impurity; a front-surface-side electrode provided at a side of a front surface of the semiconductor substrate; and a back-surface-side electrode provided at a side of a back surface of the semiconductor substrate; wherein the semiconductor substrate includes: a peak region arranged at the side of the back surface of the semiconductor substrate and having one or more peaks of an impurity concentration; a high concentration region arranged closer to the front surface than the peak region and having an impurity concentration more gently sloped than the one or more peaks; and a low concentration region arranged closer to the front surface than the high concentration region and having an impurity concentration lower than the impurity concentration of the high concentration region and a substrate concentration of the semiconductor substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Takahiro Tamura, Yuichi Onozawa, Akio Yamano
  • Patent number: 10923561
    Abstract: A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: February 16, 2021
    Assignee: DENSO CORPORATION
    Inventor: Motoo Yamaguchi
  • Patent number: 10910487
    Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
  • Patent number: 10903354
    Abstract: A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a <010> direction, a second region extending in a <001> direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the <010> direction in the first region and a second opening extending in the <001> direction in the second region, and the first opening and the second opening are divided from each other in the third region.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: January 26, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshito Nakazawa
  • Patent number: 10892352
    Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: January 12, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko Furukawa, Shoichi Orita, Hiroki Muraoka, Atsushi Narazaki, Tsuyoshi Kawakami, Yuji Murakami
  • Patent number: 10886390
    Abstract: In a method of manufacturing a semiconductor device, a gate insulating film is formed at a first surface of a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type is formed at the first surface; a gate electrode is formed on the gate insulating film; the gate insulating film is selectively removed; a thermal oxide film is formed at a surface of the second semiconductor layer; a third semiconductor layer of the first conductivity type is selectively formed at the surface of the second semiconductor layer; an interlayer insulating film is formed on the thermal oxide film; a contact hole is selectively formed to expose the third semiconductor layer; a barrier metal is formed in the contact hole; and a metal plug is embedded in the contact hole on barrier metal by a CVD method that uses a metal halide.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Makoto Shimosawa
  • Patent number: 10886377
    Abstract: The power semiconductor device includes: a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate; a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate; a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate; a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate; and a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 5, 2021
    Assignee: HYUNDAI AUTRON CO., LTD.
    Inventors: Ju Hwan Lee, Tae Young Park, Hyuk Woo, Min Gi Kang, Young Joon Kim, Tae Youp Kim, Seong-hwan Yun, Seon-hyeong Jo, Jeong Mok Ha
  • Patent number: 10868170
    Abstract: A power semiconductor die conducts a load current between front and back side load terminals. The die includes an active region with a plurality of columnar trench cells. Each columnar trench cell includes: a section of a drift zone, a section of a channel zone and a section of a source zone, the channel zone section being electrically connected to the front side load terminal and isolating the source zone section from the drift zone section; and a control section with at least one control electrode in a control trench. An edge termination region between the die edge and the active region includes a front side zone configured to have an electrical potential different from an electrical potential of the front side load terminal. An isolating trench structure is arranged between the front side zone and the channel zone which is electrically connected to the front side load terminal.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Christof Altstaetter
  • Patent number: 10861955
    Abstract: Method for fabricating an insulated gate bipolar transistor (IGBT) is provided. A substrate includes a device region, that includes control regions and turn-off regions, arranged alternately. A drift region is formed in the substrate. A well region is formed in a portion of the substrate in the control regions and the turn-off regions, and first gate structures are formed in the control regions. The well region is in contact with the drift region, and the first gate structures are in contact with both the drift region and the well region. Emission regions are formed in the well region of the control regions and in the substrate on one or both sides of each first gate structure, the drift region and each emission region are separated by the well region, and the emission regions are electrically connected to a portion of the well region in the turn-off region.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 8, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Lei Bing Yuan
  • Patent number: 10847608
    Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Patent number: 10847641
    Abstract: Among trenches disposed in a striped-shape parallel to a front surface of a semiconductor substrate, a gate electrode at a gate potential is provided in a gate trench, via a gate insulating film; and in a dummy trench, a dummy gate electrode at an emitter electric potential is provided, via a dummy gate insulating film. Among mesa regions, in a first mesa region functioning as a MOS gate, a first p-type base region is provided in a surface region overall. In a second mesa region not functioning as a MOS gate, a second p-type base region is selectively provided at a predetermined interval, along a first direction. At least one of the trenches on each side of a mesa region is a gate trench and at at least one side wall of the gate trench, a MOS gate is driven. As a result, the ON voltage may be reduced.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hitoshi Abe, Takeshi Fujii, Tomoyuki Obata
  • Patent number: 10818783
    Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hitoshi Matsuura
  • Patent number: 10811524
    Abstract: A semiconductor circuit of an embodiment includes semiconductor device and a control circuit. The semiconductor device includes a semiconductor layer that has a first region of a first-conductivity type, a second region of a second-conductivity type, a third region of the first-conductivity type, fourth region of the second-conductivity type, first and second trench, first and second gate electrode, a first gate insulating film in contact with the fourth region, and a second gate insulating film spaced away from the fourth region. The semiconductor device includes a first gate electrode pad connected to the first gate electrode, and a second gate electrode pad connected to the second gate electrode. Prior to changing a first gate voltage from a turn-ON voltage to a turn-OFF voltage, a second gate voltage changed from a first voltage to a second voltage. The second voltage is a negative voltage when the first-conductivity type is p-type.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Takeshi Suwa
  • Patent number: 10784339
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: transistor cells formed along a first surface at a front side of a semiconductor portion; a drain structure between the transistor cells and a second surface of the semiconductor portion opposite to the first surface, the drain structure forming first pn junctions with body regions of the transistor cells and including an emitter layer directly adjoining the second surface; and a metal drain electrode directly adjoining the emitter layer. An integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a charge type of the body regions is at most 1.5E13 cm?2. Further semiconductor device embodiments are described.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 22, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Enrique Vecino Vazquez, Daniel Pobig, Franz Hirler, Manfred Pippan, Patrick Schindler
  • Patent number: 10777677
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10777455
    Abstract: A method for forming a semiconductor device structure is provided. A gate structure and a source/drain contact structure are formed over a substrate. The gate structure is covered with a capping layer. The capping layer and the source/drain contact structure are successively covered with a first insulating layer and a second insulating layer. A via opening is formed in the second insulating layer to expose the first insulating layer above the source/drain contact structure. The exposed first insulating layer is recessed using a first etching gas mixture including an oxygen gas, to leave a portion of the first insulating layer. The left portion of the first insulating layer using a second etching gas mixture including a hydrogen gas, to expose the source/drain contact structure. A conductive material is formed in the via opening to electrically connect the source/drain contact structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jui Huang, Li-Te Lin, Pinyen Lin
  • Patent number: 10777678
    Abstract: A semiconductor device includes: an active area including a drift layer of a first conductivity type; and a voltage blocking area arranged around the active area and including an field relaxation region having a second conductivity type, being provided in an upper portion of the drift layer, wherein a depth of the field relaxation region decreases toward outside, and a spatial-modulation portion is provided at an outer end of the field relaxation region.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10777548
    Abstract: A method of manufacturing a semiconductor device includes forming a first trench and a second trench on a surface of a semiconductor substrate, the second trench being narrower than the first trench; forming an emitter connecting part and a trench gate that are separated from each other in the first trench and forming an embedded electrode in the second trench; forming a center insulating film in the first trench between the emitter connecting part and the trench gate; forming an interlayer insulating layer on the semiconductor substrate; forming a contact hole in the interlayer film at a location corresponding to the second trench; and forming an electrode material on the insulating layer so as to connect the electrode material and the embedded electrode in the second trench via the contact hole.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 15, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10770456
    Abstract: A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a transistor region, and the transistor region includes a drift region, a plurality of trench portions, a plurality of emitter regions and a plurality of contact regions, and an accumulation region provided between the drift region and the plurality of emitter regions in a depth direction, and having a higher first-conductivity-type doping concentration than the drift region. A first outermost contact region is an outermost one of the plurality of contact regions in a direction parallel to the first direction, and a length of the first outermost contact region in the first direction is longer than a length in the first direction of one contact region of the plurality of contact regions other than the first outermost contact region, and the accumulation region terminates at a position below the first outermost contact region.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Soichi Yoshida, Hiroshi Miyata
  • Patent number: 10770404
    Abstract: In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn Horng, Chung-Peng Hsieh
  • Patent number: 10763346
    Abstract: Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: September 1, 2020
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tomoyasu Furukawa, Masaki Shiraishi, Toshiaki Morita
  • Patent number: 10748822
    Abstract: A method for manufacturing a semiconductor device having a trench gate structure is provided. In the method, a first voltage-current characteristic indicating a relation between the main current and the gate voltage under a first temperature is measured to calculate a first threshold voltage. A second voltage-current characteristic indicating a relation between the main current and the gate voltage under a second temperature different from the first temperature is measured to calculate a second threshold voltage. It is determined whether the semiconductor device is a non-defective product or a defective product based on whether a difference between the second threshold voltage and the first threshold voltage is larger than a determination threshold value.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 18, 2020
    Assignee: DENSO CORPORATION
    Inventors: Takaaki Aoki, Masakazu Itoh
  • Patent number: 10734507
    Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region. Related methods of manufacture are also described.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze
  • Patent number: 10705123
    Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhisa Nagao
  • Patent number: 10700184
    Abstract: According to one embodiment, a semiconductor device a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, a gate electrode, a ninth semiconductor region, and a second electrode. The first, second, and fourth semiconductor regions are provided on the first electrode. The third semiconductor region is provided between the first and second semiconductor regions. The fifth semiconductor region is provided on the first, second, third, and fourth semiconductor regions. The sixth and seventh semiconductor regions are provided on the fifth semiconductor region. The eighth semiconductor region is provided on a portion of the seventh semiconductor region. The ninth semiconductor region is provided around the sixth semiconductor region and the seventh semiconductor region.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 30, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
  • Patent number: 10700059
    Abstract: In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 30, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10692995
    Abstract: The present invention provides an insulated-gate bipolar transistor (IGBT) structure and a method for manufacturing the same. The structure is a planar IGBT structure, and is characterized by an ultra-thin channel and buried oxide located below the channel. The structure can provide the theoretically lowest on-state voltage drop.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 23, 2020
    Inventor: Ka Kit Wong