With Extended Latchup Current Level (e.g., Comfet Device) Patents (Class 257/139)
  • Patent number: 11545564
    Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 3, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Koichi Nishi, Katsumi Nakamura, Ze Chen, Koji Tanaka
  • Patent number: 11538929
    Abstract: A semiconductor device includes first and third semiconductor layers of a first conductivity type, and second, fourth and fifth semiconductor layers of a second conductivity type. The first semiconductor layer is provided on the fifth semiconductor layer. The second semiconductor layer is provided on the first semiconductor layer. The third and fourth semiconductor layers are arranged along the second semiconductor layer. In a plane parallel to an upper surface of the second semiconductor layer, the fourth semiconductor layer has a surface area greater than a surface area of the third semiconductor layer. The device further includes first to third electrodes, and first control electrode. The first to third electrodes are electrically connected to the third to fifth semiconductor layers, respectively. The first control electrode is provided in a first trench extending into the first semiconductor layer from an upper surface of the third semiconductor layer.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: December 27, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takeshi Suwa, Tomoko Matsudai, Yoko Iwakaji, Hiroko Itokazu, Takako Motai
  • Patent number: 11502191
    Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Johann Christian Rode, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid M. Hafez
  • Patent number: 11444157
    Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 13, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Koichi Nishi, Katsumi Nakamura
  • Patent number: 11398563
    Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 26, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 11393907
    Abstract: A semiconductor device includes: a semiconductor substrate; trenches formed in the substrate and extending lengthwise in parallel with one another, the trenches having connecting regions which interconnect adjacent ones of the trenches; semiconductor mesas separated from one another by the trenches in a first lateral direction and by the connecting regions in a second lateral direction transverse to the first lateral direction; a gate electrode and a field electrode below the gate electrode in at least some of the trenches, and dielectrically insulated from each other and from the semiconductor substrate; first contacts vertically extending into one or more transistor device regions in the semiconductor mesas; and second contacts vertically extending into the field electrodes in the connecting regions such that the gate electrodes are uninterrupted by the second contacts. Corresponding methods of producing such a semiconductor device are also described.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Robert Paul Haase
  • Patent number: 11387323
    Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 12, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Chin-yu Tsai, Guruvayurappan Mathur
  • Patent number: 11387359
    Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Oliver Humbel, Josef-Georg Bauer, Jens Brandenburg, Diana Car, Philipp Sebastian Koch, Angelika Koprowski, Sebastian Kremp, Thomas Kurzmann, Erwin Lercher, Holger Ruething
  • Patent number: 11374122
    Abstract: A semiconductor device of an embodiment includes an element region and a termination region surrounding the element region. The element region includes a gate trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type on the first silicon carbide region, a third silicon carbide region of n-type on the second silicon carbide region, and a fourth silicon carbide region of p-type sandwiches the first silicon carbide region and the second silicon carbide region with the gate trench, the fourth silicon carbide region being deeper than the gate trench. The termination region includes a first trench surrounding the element region, and a fifth silicon carbide region of p-type between the first trench and the first silicon carbide region, the fifth silicon carbide region same or shallower than the fourth silicon carbide region. The semiconductor device includes a gate electrode, a first electrode, and a second electrode.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: June 28, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhisa Tanaka, Ryosuke Iijima
  • Patent number: 11355595
    Abstract: Directly beneath p?-type base regions, n-type storage regions are provided. The storage regions contain hydrogen donors as an impurity and have an impurity concentration higher than that of the n?-type drift region. The storage regions are formed by hydrogen ion irradiation from a back surface of a semiconductor substrate. The storage regions have a peak hydrogen concentration and are at positions that coincide with where the hydrogen ions have been irradiated. By the hydrogen ion irradiation, a crystal defect region that is a carrier lifetime killer region is formed concurrently with the storage regions, closer to the back surface of the semiconductor substrate than are storage regions. The crystal defect region has a crystal defect density with a peak density at a position closer to the back surface of the semiconductor substrate than are the storage regions. A semiconductor device having such storage regions and a carrier lifetime killer region is enabled.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: June 7, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motoyoshi Kubouchi
  • Patent number: 11349019
    Abstract: A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, and a lower gradient portion in which the concentration decreases from the maximum portion to a drift region. When a full width at half maximum determined by setting a depth position of the maximum portion as a range of impurity implantation with reference to a range-full width at half maximum characteristic according to a material of the substrate and a type of impurities contained in the accumulation region is set as a standard full width at half maximum, a full width at half maximum of the distribution in the accumulation region is 2.2 times the standard full width at half maximum or greater.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: May 31, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11342186
    Abstract: A semiconductor device wherein a hydrogen concentration distribution has a first hydrogen concentration peak and a second hydrogen concentration peak and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak in a depth direction, wherein the first hydrogen concentration peak and the first donor concentration peak are placed at a first depth and the second hydrogen concentration peak and the second donor concentration peak are placed at a second depth deeper than the first depth relative to the lower surface is provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 24, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasunori Agata, Takashi Yoshimura, Hiroshi Takishita, Misaki Meguro, Naoko Kodama, Yoshihiro Ikura, Seiji Noguchi, Yuichi Harada, Yosuke Sakurai
  • Patent number: 11342247
    Abstract: A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 24, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chia-Yu Chang, Chih-Chien Ho, Steven Su
  • Patent number: 11342281
    Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 24, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Yabuta, Takayuki Yamada, Yuya Muramatsu, Noriyuki Besshi, Yutaro Sugi, Hiroaki Haruna, Masaru Fuku, Atsuki Fujita
  • Patent number: 11335771
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween; first and second control electrodes each in a trench at the frontside of the semiconductor part. The semiconductor part includes first to sixth layers. The first and third layers are of a first conductivity type. Other layers are of a second conductivity type. The first layer extends between the first electrode at the backside and the second electrode at the frontside. The second layer is provided between the first layer and the second electrode. The third and fourth layers each are selectively provided between the second layer and the second electrode. The fifth layer is provided between the first layer and the first electrode. The sixth layer is provided between the first layer and the second control electrode. The sixth layer extends along an insulating film between the semiconductor part and the second control electrode.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 17, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoko Iwakaji, Tomoko Matsudai
  • Patent number: 11329150
    Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: May 10, 2022
    Assignee: NXP USA, Inc.
    Inventors: Tanuj Saxena, Vishnu Khemka, Bernhard Grote, Ganming Qin, Moaniss Zitouni
  • Patent number: 11322587
    Abstract: A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.
    Type: Grant
    Filed: June 13, 2020
    Date of Patent: May 3, 2022
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Hans-Juergen Thees, Stefan Loesch, Marc Probst, Tom Richter, Olaf Storbeck
  • Patent number: 11322586
    Abstract: A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 3, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shunsuke Sakamoto
  • Patent number: 11309883
    Abstract: A semiconductor module, including a semiconductor chip that includes a switching device having a control electrode, and a control terminal connected to the control electrode, a first resistance being formed between the control electrode and the control terminal and having a positive temperature coefficient, and a second resistance connected to the control terminal, the second resistance having a negative temperature coefficient. A temperature coefficient of a combined resistance at the control terminal is zero or negative.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 19, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Susumu Iwamoto
  • Patent number: 11309415
    Abstract: A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 19, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Shunichi Nakamura
  • Patent number: 11309310
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer po
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 19, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Kohei Shinsho
  • Patent number: 11309411
    Abstract: The present invention relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor that has multiple mesas having different widths, configured to promote the buildup and accumulation of hole carriers, thereby facilitating relatively easy subsequent processing, while maximizing conductivity modulation.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 19, 2022
    Assignee: DB HiTek Co., Ltd.
    Inventor: Young-Seok Kim
  • Patent number: 11296212
    Abstract: A current switching semiconductor device to be used in a power conversion device achieves both a low conduction loss and a low switching loss. The semiconductor device includes the IGBT in which only Gc gates are provided and an impurity concentration of the p type collector layer is high, and the IGBT in which the Gs gates and the Gc gates are provided and an impurity concentration of the p type collector layer is low. When the semiconductor device is turned off, the semiconductor device transitions from a state in which a voltage lower than a threshold voltage is applied to both the Gs gates and the Gc gates to a state in which a voltage equal to or higher than the threshold voltage is applied to the Gc gates prior to the Gs gates.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 5, 2022
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tomoyuki Miyoshi, Mutsuhiro Mori, Tomoyasu Furukawa, Yujiro Takeuchi, Masaki Shiraishi
  • Patent number: 11296213
    Abstract: According to an embodiment of a power semiconductor device, the device includes: a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional power semiconductor device embodiments are described herein, as are corresponding methods of production.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Philipp Sandow, Wolfgang Roesner, Matteo Dainese
  • Patent number: 11245010
    Abstract: A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kosuke Yoshida, Haruo Nakazawa, Kenichi Iguchi, Koh Yoshikawa, Motoyoshi Kubouchi
  • Patent number: 11233158
    Abstract: A device includes a first doped semiconductor region and a second oppositely doped semiconductor region that are separated by an undoped or lightly-doped semiconductor drift region. The device further includes a first electrode structure making an ohmic contact with the first doped semiconductor region, and a second electrode structure making a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows flow of both electrons and holes into, and out of, the device.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 25, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Mingjiao Liu
  • Patent number: 11222858
    Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: January 11, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Xiaotian Zhang, Zhiqiang Niu
  • Patent number: 11217449
    Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomohide Terashima, Yasuhiro Kagawa, Kensuke Taguchi
  • Patent number: 11189688
    Abstract: An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 30, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Luca De-Michielis, Munaf Rahimo, Chiara Corvasce
  • Patent number: 11189709
    Abstract: A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: November 30, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 11189698
    Abstract: Disclosed is a semiconductor power device, including a semiconductor substrate; a MOSFET region formed on the semiconductor substrate, where the MOSFET region includes at least one MOSFET unit; and at least one collector region located in the semiconductor substrate, where the collector region and the MOSFET unit form an insulated gate bipolar transistor.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 30, 2021
    Assignee: SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD
    Inventors: Yuanlin Yuan, Wei Liu, Zhendong Mao, Lei Liu, Rui Wang, Yi Gong
  • Patent number: 11183589
    Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 11183386
    Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 23, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomohide Terashima, Yasuhiro Kagawa, Kensuke Taguchi
  • Patent number: 11183601
    Abstract: A semiconductor device includes a semiconductor substrate including a drift region of a first conductivity type, a transistor portion provided in the substrate, and an adjacent element portion provided in the substrate, the adjacent element and transistor portions being arranged along an arrangement direction. The transistor and adjacent element portions both include a base region of a second conductivity type provided above the drift region, trench portions formed through the base region, extending in an extending direction orthogonal to the arrangement direction on the upper surface, and having a conducting portion therein, and a first lower surface side lifetime control region provided, on a lower surface side, continuously from the transistor portion to the adjacent element portion and includes a lifetime killer. The lifetime control region is provided over entirety of the transistor portion and in a part of the adjacent element portion in a top view of the substrate.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11171226
    Abstract: IGBT semiconductor structure having a p+ substrate, an n? layer, at least one p region adjacent to the n? layer, and at least one n+ region adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the n? layer, and the n+ region forms a second p-n junction together with the at least one p region. The dielectric layer covers the first p-n junction and the second p-n junction. The second terminal contact is implemented as a field plate on the dielectric layer and a doped intermediate layer with a layer thickness of 1 ?m-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the p+ substrate and the n? layer, wherein the intermediate layer is integrally joined to at least the p+ substrate.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 9, 2021
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 11152466
    Abstract: A semiconductor device includes a semiconductor body; a first electrode on the semiconductor body; control electrodes provided in the semiconductor body along the surface thereof; and first films electrically insulating the control electrodes from the semiconductor body. The semiconductor body includes first, third, sixth layers of a first conductivity type, and second, fourth, fifth layers of a second conductivity type. The second to sixth layers are provided between the first electrode and the first layer. The second and third layers are positioned between two adjacent control electrodes. The fourth to sixth layers are positioned between other two adjacent control electrodes. The sixth layer positioned between the fourth layer and the fifth layer. The sixth layer includes a major portion and a boundary portion between the major portion and one of the first films. An impurity concentration in the boundary portion is lower than that in the major portion.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 19, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11133398
    Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 28, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 11133393
    Abstract: The semiconductor device includes, in plan view, a gate electrode having a first portion located on a side surface portion where a plurality of emitter regions are formed, and a gate electrode having a second portion located between the plurality of emitter regions. The second portion of the gate electrode has a length shorter than first portion in the direction from the main surface to the back surface of the gate electrode of the semiconductor substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobue Maekawa
  • Patent number: 11121242
    Abstract: A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Johannes Laven, Hans-Joachim Schulze
  • Patent number: 11114528
    Abstract: A power transistor having a semiconductor barrier region is presented. A power unit cell of the power transistor has at least two trenches that may both extend into the semiconductor barrier region. The semiconductor barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The semiconductor barrier region can be electrically floating. Further, the at least two trenches may both increase in width along their respective extension into the semiconductor body.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 7, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Matteo Dainese, Markus Beninger-Bina, Alexander Philippou
  • Patent number: 11107740
    Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 31, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Jürgen Schuderer, Umamaheswara Vemulapati, Marco Bellini, Jan Vobecky
  • Patent number: 11094691
    Abstract: A semiconductor device includes a semiconductor substrate, and the semiconductor substrate is divided into an IGBT region, a diode region, and a MOSFET region. A drift layer of n?-type is provided in the semiconductor substrate. The drift layer is shared among the IGBT region, the diode region, and the MOSFET region. In the semiconductor substrate, the diode region is always disposed between the IGBT region and the MOSFET region to cause the IGBT region and the MOSFET region to be separated from each other without being adjacent to each other.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: August 17, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Shinya Soneda
  • Patent number: 11094810
    Abstract: There is provided a semiconductor device comprising: a semiconductor substrate; an emitter region of a first conductivity type provided inside the semiconductor substrate; a base region of a second conductivity type provided below the emitter region inside the semiconductor substrate; an accumulation region of the first conductivity type provided below the base region inside the semiconductor substrate, and containing hydrogen as an impurity; and a trench portion provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 17, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11081576
    Abstract: A method of manufacturing an insulated-gate semiconductor device, includes: digging a gate trench and a dummy trench; burying a dummy electrode in the dummy trench via a gate insulating film and burying a gate electrode in the gate trench via the gate insulating film; exposing an upper portion of the dummy electrode and selectively forming an insulating film for testing so as to cover the gate electrode; depositing a conductive film for testing on the dummy electrode and the insulating film for testing; and selectively testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the conductive film for testing and the charge transport, region.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 3, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takamasa Ishikawa, Seiji Noguchi
  • Patent number: 11081575
    Abstract: An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 3, 2021
    Assignee: ZHONG SHAN HONSON ELECTRONIC TECHNOLOGIES LIMITED
    Inventors: Johnny Kin On Sin, Hao Feng, Song Yuan
  • Patent number: 11081544
    Abstract: A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 ?m to 60 ?m. The semiconductor body is annealed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Oana Julia Spulber, Stephan Voss
  • Patent number: 11075291
    Abstract: According to an embodiment of a semiconductor device, the device includes a semiconductor substrate having a transistor region and a diode region. The transistor region includes a plurality of IGBT cells, and a charge carrier compensation region configured to expel or admit drift zone minority charge carriers based on an on-state or an off-state of the IGBT cells. The diode region includes a plurality of diode cells. An isolation structure is provided between the transistor region and the diode region. The isolation structure includes a first trench extending lengthwise along at least part of a periphery of the diode region and a second trench interposed between the first trench and the transistor region. The charge carrier compensation region extends to the second trench of the isolation structure but not the first trench such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: July 27, 2021
    Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.
    Inventors: Matteo Dainese, Canhua Li, Andreas Moser, Wolfgang Wagner
  • Patent number: 11069770
    Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 20, 2021
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Patent number: 11063143
    Abstract: A method of manufacturing an insulated-gate semiconductor device includes: digging a dummy trench and digging a gate trench so as to have a U-like shape in a planar pattern to surround the dummy trench into the U-like shape; forming a dummy electrode and a gate electrode in the dummy trench and the gate trench via a gate insulating film; forming a projection for testing connected to the dummy electrode via an opening of the U-like shape and a wiring layer for testing; and testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the wiring layer for testing and a charge transport region.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 13, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takamasa Ishikawa, Noriaki Yao, Seiji Noguchi
  • Patent number: 11054088
    Abstract: This disclosure discloses a light-emitting bulb. The light-emitting bulb includes a cover, an electrical associated with the cover, a board arranged between the cover and the electrical connector, and a first light-emitting device disposed on the board. The first light-emitting device includes a carrier having a first side and a second side, a first electrode part disposed near the first side and extending to the second side, a bended part disposed near to the second side and spaced apart from the first electrode part, and a second electrode part extending from the bended part to the first side. No light-emitting diode unit is arranged on the second electrode part.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 6, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chiu-Lin Yao, Min-Hsun Hsieh, Been-Yu Liaw, Wei-Chiang Hu, Po-Hung Lai, Chun-Hung Liu, Shih-An Liao, Yu-His Sung, Ming-Chi Hsu