Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same
A structure of trench VDMOS transistor comprises an n− epi-layer/n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer is formed on the inter-metal dielectric layer and through the source contact plugs connecting the source regions and the first poly-Si layer. The drain electrode is formed on the rear surface of the n+ substrate for both embodiments.
The present invention pertains to a semiconductor device, in particularly, to a structure of a trench-vertical doubled diffused MOS transistors and a method of making the same.
DESCRIPTION OF THE PRIOR ARTAmong those of transistors with capability of withstand high reverse bias voltage, the double-diffused metal oxide semiconductor transistor DMOS may be one of the most preferred, In the DMOS devices, the vertical double diffused metal oxide semiconductor (VDMOS) transistor attracts further attention than the lateral double-diffused metal oxide semiconductor (LDMOS). The LDMOS structure is a planar device whereas the VDMS is a trench structure and the VDMS is thus with advantages of low cost and low open resistance (low on-resistance; RON). Parts of reasons for that may be due to the latter component has a higher integrated density and uses a whole rear surface side of the semiconductor substrate as its drain electrode. The trench MOS is one of VDMOS and with a higher integrated density than the average of VDMOS.
An object of the present invention is to disclose a trench vertical doubled diffused MOS transistor (VDMOS transistor).
According to a first preferred embodiment, the VDMOS transistor comprises an n− epi-layer on a n+ semiconductor substrate having a plurality of trenches in parallel formed therein and the trenches are spaced each other by a mesa; each of the trenches has a trench oxide layer formed on a bottom and sidewalls and a first conductive poly-Si layer filled in the trench; a plurality of planar gates having a second poly-Si layer on a planar gate oxide layer are formed on the mesas; a plurality of source regions are formed in the n− epi-layer at the mesas asides the planar gates; each of the source regions is a region having doubled diffused impurities formed therein; an inter-metal dielectric layer having source contact holes and gate contact holes formed therein, is formed on the source regions, the first poly-Si layer, and the planar gates; a first interconnecting metal layer is formed on the inter-metal dielectric layer and connected to the source regions through the source contact plugs; a second interconnecting metal layer is formed on the inter-metal dielectric layer and connected to the planar gate through the gate contact plugs; and a rear metal layer served as a drain electrode is formed on a rear surface of the n+ semiconductor substrate; each of the source regions includes a p body, a shallower n+ region extended to the mesa surface formed in the p body, and a p+ region formed in the p body right at a bottom of the source contact plug.
According to a second preferred embodiment, the VDMOS transistor comprises a n− epi-layer on a n+ semiconductor substrate having a plurality of trenches formed in parallel therein and the trenches spaced each other by a mesa; each of the trenches has a trench oxide layer formed on a bottom and sidewall and a stack of first oxide layer/a first conductive poly-Si layer filled in the trench; a planar gate oxide layer is formed on the mesas and a plurality of rows of a second poly-Si layer extended to the ends of the substrate, are formed on the planar gate oxide layer and the first oxide layer; a plurality of source regions are formed in the n− epi-layer asides the planar gates; each of the source regions is a region having doubled diffused impurities formed therein; an inter-metal dielectric layer having source contact holes, is formed on the source regions, the first oxide layer, and the planar gates; a interconnection metal layer is formed on the inter-metal dielectric layer and is connected to the source regions through the source contact plugs; a interconnection metal layer is formed on the inter-metal dielectric layer and connected to the planar gate through the source contact plugs; and a rear metal layer served as a drain electrode is formed on a rear surface of said n+ semiconductor substrate. Each of the source regions includes a p body, a shallower n+ region extended to the mesa surface formed in the p body, and a p+ region formed in the p body at a bottom of the source contact plugs.
The present invention discloses a trench-vertical doubled diffused MOS transistor, hereinafter called a VDMOS transistor. Please refer to a top view shown in
In accordance with a first preferred embodiment of the present invention, a trench VDMOS transistor is illustrated in the plan-view
In accordance with a second preferred embodiment of the present invention, a trench VDMOS transistor is illustrated in the plan-view
Asides the rows of the rows of the second poly-Si layer 140 are source regions formed in the n− epi-layer 105. Each of the source regions has a shallow n+ implanted region 155 extended to the mesa 118 formed into the p body 135. An inter-metal dielectric layer 185 formed on the resulted exposed surfaces. The inter-metal dielectric layer 185 has a plurality of source contact holes 187s formed therein. An interconnecting metal layer 191s is formed on the inter-metal dielectric layer 185 and filled in the source contact holes as source contact plugs 188s connecting the source region and the first poly-Si layer 130 through the first oxide layer 135. Under the source contact plugs 188s are p+ implanted regions 165 as source contact pads SP formed in the p body 135. A rear metal layer 195 served as a drain electrode formed on the rear n+ substrate 100.
The detailed processes for forming the structure of VDMOS transistor are as follows.
Please refer to
Subsequently, a thermal oxidation process is carried out to form a trench oxide layer 120 conformally formed on the sidewalls and bottoms of the trenches and the mesas 118. The processes can repair the damage during etching.
Referring to
Still referring to
Please refer to
Referring to cross-sectional views
Thereafter, an anisotropic dry etch is performed to pattern the inter-metal dielectric layer 185, the planar gate oxide layer 127, using the n− epi-layer 105 as an etching stop layer. Then a timing control etch is successively performed to remove the exposed n+ implanted regions 155. After the photoresist layer 186 is removed, a third ion implantation through the contact holes is carried out to form p+ regions 165 in the p bodies 135. After the ion implantations, an anneal process at a temperature between about 800-1000° C. to activate the impurities are carried out.
Subsequently, an interconnecting metal layer is deposited on the inter-metal dielectric layer 185 and filled in the contact holes 187s and 187g by sputtering. The interconnection metal layer is then patterned to two separate groups 191s and 191g. Group 191s connects the source region and the first poly-Si layer 130 through the source contact plugs 188s, as shown in
The interconnecting metal layer 191s, 191g may be a stack layer of Ti/TiN, TiNi/Ag or TiW/Al or a single metal layer formed of aluminum. The drain electrode of the VDMOS transistor is a rear metal layer 195 formed on the rear side of the n+ semiconductor 100.
Refer to
According to a second preferred embodiment, the illustrating diagram is started from the
Thereafter, a thermal process is performed to form the planar oxide layer 127 again, and a second poly-Si layer 140 with in-situ doped conductive impurities deposited on the planar gate oxide layer 127 is followed. A photoresist pattern 142 is formed on the second poly-Si layer 140 to define a plurality of rows of the second poly-Si layer 140 as gates, as shown in cross-sectional views
Along the cutting line AA′ of
Referring to cross-sectional views of
Subsequently, an interconnecting metal layer 191s is deposited on the inter-metal dielectric layer 185 and filled in the source contact holes 187s by sputtering. The results are shown in
In the second preferred embodiment, the gate contact plugs are formed on the ends of the second poly-Si layer 140 only.
The benefits of the present invention are:
(1). The VDMOS transistor according to the present invention has a better capability of reverse break down voltage performance than the prior art, shown in
(2). The VDMOS transistor according to the present invention includes a planar MOS gate whose planar gate oxide layer 127 is much thinner than the trench gate oxide layer 120 so that the VDMOS transistor has a lower threshold forward voltage than the VDMOS transistor in accordance with the prior art, shown in
As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. For instance, the aforementioned exemplary embodiments are illustrated by n type VDMOS transistor formed on the n type substrate; the processes may be applied to form p-type VDMOS transistor formed on p type substrate.
Claims
1. A trench vertical doubled diffused transistor (VDMOS transistor), comprising:
- a first conductive-impurity-lightly-doped epi-layer on a first conductive-impurity-heavily-doped semiconductor substrate having a plurality of trenches formed in parallel therein, said trenches spaced each other by a mesa in between and each of said trenches having a trench oxide layer formed on a bottom and sidewall and a first conductive poly-Si layer filled;
- a plurality of planar gates formed on said mesas, said planar gates having a second conductive poly-Si layer on a planar gate oxide layer;
- a plurality of source regions formed in said first conductive-impurity-lightly-doped epi-layer asides said planar gates, each of said source regions having doubled diffused impurities formed therein, each of said planar gates being a discrete island associated with said source regions distributed along a longitudinal direction of said trenches;
- an inter-metal dielectric layer having source contact holes and gate contact holes formed therein, formed on said source regions, said first poly-Si layer, said planar gates, said inter-metal dielectric layer;
- a first interconnection metal layer formed on said inter-metal dielectric layer and filled said source contact holes to form source contact plugs connecting said source regions and said first poly-Si layer;
- a second interconnection metal layer formed on said inter-metal dielectric layer and filled said gate contact holes to form gate contact plugs connecting said second conductive poly-Si layer; and
- a rear metal layer formed on a rear surface of said first conductive-impurity-heavily-doped semiconductor substrate as a drain electrode.
2. The VDMOS transistor according to claim 1, wherein each of said source regions having a second conductive-impurity-implanted body formed in said first conductive-impurity-lightly-doped epi-layer, and a shallower first conductive-impurity-heavily-implanted region inside said second conductive-impurity-implanted body and said shallower first conductive-impurity-heavily-implanted region extended to a surface of said first conductive lightly doped epi-layer.
3. The VDMOS transistor according to claim 1, wherein said source contact plugs connected said second conductive-impurity-implanted body and said first conductive-impurity-heavily-implanted region.
4. The VDMOS transistor according to claim 3, wherein each of said source regions further comprises a second conductive-impurity-heavily-implanted region formed in said second conductive-impurity-implanted body right beneath a bottom of said source contact plugs so that said source contact plugs connected said first conductive-impurity-heavily-implanted region and said second conductive-impurity-implanted body through said second conductive-impurity-heavily-implanted region.
5. The VDMOS transistor according to claim 1, further comprises a planar gate oxide layer formed in between said first poly-Si layer and said inter-metal dielectric layer.
6. A trench vertical doubled diffused transistor (VDMOS transistor), comprising:
- a first conductive-impurity-lightly-doped epi-layer on a first conductive-impurity-heavily-doped semiconductor substrate having a plurality of trenches formed in parallel therein, said trenches spaced each other by a mesa in between and each of said trenches having a trench oxide layer formed on a bottom and sidewall, stack layers of a first oxide layer over a first conductive poly-Si layer filled in each of said trenches;
- a planar gate oxide layer formed on said mesas;
- a plurality of rows of a second conductive poly-Si layer formed on said planar gate oxide layer, and said first oxide layer, said rows of said second conductive poly-Si layer along a transversal direction of said trenches;
- a plurality of source regions formed in said first conductive-impurity-lightly doped epi-layer asides said rows of said second poly-Si layer, each of said source regions being doubled diffused regions;
- an inter-metal dielectric layer formed on said source regions, said first oxide layer, said rows of said second poly-Si layer, said inter-metal dielectric layer having source contact holes formed therein;
- an interconnection metal layer formed on said inter-metal dielectric layer and filled said source contact holes to form source contact plugs connecting said source regions and said first poly-Si layer; and
- a rear metal layer formed on a rear surface of said first conductive-impurity-heavily-doped semiconductor substrate as a drain electrode.
7. The VDMOS transistor according to claim 6, wherein each of said source regions having a second conductive-impurity-implanted body formed in said first conductive-impurity-lightly-doped epi-layer, and a shallower first conductive-impurity-implanted region inside said second conductive-impurity-implanted body and said shallower first conductive-impurity-heavily-implanted region extended to a surface of said first conductive-impurity-doped epi-layer.
8. The VDMOS transistor according to claim 6, wherein said source contact plugs connected said second conductive-impurity-implanted body and said first conductive-impurity-heavily-implanted region.
9. The VDMOS transistor according to claim 8, wherein each of said source regions further comprises a second conductive-impurity-heavily-implanted region formed in said second conductive-impurity-implanted body right beneath a bottom of said source contact plugs so that said source contact plugs connected said first conductive-impurity-heavily-implanted region and said second conductive-impurity-implanted body through said second conductive-impurity-heavily-implanted region.
Type: Application
Filed: Jun 23, 2014
Publication Date: Dec 25, 2014
Inventor: Qinhai Jin (Zhubei City)
Application Number: 14/311,521
International Classification: H01L 29/78 (20060101); H01L 29/08 (20060101); H01L 29/06 (20060101);