Gate Controls Vertical Charge Flow Portion Of Channel (e.g., Vmos Device) Patents (Class 257/329)
  • Patent number: 11908907
    Abstract: An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Ruilong Xie, Tian Shen, Kai Zhao
  • Patent number: 11910607
    Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Sunggil Kim, Dongkyum Kim, Seulye Kim, Ji-Hoon Choi
  • Patent number: 11908944
    Abstract: A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Lan Yu, Samuel Sung Shik Choi, Ruilong Xie
  • Patent number: 11910605
    Abstract: A semiconductor storage includes a stack, columns, and first, second, third, fourth, and fifth insulators. The stack includes first conductive layers, and second and third conductive layers below and above the first conductive layers, respectively. The columns penetrate the stack in a first direction. The first and second insulators penetrate the stack and are separated from each other in a second direction. The third insulator is between the first and second insulators in a third direction. The third insulator includes first and second portions apart from each other in the second direction. The fourth insulator is between the first and second portions. The fifth insulator is between the first and second portions above the fourth insulator. The second conductive layer includes two electrically-separated regions, between which the third and fourth insulators are provided. The third conductive layer includes two electrically-separated regions between which the third and fifth insulators are provided.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Gen Kuribayashi, Shigeki Kobayashi
  • Patent number: 11895852
    Abstract: A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yiming Zhu, Erxuan Ping
  • Patent number: 11895822
    Abstract: The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yachao Xu
  • Patent number: 11894305
    Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 6, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins, Rita J. Klein, Everett A. McTeer, Lifang Xu, Daniel Billingsley, Collin Howder
  • Patent number: 11887646
    Abstract: In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: January 30, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Chen, Cheng Gan, Xin Wu, Wei Liu
  • Patent number: 11881486
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: January 23, 2024
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Patent number: 11876437
    Abstract: According to some embodiments, a half-bridge circuit is provided. The half-bridge circuit includes a substrate, a monolithic die over the substrate, a switch node, a high-side switch integrated with the monolithic die and coupled to the switch node, and a conductive structure including a first terminal coupled to the substrate and a second terminal coupled to the switch node.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 16, 2024
    Assignee: Infineon Technologies Austria AG
    Inventor: Kennith Kin Leong
  • Patent number: 11877454
    Abstract: A vertical memory device includes a substrate, a plurality of gate electrodes vertically stacked over the substrate in a cell array region, and a plurality of multi-layered pad portions formed over the substrate in a contact region. Each multi-layered pad portion of the plurality of multi-layered pad portions extends from an end of a gate electrode of the plurality of gate electrodes. Each multi-layered pad portion of the plurality of multi-layered pad portions includes a lower pad, an upper pad spaced vertically apart from the lower pad, a buffer pad formed between the lower pad and the upper pad, and a pad interconnection portion interconnecting the lower pad and the upper pad.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Kwang-Seok Oh
  • Patent number: 11876132
    Abstract: A semiconductor device includes a first electrode; a first semiconductor region provided on the first electrode; a second semiconductor region provided on the first semiconductor region; a third semiconductor region provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode aligned with the first semiconductor region and the second semiconductor region; a gate electrode provided between the third electrode and the second semiconductor region; a first insulating portion including a first insulating region provided between the third electrode and the first semiconductor region and facing the third electrode, a second insulating region facing the first semiconductor region, and at least one air-gap region located between the first insulating region and the second insulating region; and a second insulating portion provided between the gate electrode and the second semiconductor region.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 16, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshifumi Nishiguchi
  • Patent number: 11864369
    Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 2, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Yu Ye, Chung-Yi Lin, Yun-Ju Pan, Chee-Wee Liu
  • Patent number: 11839073
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11824024
    Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: November 21, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuaki Hozumi
  • Patent number: 11825646
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following steps. A bit line structure is formed on a substrate. Each of the bit lines is provided with an insulation block on a side facing away from the substrate. A shielding portion is formed on a top of the insulation block that faces away from the substrate. A projection area of the shielding portion on the substrate is larger than a projection area of the insulation block on the substrate. An insulation sidewall is formed on a sidewall of the bit line and a sidewall of the insulation block, and a gap extending to the substrate is formed within the insulation sidewall corresponding to the shielding portion.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: November 21, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Bingyu Zhu, Jingwen Lu
  • Patent number: 11804540
    Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi Chan Jun, Min Gyu Kim, Gil-Hwan Son
  • Patent number: 11792989
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: October 17, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Patent number: 11792993
    Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conduc
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Junghwan Kim, Chanhyoung Kim
  • Patent number: 11791408
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, an insulating part, a conductive part, and a gate electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating part is provided on the first electrode. The conductive part is provided in the insulating part and is arranged with the first semiconductor region. The gate electrode is provided in the insulating part. The gate electrode is positioned above the conductive part and is arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and the insulating part, and is electrically connected to the third semiconductor region.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: October 17, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kenya Kobayashi
  • Patent number: 11784257
    Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventor: Bernhard Sell
  • Patent number: 11776628
    Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 3, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Kazuki Isozumi, Parth Amin
  • Patent number: 11776999
    Abstract: A semiconductor device includes a semiconductor layer, first and second electrodes, one or more gate electrodes, and an array of structures. The semiconductor layer has first and second sides opposite to each other in a first direction. The semiconductor layer is single crystal silicon. The array of structures is in the semiconductor layer and arranged in a second direction perpendicular to the first direction and along a [100] direction of the single crystal silicon and in a third direction that is perpendicular to the first direction and not perpendicular to the second direction. A first distance between first and second ones of the structures adjacent to each other in the third direction is less than a second distance between the first one and a third one of the structures adjacent to the first one in the second direction.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: October 3, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tsuyoshi Kachi, Tatsuya Nishiwaki
  • Patent number: 11776620
    Abstract: A semiconductor base material stands on a substrate in a vertical direction or extends in a horizontal direction. Between first and second impurity layers disposed at the ends of the semiconductor base material, first and second gate insulating layers and first and second gate conductor layers are disposed around the semiconductor base material. A memory write operation is performed where voltages are applied to the first and second impurity layers and the first and second gate conductor layers to cause an impact ionization phenomenon to occur in a channel region, and among generated groups of electrons and positive holes, the group of electrons are discharged from the channel region and some of the group of positive holes are retained in the channel region. A memory erase operation is performed where the retained group of positive holes are discharged via any of or both of the first and second impurity layers.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: October 3, 2023
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Koji Sakui, Nozomu Harada
  • Patent number: 11777419
    Abstract: A semiconductor device includes: a semiconductor substrate in which a cell region, an isolation region being a region which is located outward of the cell region, and a termination region including a guard ring region being located outward of the isolation region and an excess region being a region which is located outward of the guard ring region are defined; an insulating layer covering a top surface of the semiconductor substrate in the isolation region and the termination region; a surface electrode located on a portion of the top surface of the semiconductor substrate and a portion of a top surface of the insulating layer in the cell region and the isolation region; and a waterproof layer covering a portion of the insulating layer exposed from the surface electrode. The waterproof layer is spaced apart from the surface electrode.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: October 3, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 11769830
    Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 26, 2023
    Inventors: Seungchan Yun, Donghwan Han
  • Patent number: 11765902
    Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Lifang Xu
  • Patent number: 11764298
    Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-? layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: September 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Ruilong Xie, Heng Wu, Junli Wang, Brent Anderson
  • Patent number: 11764259
    Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Tenko Yamashita, Xin Miao, Wenyu Xu, Kangguo Cheng
  • Patent number: 11764294
    Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 19, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Tomomi Yamanobe, Yoshinobu Takeshita, Kazutaka Kodama, Minako Oritu
  • Patent number: 11757012
    Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Andrew Greene, Dechao Guo, Tenko Yamashita, Veeraraghavan S. Basker, Robert Robison, Ardasheir Rahman
  • Patent number: 11756956
    Abstract: Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 12, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11756823
    Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 12, 2023
    Assignee: Newport Fab, LLC
    Inventors: Allan K Calvo, Paul D Hurwitz, Roda Kanawati
  • Patent number: 11757036
    Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: September 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Chen Zhang, Julien Frougier, Alexander Reznicek, Shogo Mochizuki
  • Patent number: 11728425
    Abstract: The semiconductor device includes a first source/drain layer, a dielectric layer, a channel, a gate electrode, a first gate dielectric layer, a seed layer, a conductive layer, and a second source/drain layer. The dielectric layer is disposed on the first source/drain layer, in which the dielectric layer has a hole penetrating the dielectric layer. The channel is disposed in the hole and extends substantially perpendicular to an upper surface of the first source/drain layer. The gate electrode surrounds the channel. The first gate dielectric layer is disposed between the gate electrode and the channel. The seed layer is disposed between the gate electrode and the dielectric layer and on an upper surface of the dielectric layer, in which the seed layer covers a portion of a sidewall of the hole.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: August 15, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Jhen Wu, Hsih-Yang Chiu
  • Patent number: 11728344
    Abstract: A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11721629
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Yiping Wang, Jordan D. Greenlee, John Hopkins
  • Patent number: 11710699
    Abstract: A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 25, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Jingyun Zhang, Reinaldo Vega, Kangguo Cheng
  • Patent number: 11706934
    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Stephen H. Tang, Stephen W. Russell
  • Patent number: 11706919
    Abstract: A vertical memory device includes first horizontal gate electrodes disposed on a substrate and spaced apart from each other in a first direction that is substantially perpendicular to an upper surface of the substrate. Each of the first horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. A vertical channel extends through the first horizontal gate electrodes in the first direction. A charge storage structure is disposed between the vertical channel and each of the first horizontal gate electrodes. A first vertical gate electrode extends through the first horizontal gate electrodes in the first direction. The first vertical gate electrode is electrically insulated from the first horizontal gate electrodes. A first horizontal channel is disposed at a portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seokcheon Baek
  • Patent number: 11695041
    Abstract: A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangsu Kim, Junbeom Park, Junggil Yang
  • Patent number: 11695061
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Patent number: 11696442
    Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
  • Patent number: 11696430
    Abstract: An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11688775
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Brent A. Anderson
  • Patent number: 11682727
    Abstract: A SiO2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO2 layer. P+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 20, 2023
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Yoshiaki Kikuchi
  • Patent number: 11677001
    Abstract: The present disclosure discloses a semiconductor device with C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the same. According to the embodiments, the semiconductor device may comprise a channel portion on a substrate, the channel portion including two or more curved nanosheets or nanowires spaced apart from each other in a lateral direction relative to the substrate and each having a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a gate stack surrounding an outer circumference of each nanosheet or nanowire in the channel portion.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: June 13, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11672119
    Abstract: A vertical memory device includes a gate electrode structure, channels, a charge storage structure, and a division pattern. The gate electrode includes gate electrodes spaced apart from each other in a first direction. The channel extends through the gate electrode structure, and includes a first portion and a second portion on and contacting the first portion. The second portion includes a lower surface having a width less than that of an upper surface of the first portion. The charge storage structure covers an outer sidewall of the channel. The division pattern extends between the channels in a second direction, and includes a first dummy channel and a first dummy charge storage structure covering a sidewall and a lower surface thereof. The first dummy channel includes the same material as that the channel, and the first dummy charge storage structure includes the same material as the charge storage structure.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 6, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jisung Cheon, Jiye Noh, Byunggon Park, Jinsoo Lim
  • Patent number: 11665901
    Abstract: Embodiments of structure and methods for forming a memory device are provided. In an example, a memory device includes a substrate, a stack above the substrate, a channel structure, and a source contact structure each extending vertically through the memory stack. The source contact structure includes (i) a plurality of first source contact portions each extending vertically and laterally separated from one another and (ii) a second source contact portion extending vertically over and in contact with the plurality of first source contact portions, the second source contact portion being laterally continuous.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 30, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Lu Zhang, Zhipeng Wu, Bo Xu, Kai Han, Chuan Yang, Zi Yin, Liuqun Xie
  • Patent number: 11665894
    Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Larsen, Lifang Xu