Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.

Abstract: A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.

Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

Abstract: Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor memory device includes a first conductive pattern, a second conductive pattern configured to overlap a first line component of the first conductive pattern and to leave exposed a first pad component of the first conductive pattern. The semiconductor memory device also includes an interlayer insulating layer between the first conductive pattern and the second conductive pattern. The semiconductor memory device further includes a first conductive contact and a first insulating pillar extending from the first pad component of the first conductive pattern in opposite directions.

Abstract: A method of manufacturing a semiconductor memory device is provided. The method include: providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate; defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer; removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer; forming gate stacks around peripheries of the channel layer in the respective active regions; and forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.

Abstract: A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.

Abstract: In this patent application, a new Metal Oxide Semiconductor MOS planar cell design concept is proposed. The inventive power semiconductor includes a planar cell forming a horizontal channel and a plurality of trenches, which are arranged orthogonally to the plane of the planar cells. A second p base layer is introduced which extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, a vertical channel is prevented from forming in the trench regions while allowing the horizontal channels to form. This is extremely important in order to avoid significant issues (i.e. shifts in Vth) encountered in prior art IGBT designs. The new cell concept adopts planar MOS channel and Trench technology in a single MOS cell structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines.

Abstract: A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: A method of manufacturing a semiconductor substrate according to an embodiment includes a first step of forming a groove having a bottom surface and a side surface on which scallops are formed by performing a process including isotropic etching on a main surface of a substrate, a second step of performing at least one of a hydrophilic treatment on the side surface of the groove and a degassing treatment on the groove, and a third step of removing the scallops formed on the side surface of the groove and planarizing the side surface by performing anisotropic wet etching in a state where the bottom surface of the recess is present.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate.

Abstract: A trench MOSFET can include: a semiconductor layer having a first doping type; a trench extending from an upper surface of the semiconductor layer to internal portion of the semiconductor layer; insulating layers and electrode conductors located in the trench; a body region having a second doping type in an upper region of the semiconductor layer adjacent to the trench; and a floating region having the first doping type located in a predetermined position of the semiconductor layer adjacent to both sides of the trench, where the floating region is located below the body region and is separated from the body region.

Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.

Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device). When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

Abstract: An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: P+ layers 32b and 32e that cover the entire top portions of Si pillars 6b and 6e and surround the Si pillars 6b and 6e with an equal width in plan view are formed in a self-aligned manner with the Si pillars 6b and 6e. W layers 33b and 33e are formed on the P+ layers 32b and 32e. A band-shaped contact hole C3 that is partly in contact with regions of the W layers 33b and 33e and that extends in the Y direction is formed. A power supply wiring metal layer Vdd is formed such that the band-shaped contact hole C3 is filled with the power supply wiring metal layer Vdd. In plan view, regions of the W layers 33b and 33e partly protrude outward from the band-shaped contact hole C3.

Abstract: Provided are a 3-dimensional (3D) flash memory with an improved degree of integration and a method of manufacturing the same. The 3D flash memory may include at least one vertical string formed to extend in one direction on a substrate and comprising a channel layer formed to extend in the one direction and a charge storage layer formed to extend in the one direction so as to surround the channel layer; a plurality of electrode layers stacked to be vertically connected to the at least one vertical string; and a source line formed to be buried in the substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.

Abstract: The present disclosure relates to a method of forming a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region pattern layer, the first active region pattern layer includes a bridge pattern, and a first active region pattern region and a second active region pattern region; the first active region pattern region includes a first active region pattern for defining a first pull-down transistor of a first memory cell structure; the second active region pattern region includes a first symmetrical active region pattern for defining a second pull-down transistor of a second memory cell structure; and the first active region pattern and the first symmetrical active region pattern are adjacent to each other and connected through the bridge pattern, a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected through the bridge pattern.

Abstract: A gate TiN layer of adjacent Si pillars among Si pillars contacts at entire channel length in a vertical direction. SiO2 layers are formed, surrounding the Si pillars, and mask material layers on top thereof, and being spaced from each other. Then, a SiN layer is formed surrounding the SiO2 layers. Then, the mask material layers and the SiO2 layers are removed. Then, a P+ layer and N+ layers which upper surfaces are lower than an upper surface position of the SiN layer are formed surrounding each top of the Si pillars by selective epitaxial crystal growth method.

Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; and a SiC layer. The SiC layer includes: a first conductive type first SiC region having a first region, a second region facing the gate electrode, and a third region in contact with the first electrode; a second conductive type second SiC region between the second region and the third region; a second conductive type third SiC region, the second region interposed between the second SiC region and the third SiC region; a second conductive type fourth SiC region, the third region interposed between the second SiC region and the fourth SiC region; a first conductive type fifth SiC region; a second conductive type sixth SiC region between the first region and the second SiC region; and a second conductive type seventh SiC region between the first region and the second SiC region and distant from the sixth SiC region in the first direction.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

Abstract: A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

Abstract: A power semiconductor device includes a control cell for controlling a load current and electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including a contact region having dopants of the first or second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to control a conduction channel in the channel region; and a contact plug including at least one of a doped semiconductive material or metal, and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which horizontally projects beyond lateral boundaries of the mesa.

Abstract: A driver circuit for a three-dimensional (3D) memory device has a super junction structure as a field management structure. The super junction structure could be referred to as an extended junction structure, which distributes the electrical field of the junction between the vertical channel and the gate conductor for a string driver. The vertical channel includes a channel conductor to connect vertically between a source conductor and a drain conductor. The extended junction structure extends in parallel with the vertical channel conductor, extending vertically toward the drain conductor, having a height greater than a height of the gate conductor.

Abstract: Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Abstract: A memory device includes a first and second conductor respectively included in a first and second layer stack stacked in a first direction and separated from each other; a first and second portion of a semiconductor extending in the first direction between the first and the second layer stack, and separated from each other in same layer; a first film between the first conductor and the first portion; a second film between the second conductor and the second portion; a first insulator between the first conductor and the first film; a second insulator between the second conductor and the second film; a third insulator between the first insulator and the first film; and a fourth insulator between the second insulator and the second film. The third and fourth insulator have a higher dielectric constant than the first and second insulator.

Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, and contains nickel or copper, an entire back surface of the bonding layer being electrically connected to and in direct contact with an electrode in the semiconductor device; an anti-oxidation layer disposed on the bonding layer; and a protective layer disposed directly on a top surface of a peripheral portion of the bonding layer on which the anti-oxidation layer is absent, covering an outer peripheral edge of the bonding layer, wherein the protective layer is made of an electrically insulating resin.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A semiconductor device includes a semiconductor element having a substrate, a drift layer, a base region, a source region, trench gate structures, an interlayer insulating film, a source electrode, and a drain electrode. The substrate is made of silicon carbide. The drift layer is disposed on the substrate and has an impurity concentration lower than the substrate. The base region is made of silicon carbide and disposed on the drift layer. The source region is made of silicon carbide having an impurity concentration higher than the drift layer. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The interlayer insulating film covers the gate electrode and the gate insulating film. The source electrode is in ohmic-contact with the source region. The drain electrode is disposed on a rear surface of the substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.

Abstract: A semiconductor device includes: a cell stack structure including first cell stack layers and stack conductive layers, which are alternately stacked; a cell plug penetrating the cell stack structure; and a cell chip guard surrounding the cell stack structure and the cell plug. The cell chip guard includes a guard semiconductor layer and a guard insulating layer covering a sidewall of the guard semiconductor layer.