Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

Abstract: A semiconductor device includes: a cell stack structure including first cell stack layers and stack conductive layers, which are alternately stacked; a cell plug penetrating the cell stack structure; and a cell chip guard surrounding the cell stack structure and the cell plug. The cell chip guard includes a guard semiconductor layer and a guard insulating layer covering a sidewall of the guard semiconductor layer.

Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.

Abstract: An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

Abstract: A bottom portion of a Ta pillar serving as a contact portion is connected to an N+ layer and a P+ layer, and a gate HfO2 layer is connected to side surfaces of Si pillars and a Ta pillar serving as a contact portion and an upper surface of a SiO2 layer between the Si pillars and the Ta pillar serving as the contact portion. Gate TiN layers are provided on a side surface of the gate HfO2 layer surrounding the Si pillars. Midpoints of the Si pillars and the Ta pillar serving as the contact portion are on one first line in plan view.

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.

Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide substrate, a first silicon carbide epitaxial layer, and a second silicon carbide epitaxial layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first silicon carbide epitaxial layer is in contact with a whole of the first main surface. The second silicon carbide epitaxial layer is in contact with a whole of the second main surface. A carrier concentration of the silicon carbide substrate is higher than a carrier concentration of each of the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

Abstract: Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET1 below a top VTFET1, and a bottom VTFET2 below a top VTFET2, and a method of forming a stacked VTFET device are also provided.

Abstract: A semiconductor device of embodiments includes: a semiconductor layer; a first insulating layer provided on the semiconductor layer; a first metal layer provided on the first insulating layer and containing aluminum (Al); a second metal layer provided on the first insulating layer and containing aluminum (Al); and a second insulating layer provided on the first insulating layer, provided between the first metal layer and the second metal layer, having a top surface in contact with a side surface of the first metal layer and a side surface of the second metal layer, and containing silicon (Si) and nitrogen (N).

Abstract: A semiconductor device including a static random access memory (SRAM) in a three-dimensional (3D) stack is provided. The semiconductor device includes a first transistor stack including a first channel and a first gate, a second transistor stack including a second channel and a second gate, the second transistor stack being disposed above the first transistor stack, a bit line disposed on a first portion of an upper surface of the first channel, a voltage source disposed on a first portion of an upper surface of the second channel and a first shared contact connecting the first channel to the second channel, where a width of the second channel is less than a width of the first channel.

Abstract: A liquid crystal display device includes: a substrate; a plurality of vertical organic light-emitting transistors; a data line that supplies a voltage to a gate electrode of the vertical organic light-emitting transistor; a thin-film transistor that is connected between the gate electrode of each of the vertical organic light-emitting transistors and the data line and controls supply of the voltage to the gate electrode of the vertical organic light-emitting transistor; a gate line that is connected to the gate electrode of the thin-film transistor and transmits a signal for switching the thin-film transistor; and a plurality of current supply lines that are wired in a first direction outside a formation region of the vertical organic light-emitting transistor, the current supply lines being in contact with a source electrode of the vertical organic light-emitting transistor to supply a current to the vertical organic light-emitting transistor.

Abstract: A semiconductor device of the present disclosure includes: a semiconductor element disposed on a first surface side of a semiconductor substrate; a through-electrode that is provided through the semiconductor substrate in a thickness direction of the semiconductor substrate and introduces charge obtained in the semiconductor element to a second surface side of the semiconductor substrate; and an amplifier transistor that outputs an electrical signal based on the charge introduced by the through-electrode, the amplifier transistor using the through-electrode as a gate electrode and including a source region and a drain region around the through-electrode.

Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Abstract: A 3D flash memory device includes a substrate having a substantial planar surface. A plurality of active columns of semiconducting material is disposed above the substrate. Each of the plurality of active columns extends along a first direction orthogonal to the planar surface of the substrate. The plurality of active columns is arranged in a two-dimensional array. Each of the plurality of active columns may comprise multiple local bit lines and multiple local source lines extending along the first direction. Multiple channel regions are disposed between the multiple local bit lines and multiple local source lines. A word line stack wraps around the plurality of active columns. A charge-storage element is disposed between the word line stack and each of the plurality of active columns.

Abstract: An image sensor is disclosed. The image sensor includes a semiconductor substrate, a plurality of pillars protruding from the semiconductor substrate, and spaced from each other, a spacer layer on the semiconductor substrate and a sidewall of each of the plurality of pillars, a plurality of gate structures on the spacer layer, and a plurality of unit pixels arranged in a matrix form. The first unit pixel includes a first photodiode (PD) formed in the semiconductor substrate, a first pillar, a second pillar and a third pillar of the plurality of pillars, and a first gate structure and a second gate structure of the plurality of gate structures. Each of the first pillar and the second pillar includes a first channel region and a first drain region on the first channel region. The third pillar is not surround by any gate structure of the plurality of gate structures.

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

Abstract: Power semi-conductor module (1) comprising: —at least one IGBT with a Gate G forming a first electrode (11) and an Emitter E forming a second electrode (12), or —at least one MOSFET with a Gate G forming a first electrode (11) and a Source S forming a second electrode (12). The first electrode (11) includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion (13). The monitoring portion (13) is in electrical contact with the second electrode (12) such that a leakage current flows between the first electrode (11) and the second electrode (12) in an operational state of the module (1). The monitoring portion (13) has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module (1).

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.

Abstract: A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

Abstract: An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.

Abstract: A semiconductor storage includes a stack, columns, and first, second, third, fourth, and fifth insulators. The stack includes first conductive layers, and second and third conductive layers below and above the first conductive layers, respectively. The columns penetrate the stack in a first direction. The first and second insulators penetrate the stack and are separated from each other in a second direction. The third insulator is between the first and second insulators in a third direction. The third insulator includes first and second portions apart from each other in the second direction. The fourth insulator is between the first and second portions. The fifth insulator is between the first and second portions above the fourth insulator. The second conductive layer includes two electrically-separated regions, between which the third and fourth insulators are provided. The third conductive layer includes two electrically-separated regions between which the third and fifth insulators are provided.

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.

Abstract: The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: A semiconductor device includes a first electrode; a first semiconductor region provided on the first electrode; a second semiconductor region provided on the first semiconductor region; a third semiconductor region provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode aligned with the first semiconductor region and the second semiconductor region; a gate electrode provided between the third electrode and the second semiconductor region; a first insulating portion including a first insulating region provided between the third electrode and the first semiconductor region and facing the third electrode, a second insulating region facing the first semiconductor region, and at least one air-gap region located between the first insulating region and the second insulating region; and a second insulating portion provided between the gate electrode and the second semiconductor region.

Abstract: A vertical memory device includes a substrate, a plurality of gate electrodes vertically stacked over the substrate in a cell array region, and a plurality of multi-layered pad portions formed over the substrate in a contact region. Each multi-layered pad portion of the plurality of multi-layered pad portions extends from an end of a gate electrode of the plurality of gate electrodes. Each multi-layered pad portion of the plurality of multi-layered pad portions includes a lower pad, an upper pad spaced vertically apart from the lower pad, a buffer pad formed between the lower pad and the upper pad, and a pad interconnection portion interconnecting the lower pad and the upper pad.

Abstract: According to some embodiments, a half-bridge circuit is provided. The half-bridge circuit includes a substrate, a monolithic die over the substrate, a switch node, a high-side switch integrated with the monolithic die and coupled to the switch node, and a conductive structure including a first terminal coupled to the substrate and a second terminal coupled to the switch node.

Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following steps. A bit line structure is formed on a substrate. Each of the bit lines is provided with an insulation block on a side facing away from the substrate. A shielding portion is formed on a top of the insulation block that faces away from the substrate. A projection area of the shielding portion on the substrate is larger than a projection area of the insulation block on the substrate. An insulation sidewall is formed on a sidewall of the bit line and a sidewall of the insulation block, and a gap extending to the substrate is formed within the insulation sidewall corresponding to the shielding portion.

Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer.

Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, an insulating part, a conductive part, and a gate electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating part is provided on the first electrode. The conductive part is provided in the insulating part and is arranged with the first semiconductor region. The gate electrode is provided in the insulating part. The gate electrode is positioned above the conductive part and is arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and the insulating part, and is electrically connected to the third semiconductor region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conduc

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: A semiconductor device includes a semiconductor layer, first and second electrodes, one or more gate electrodes, and an array of structures. The semiconductor layer has first and second sides opposite to each other in a first direction. The semiconductor layer is single crystal silicon. The array of structures is in the semiconductor layer and arranged in a second direction perpendicular to the first direction and along a [100] direction of the single crystal silicon and in a third direction that is perpendicular to the first direction and not perpendicular to the second direction. A first distance between first and second ones of the structures adjacent to each other in the third direction is less than a second distance between the first one and a third one of the structures adjacent to the first one in the second direction.

Abstract: A semiconductor device includes: a semiconductor substrate in which a cell region, an isolation region being a region which is located outward of the cell region, and a termination region including a guard ring region being located outward of the isolation region and an excess region being a region which is located outward of the guard ring region are defined; an insulating layer covering a top surface of the semiconductor substrate in the isolation region and the termination region; a surface electrode located on a portion of the top surface of the semiconductor substrate and a portion of a top surface of the insulating layer in the cell region and the isolation region; and a waterproof layer covering a portion of the insulating layer exposed from the surface electrode. The waterproof layer is spaced apart from the surface electrode.

Abstract: A semiconductor base material stands on a substrate in a vertical direction or extends in a horizontal direction. Between first and second impurity layers disposed at the ends of the semiconductor base material, first and second gate insulating layers and first and second gate conductor layers are disposed around the semiconductor base material. A memory write operation is performed where voltages are applied to the first and second impurity layers and the first and second gate conductor layers to cause an impact ionization phenomenon to occur in a channel region, and among generated groups of electrons and positive holes, the group of electrons are discharged from the channel region and some of the group of positive holes are retained in the channel region. A memory erase operation is performed where the retained group of positive holes are discharged via any of or both of the first and second impurity layers.

Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.