Gate Controls Vertical Charge Flow Portion Of Channel (e.g., Vmos Device) Patents (Class 257/329)
  • Patent number: 11563022
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Indra V. Chary, Justin B. Dorhout, Jian Li, Haitao Liu, Paolo Tessariol
  • Patent number: 11563007
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate, a cell capacitor, a channel structure, a lining material, a word line and a bit line. The cell capacitor is disposed over the substrate. The channel structure is disposed over the cell capacitor, wherein the channel structure comprises a horizontal member and at least two vertical members extending from the horizontal member and separated by a ditch on the horizontal member. The lining material surrounds each of the at least two vertical members. The word line encloses the at least two vertical members and partially fills the ditch. The bit line is disposed over the channel structure.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 24, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11545499
    Abstract: Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: January 3, 2023
    Assignee: International Business Machines Corporation
    Inventor: Tenko Yamashita
  • Patent number: 11545492
    Abstract: A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem. The semiconductor material of the stem comprises an upper source/drain region and a channel region there-below. The transistor comprises at least one of (a) and (b), where (a): the semiconductor material of the stem comprises a lower source/drain region below the channel region, and (b): the semiconductor material of the base comprises a lower source/drain region. A gate is operatively laterally adjacent the channel region of the stem. Other embodiments are disclosed, including arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor. Methods are disclosed.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11545437
    Abstract: A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Takashi Watanabe, Yasuhito Yoshimizu
  • Patent number: 11545571
    Abstract: The semiconductor device includes a first source/drain layer, a dielectric layer, a channel, a gate electrode, a first gate dielectric layer, a seed layer, a conductive layer, and a second source/drain layer. The dielectric layer is disposed on the first source/drain layer, in which the dielectric layer has a hole penetrating the dielectric layer. The channel is disposed in the hole and extends substantially perpendicular to an upper surface of the first source/drain layer. The gate electrode surrounds the channel. The first gate dielectric layer is disposed between the gate electrode and the channel. The seed layer is disposed between the gate electrode and the dielectric layer and on an upper surface of the dielectric layer, in which the seed layer covers a portion of a sidewall of the hole.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 3, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Jhen Wu, Hsih-Yang Chiu
  • Patent number: 11545573
    Abstract: A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Patent number: 11538933
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 27, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yi Su, Madhur Bobde
  • Patent number: 11538824
    Abstract: Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: December 27, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Lei Xue, Lan Yao, Chia-Chann Shiue, Xiaoxin Liu
  • Patent number: 11538924
    Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: December 27, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi Chan Jun, Min Gyu Kim, Gil-Hwan Son
  • Patent number: 11532508
    Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 20, 2022
    Assignee: Infineon Technologies AG
    Inventors: Holger Huesken, Frank Dieter Pfirsch
  • Patent number: 11532756
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: December 20, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11532519
    Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Bo Liao, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11526647
    Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang, Yu-Ti Su, Wei-Hsiang Ma
  • Patent number: 11522058
    Abstract: A semiconductor device includes a first electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, a second electrode connected to the third and fourth semiconductor layers, a gate electrode extending from the fourth toward the second semiconductor layer next to the third semiconductor layer, a field plate electrode extending in a direction from the fourth toward the second semiconductor layer next to the second semiconductor layer, and a first insulating film between the field plate electrode and the second semiconductor layer and having a lower end further from the field plate electrode than the first semiconductor layer; the first, second, and fourth semiconductor layers are of a first conductivity type; and the third semiconductor layer is of a second conductivity type.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: December 6, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tsuyoshi Kachi
  • Patent number: 11522072
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Patent number: 11515427
    Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
  • Patent number: 11508742
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
  • Patent number: 11508819
    Abstract: A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 22, 2022
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Patent number: 11502230
    Abstract: A light emitting device including first, second, and third light emitting parts disposed one over another and each including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, a first conductive pattern at least partially disposed between the second and third light emitting parts, the first conductive pattern including a first portion electrically coupled with at least one of the first-type and second-type semiconductor layers of the first and second light emitting parts, and a second portion extending from the first portion and disposed on one surface of the second light emitting part between the second and third light emitting parts, and a second conductive pattern disposed on the third light emitting part and electrically coupled with the first conductive pattern, in which the second conductive pattern at least partially overlaps with the second portion of the first conductive pattern.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 15, 2022
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seong Gyu Jang, Chan Seob Shin, Seom Geun Lee, Ho Joon Lee, Jong Hyeon Chae
  • Patent number: 11489071
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active portion and a gate pad portion; a first semiconductor layer of the first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has first semiconductor regions of the first conductivity type, first trenches, gate insulating films, first gate electrodes, an interlayer insulating film, and second semiconductor regions of the second conductivity type. The gate pad portion has at least one second trench, an insulating film 9b, at least one second gate electrode, at least one fourth semiconductor region of the second conductivity type, and a gate electrode pad. Between the gate electrode pad and the semiconductor substrate, a polycrystalline silicon film is provided.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11482489
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Patent number: 11482627
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 25, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11476362
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 11456315
    Abstract: A method for forming a three-dimensional (3D) memory device is disclosed. In some embodiments, the method includes forming an alternating dielectric stack on a substrate, and forming a plurality of channel holes penetrating the alternating dielectric stack vertically to expose at least a portion of the substrate. A first mask can be formed to cover the channel holes in a first area and expose the channel holes in a second area. The method also includes forming a recess in the alternating dielectric stack in the second area, followed by forming a second mask in the recess. The second mask covers the channel holes in the second area and exposes the channel holes in the first area. The memory film at bottom of each channel hole in the first area can therefore be removed, while the memory film in the second area can be protected by the second mask.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: September 27, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Feng Lu, Jing Gao, Wenbin Zhou
  • Patent number: 11456181
    Abstract: A first mask layer is formed on top of a semiconductor substrate. A mandrel material is formed perpendicular to the first mask layer. A second mask layer is formed on one or more exposed surfaces of the mandrel material. The mandrel material is removed. A pattern of the first mask layer and the second mask layer is transferred into the semiconductor substrate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chanro Park, Ruilong Xie, Juntao Li
  • Patent number: 11456308
    Abstract: A circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek, Takashi Ando, Nanbo Gong
  • Patent number: 11437388
    Abstract: A semiconductor memory device includes a substrate, a first stack, a plurality of first columnar portions, a second stack, a plurality of second columnar portions, and a third stack. In the first stack, first conductive layers and first insulating layers are alternately stacked in a thickness direction of the substrate. Each of the plurality of first pillars extends inside the first stack in the thickness direction. In the second stack, second conductive layers and second insulating layers are alternately stacked in the thickness direction. Each of the plurality of second pillars extends inside the second stack in the thickness direction. The third stack is positioned between the first stack and the second stack in the first direction. In the third stack, third insulating layers and fourth insulating layers including a material different from a material of the third insulating layer are alternately stacked in the thickness direction of the substrate.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: September 6, 2022
    Assignee: Kioxia Corporation
    Inventors: Kosei Noda, Go Oike
  • Patent number: 11430808
    Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungmin Song, Beyounghyun Koh, Yongjin Kwon, Kangmin Kim, Jaehoon Shin, JoongShik Shin, Sungsoo Ahn, Seunghwan Lee
  • Patent number: 11424259
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 23, 2022
    Inventors: Euntaek Jung, Joongshik Shin
  • Patent number: 11417730
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov, Kamal M. Karda, Michael Mutch, Hung-Wei Liu, Jeffery B. Hull
  • Patent number: 11417660
    Abstract: A semiconductor device includes a stacked line structure including a bit line over a substrate, an active layer positioned at a higher level than the stacked line structure and parallel to the bit line, a capacitor positioned at a higher level than the active layer, a first plug extending downwardly to be coupled to the bit line through the active layer, a second plug formed between the active layer and the capacitor, and a word line extending in a direction that intersects with the bit line while intersecting with the active layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung-Jin Park
  • Patent number: 11404284
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 2, 2022
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Patent number: 11380791
    Abstract: A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Hyun-Seung Song, Hyo-Jin Kim, Kyoung-Mi Park, Hwi-Chan Jun, Seung-Seok Ha
  • Patent number: 11380711
    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: July 5, 2022
    Inventors: Sohyeon Lee, Sungsu Moon, Jaeduk Lee, Ikhyung Joo
  • Patent number: 11374017
    Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 28, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kohji Kanamori, Seogoo Kang, Jongseon Ahn, Jeehoon Han
  • Patent number: 11374019
    Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 28, 2022
    Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
  • Patent number: 11362210
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, an insulating part, a conductive part, and a gate electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating part is provided on the first electrode. The conductive part is provided in the insulating part and is arranged with the first semiconductor region. The gate electrode is provided in the insulating part. The gate electrode is positioned above the conductive part and is arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and the insulating part, and is electrically connected to the third semiconductor region.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 14, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenya Kobayashi
  • Patent number: 11362042
    Abstract: A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 14, 2022
    Assignee: IceMos Technology Corporation
    Inventors: Kiraneswar Muthuseenu, Samuel Anderson, Takeshi Ishiguro
  • Patent number: 11355388
    Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan-Jhi Huang, Yu-Yu Chen
  • Patent number: 11355644
    Abstract: A method of forming a semiconductor device is provided that includes forming a first source/drain region in a supporting substrate abutting a fin structure; and forming an isolation region in the supporting substrate adjacent to a first side of the fin structure, wherein the first source/drain region is positioned on an opposing second side of the fin structure. A gate structure is formed on the channel region portion of the fin structure. In a following step, a second source/drain region on an upper surface of the fin structure. Contacts can be formed aligned to the first source/drain region and the gate structure.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Juntao Li, Kangguo Cheng
  • Patent number: 11348920
    Abstract: A semiconductor device includes a first source/drain structure, a channel layer, a second source/drain structure, a gate structure and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on opposite first and second sidewalls of the channel layer when viewed in a first cross-section taken along a first direction. The gate structure is also on a third sidewall of the channel layer but absent from a fourth sidewall of the channel layer when viewed in a second cross-section taken along a second direction different from the first direction. The epitaxial layer is on the fourth sidewall of the channel layer when viewed in the second cross-section and forming a P-N junction with the channel layer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 11335803
    Abstract: The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 17, 2022
    Inventors: Chiao-Shun Chuang, Che-Yung Lin
  • Patent number: 11335769
    Abstract: A semiconductor device includes a semiconductor part, a terminal insulating film, a first protective film, a second electrode, a terminal electrode, a first insulating film, and a second protective film. The terminal insulating film is provided on the semiconductor part in the terminal region. The first protective film is provided on the terminal insulating film. The first and second protective films includes silicon and nitrogen. The second electrode is provided on the semiconductor part in the cell region and includes an end portion located on the first protective film. The terminal electrode is provided on the first protective film in the terminal region and is connected to the semiconductor part. The first insulating film is provided on the first protective film. The first insulating film includes hydrogen and contacts the second electrode and the terminal electrode. The second protective film covers the first insulating film.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: May 17, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kenichi Matsushita, Tatsuya Ohguro
  • Patent number: 11335825
    Abstract: A single-photon avalanche diode (SPAD) is disclosed. In one aspect, the SPAD comprises an inner doped region, a geometrical structure of a boundary of the inner doped region rotationally symmetric in a horizontal direction of a substrate; at least one outer doped region connected to a second terminal, the at least one outer doped region arranged to at least partially enclose the inner doped region and the outer doped region comprising dopant implantations of a different type than the inner doped region; a lowly doped depletion volume arranged to surround the inner doped region, a depth of the lowly doped depletion volume extending from the top surface of the substrate into the substrate being larger than a depth of the at least one outer doped region, and when a reverse bias is applied to an anode, an electric field peak around the inner doped region being formed to enable impact ionization and multiplication of charges.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 17, 2022
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventor: Edward Van Sieleghem
  • Patent number: 11309426
    Abstract: An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: April 19, 2022
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 11309288
    Abstract: The present disclosure provides a device die, a die assembly and an electronic system. The device die includes a package and a plurality of transfer pads disposed on a functional surface of the package. The transfer pads are divided into a plurality of segments electrically isolated from each other. In an adjacent pair of transfer pads, there is only one electrical connection between the transfer pads, comprising one segment in one transfer pad electrically connected to one segment in the other transfer pad. The die assembly includes a pair of device dies stacked in a stepped configuration. The electronic system includes a supporting member having at least one metallic layer, and a plurality of device dies disposed on the supporting member and mechanically and electrically coupled to the metallic layer by a plurality of conductive strings.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11296113
    Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kwang-Ho Kim, Peter Rabkin
  • Patent number: 11289429
    Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. Divider trenches and slit trenches are formed such that the divider trenches laterally extend along a first horizontal direction and divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers, and the slit trenches laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction. The sacrificial material layers are replaced with electrically conductive layers employing the divider trenches as a conduit for an etchant and for a reactant. Each of the divider trenches and the slit trenches are filled with material portions to provide a plurality of divider trench fill structures in the divider trenches and to provide a plurality of slit trench fill structures in the slit trenches.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 29, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Kazuma Shimamoto
  • Patent number: 11289595
    Abstract: A power semiconductor device includes: a semiconductor body having a front side surface and a drift region having first conductivity type dopants; and an edge termination region that includes a part of the drift region and a first semiconductor region extending along the front side surface. The first semiconductor region includes dopants of both conductivity types and forms a continuous pn-junction with the drift region. An integrated vertical dopant concentration of the second conductivity type dopants is higher than an integrated vertical dopant concentration of the first conductivity type dopants within the first semiconductor region.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: March 29, 2022
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Frank Dieter Pfirsch