Gate Controls Vertical Charge Flow Portion Of Channel (e.g., Vmos Device) Patents (Class 257/329)
  • Patent number: 10355031
    Abstract: A method for manufacturing an array substrate includes forming a buffer layer on a substrate; forming a source and a data line in the buffer layer, forming a first gate, a second gate, a first scan line, and a second scan line on the buffer layer, simultaneously; forming a semiconductor layer; forming a conductor layer by converting the semiconductor layer formed on the first scan line and the second scan line into a conductor; forming a first pixel electrode on the semiconductor layer and forming a second pixel electrode on the conductor layer, simultaneously.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 16, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhichao Zhou
  • Patent number: 10355058
    Abstract: A display device includes a plurality of first detection electrodes that are respectively disposed in a plurality of first areas, which are shaped in a stripe pattern and extend in the first direction, and extend in a first direction, an insulating layer that is disposed in a grid-like area, covers the first detection electrodes, and is placed on perimeters of pixel electrodes, and a plurality of second detection electrodes that are disposed on a sealing layer along a plurality of second areas and extend in a second direction, the second areas being included in the grid-like area, shaped in a stripe pattern, and extending in the second direction. The common electrodes are respectively disposed on a plurality of second banks and continue to the first direction.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Japan Display Inc.
    Inventors: Mitsuhide Miyamoto, Hayato Kurasawa, Hiroshi Mizuhashi, Takayuki Nakanishi, Shuji Hayashi, Yoshitoshi Kida
  • Patent number: 10347745
    Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Puneet Harischandra Suvarna, Steven J. Bentley, Daniel Chanemougame
  • Patent number: 10347639
    Abstract: Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shingo Ujihara, Hiroaki Taketani
  • Patent number: 10340293
    Abstract: A transistor display panel includes a substrate, a gate line disposed on the substrate, a data line disposed on the substrate, and a transistor disposed on the substrate. The transistor includes a first electrode, a second electrode overlapping the first electrode, a semiconductor layer disposed between the first electrode and the second electrode, and a gate electrode. The semiconductor layer is disposed in an overlapping region where the gate line and the data line overlap each other.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung-Hun Noh, Hyun Sup Lee, Sang-Hee Jang, Hyung-Il Jeon, Byung Seok Choi
  • Patent number: 10340184
    Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 2, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10332983
    Abstract: Vertical field-effect transistors are fabricated while controlling gate length by causing enhanced oxidation of silicon germanium regions on parallel semiconductor fin channel regions. Oxidation of the silicon germanium region is accompanied by volume expansion and condensation. Shared or non-shared gate structures are formed on the sidewalls of the semiconductor fin channel regions. A dielectric liner may be incorporated with self-aligned oxide regions to form a composite spacer for providing electrical isolation of the top source/drain regions.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10325989
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 10312346
    Abstract: A method includes forming a plurality of fins on a substrate. The method further includes forming a plurality of deep trenches in the substrate and interposed between each fin of the plurality of fins. The method further includes forming a doped semiconductor layer having a uniform thickness, wherein the doped semiconductor layer is formed prior to removing any fins of the plurality of fins.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bassem M. Hamieh, Stuart A. Sieg, Junli Wang
  • Patent number: 10311945
    Abstract: A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a silicide layer formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 4, 2019
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Masamichi Asano
  • Patent number: 10304955
    Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10297507
    Abstract: A vertical FET structure includes a bottom source-drain region disposed on a substrate of the first type; a recessed first heterostructure layer disposed on the bottom source-drain region; a first fin disposed on the bottom source-drain region; a dielectric inner spacer disposed on the recessed first heterostructure; an outer spacer disposed on the inner spacer; a high-k and metal gate layer disposed on the outer spacer, the inner spacer, and the channel layer; an interlayer dielectric oxide disposed between the first fin and the outer spacer; a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer; a dielectric inner spacer disposed on the recessed second heterostructure layer; and a top source-drain region layer disposed on the dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET. A method for forming the vertical FET is also provided.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shogo Mochizuki, Tenko Yamashita, Chen Zhang
  • Patent number: 10297513
    Abstract: The present invention provides stacked VFET devices. In one aspect, a method of forming a stacked VFET device includes: patterning a fin(s) in a wafer having a vertical fin channel of a VFET1 separated from a vertical fin channel of a VFET2 by an insulator; forming a bottom source and drain of the VFET1 below the vertical fin channel of the VFET1; forming a gate of the VFET1 alongside the vertical fin channel of the VFET1; forming a gate of the VFET2 alongside the vertical fin channel of the VFET2; forming a top source and drain of the VFET1 above the vertical fin channel of the VFET1; forming a bottom source and drain of the VFET2 below the vertical fin channel of the VFET2; and forming a top source and drain of the VFET2 above the vertical fin channel of the VFET2. A stacked VFET device is also provided.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Chen Zhang
  • Patent number: 10297636
    Abstract: A method of fabricating an image sensor includes implanting a first dopant in a substrate, removing a portion of the substrate to define a protrusion, forming a conductive feature over the protrusion, and implanting a second dopant in the protrusion. The removal of the portion of the substrate defines a first surface surrounding the protrusion. The second dopant has a same conductivity type as the first dopant.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 10297660
    Abstract: A semiconductor device includes: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having an impurity concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; an accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having an impurity concentration higher than the drift region; and a plurality of trench sections provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate and provided with a conductive section therein. A length of the accumulation region in a depth direction of the semiconductor substrate is less than 1.5 ?m.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10297594
    Abstract: A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 21, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Jongoh Kim, Hong Chang
  • Patent number: 10297598
    Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul Jamison, Choonghyun Lee, Vijay Narayanan
  • Patent number: 10297491
    Abstract: A structure of a semiconductor includes an isolation structure in a well of a substrate. An upper surface of the isolation structure in the well of the substrate is lower than an upper surface of the substrate and an upper surface of the well. A gate electrode has a first portion over the isolation structure, and a second portion laterally adjacent to the first portion, and above the first portion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Chou, Kong-Beng Thei
  • Patent number: 10283414
    Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Chih-Sheng Chang, Cheng-Hsien Wu
  • Patent number: 10283621
    Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Hui Zang, Steven Bentley
  • Patent number: 10283416
    Abstract: A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10283620
    Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee
  • Patent number: 10276717
    Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhiqiang Wu, Yi-Ming Sheu, Tzer-Min Shen, Chun-Fu Cheng, Hong-Shen Chen
  • Patent number: 10269802
    Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Han Lin
  • Patent number: 10269867
    Abstract: A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 23, 2019
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Patent number: 10263070
    Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: April 16, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yi Su, Sik Lui
  • Patent number: 10262994
    Abstract: A FinFET semiconductor device having semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region. The device includes a plurality of fins attached to the semiconductor body and extending across the semiconductor body, a channel gate disposed over a section of the plurality of fins; a supplemental gate disposed on the drain-region STI.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 16, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Qing Liu, Akira Ito
  • Patent number: 10263082
    Abstract: A gate trench of a MOS gate formed in the front surface of a silicon carbide substrate includes a first portion that includes the bottom surface of the gate trench, a second portion that is connected to the substrate front surface side of the first portion, and a third portion that is connected to the substrate front surface side of the second portion. In the third portion of the gate trench, an n+ source region is exposed along the sidewalls. The width of the third portion of the gate trench is greater than the widths of the first and second portions and of the gate trench. Upper corners of the gate trench smoothly connect the sidewalls to the substrate front surface. The thickness of a gate insulating film smoothly connected along the bottom surface and sidewalls of the gate trench is substantially uniform over the entire inner wall surface of the gate trench.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Akimasa Kinoshita
  • Patent number: 10256351
    Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 9, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10256235
    Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10249753
    Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre, Junli Wang
  • Patent number: 10243001
    Abstract: There is provided a semiconductor device. The semiconductor device includes a source layer, a well pickup layer formed on the source layer, a body structure formed on the well pickup layer and including a well region contacting the well pickup layer and first junctions formed on side walls of the body structure, channel pillars contacting the body structure and protruding from the body structure, and contact layers formed on the side walls of the body structure and electrically connecting the body structure and the well pickup layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: March 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10242907
    Abstract: A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 26, 2019
    Assignee: IMEC vzw
    Inventors: Julien Ryckaert, Juergen Boemmels, Christopher Wilson
  • Patent number: 10236211
    Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jung Yun, Joon-Hee Lee, Seong-Soon Cho
  • Patent number: 10236271
    Abstract: It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukie Suzuki, Yasuyuki Arai, Shunpei Yamazaki
  • Patent number: 10236351
    Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a trench extending into the semiconductor body along an extension direction and including an insulator; providing a monolithic electrode zone within the trench; and removing a section of the monolithic electrode zone within the trench to divide the monolithic electrode zone into at least a first electrode structure and a second electrode structure arranged separately and electrically insulated from each other.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Michael Hutzler
  • Patent number: 10230000
    Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Emilie Bourjot, Daniel Chanemougame, Tek Po Rinus Lee, Ruilong Xie, Hui Zang
  • Patent number: 10224250
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 5, 2019
    Assignee: IMEC vzw
    Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
  • Patent number: 10224406
    Abstract: A TFT array substrate includes a glass substrate, a buffer layer on the glass substrate, a source electrode, a passivation layer on the buffer layer, a gate electrode on the passivation layer, a gate insulating layer on the passivation layer and the gate electrode, an active layer, and a pixel electrode on the gate insulating layer and the active layer. A first source hole is formed in the buffer layer. The source electrode is disposed in the first source hole. A second source hole is formed in the passivation layer and over the first source hole. The source electrode extends into the second source hole. An active layer mounting hole is formed in the gate insulating layer and over the second source hole. The active layer is in the active layer mounting hole.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 5, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhichao Zhou, Yulien Chou, Yue Wu
  • Patent number: 10211315
    Abstract: Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Haigou Huang
  • Patent number: 10211288
    Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Zheng Xu
  • Patent number: 10211331
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Ichijo, Syotaro Ono, Masahiro Shimura, Hideyuki Ura, Hiroaki Yamashita
  • Patent number: 10199490
    Abstract: A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure. Corresponding methods for forming the semiconductor device are also described.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Adrian Finney, Radu Eugen Cazimirovici, Dietmar Kotz, Thomas Ostermann
  • Patent number: 10192789
    Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 29, 2019
    Assignee: SPIN TRANSFER TECHNOLOGIES
    Inventors: Gian Sharma, Amitay Levi, Kuk-Hwan Kim
  • Patent number: 10192824
    Abstract: An edge structure for multiple layers of devices including stacked multiple unit layers includes first and second stair structures. The first stair structure is at a first direction of the devices where device contacts are formed, including first edge portions of the unit layers at the first direction, of which the borders gradually retreat with increase of level height. The elevation angle from the border of the first edge portion of the bottom unit layer to that of the top one is a first angle. The second stair structure includes second edge portions of the unit layers at a second direction. The variation of border position of the second edge portion with increase of level height is irregular. The elevation angle from the border of the second edge portion of the bottom unit layer to that of the top one is a second angle larger than the first angle.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: January 29, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 10192787
    Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 29, 2019
    Assignee: SPIN TRANSFER TECHNOLOGIES
    Inventors: Gian Sharma, Amitay Levi, Kuk-Hwan Kim
  • Patent number: 10192788
    Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 29, 2019
    Assignee: SPIN TRANSFER TECHNOLOGIES
    Inventors: Gian Sharma, Amitay Levi, Kuk-Hwan Kim
  • Patent number: 10177044
    Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: January 8, 2019
    Assignee: Newport Fab, LLC
    Inventors: Edward J. Preisler, Marco Racanelli, Paul D. Hurwitz
  • Patent number: 10177218
    Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 8, 2019
    Assignee: STIMICROELECTRONICS (TOURS) SAS
    Inventors: Frédéric Lanois, Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 10170492
    Abstract: A memory device includes a semiconductor substrate, a first conductive layer, a plurality of second conductive layers, a plurality insulating layers, at least one contact plug and at least one dummy plug. The first conductive layer is disposed on the semiconductor substrate. The insulating layers are disposed on the first conductive layer. The second conductive layers are alternatively stacked with the insulating layers and insulated from the first conductive layer. The contact plug passes through the insulating layers and the second conductive layers, insulates from the second conductive layers and electrically contacts to the first conductive layer. The dummy plug, corresponds to the at least one contact plug, passes through the insulating layers and the second conductive layers, and insulates from the second conductive layers and the first conductive layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: January 1, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ting-Feng Liao, Yi-Chen Wang