SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE
A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.
This application is a continuation of U.S. application Ser. No. 13/733,936 filed on Jan. 4, 2013, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0051036 filed on May 14, 2012 in the Korean Intellectual Property Office, and the disclosure of which is incorporated by reference herein in its entirety.
TECHNICAL FIELDThe inventive concept relates to a semiconductor device and a method for manufacturing the device.
DESCRIPTION OF THE RELATED ARTMetal-oxide-semiconductor (MOS) transistors using polysilicon gate electrodes are widely known. Polysilicon gate electrodes may be annealed at a high temperature with source and drain regions. Polysilicon gate electrodes may also serve as ion implantation masks when source and drain regions are formed.
As transistors shrink, resistance of polysilicon electrodes increases, which prevents transistors from operating at high speed. Recently, integrated structures of a high dielectric constant gate oxide and a metal gate has been proposed. The introduction of new materials may cause other problems such as incompatibility of metal gates with high temperature processes and work function controls of the integrated structures. Accordingly, there is a need for an improved process for integrating a high dielectric constant gate oxide and a metal gate.
SUMMARYAccording to an exemplary embodiment of the inventive concept, a semiconductor device comprises a N-type field effect transistor including a first high dielectric constant (high-k) layer disposed on a substrate. A diffusion layer including a metal oxide is disposed on the first high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer.
According to an exemplary embodiment of the inventive concept, a static random access memory (SRAM) device comprises a N-type field effect transistor and a P-type field effect transistor. The N-type field effect transistor comprises a high dielectric constant (high-k) layer disposed on a substrate. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The P-type field effect transistor comprises the high-k layer disposed on the substrate.
According to an exemplary embodiment of the inventive concept, a semiconductor device comprises a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.
According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device comprises a step where a first trench and a second trench are formed in a substrate and defined by spacers formed on a substrate. A high-k layer is formed in the first and the second trenches. A diffusion layer is formed on the high-k layer of the first trench which includes a metal oxide. A passivation layer is formed on the diffusion layer for preventing the diffusion layer from being oxidized. Metal atoms of the metal oxide are diffused into the high-k layer of the first trench and the substrate under the first trench by thermally heating the substrate. A first metal gate is formed on the passivation layer formed in the first trench.
The above and other aspects and features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings of which:
Exemplary embodiments of the inventive concept will be described below in more detail with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on” another element or layer, it may be directly on the other layer or intervening layers may be present. Like numbers may refer to like elements throughout.
Referring to
Each of the first and second regions NFET and PFET may include a channel region C and source/drain regions 101 and 102. Here, the channel region C of the first region NFET may be a N-channel region through which N-type carriers of the source/drain regions 101 move, and the channel region C of the second region PFET may be a P-channel region through which P-type carriers of the source/drain regions 102 move. An isolation (not shown) may be formed the outside of the source and drain regions 101 and 102 in the semiconductor substrate 100 to isolate the NFET and the PFET.
The NFET may include a first trench 111. The first trench 111 may be surrounded by spacers 120 disposed on the channel region C of NFET, and an interlayer insulating layer 110 may be formed on the outside of the spacers 120. In some embodiments of the inventive concept, the NFET may include a tensile stress layer (not shown) on the source/drain regions 101 for providing tensile stress to the channel region C of the NFET. In an embodiment according to the inventive concept, the shape of the spacers 120 may have an L shape.
An interface layer 125, a first high dielectric constant (high-k) layer 131, a diffusion layer 140, a passivation layer 150, and a first metal gate 161 may be sequentially disposed in the first trench 111. In this case, the first high-k layer 131, the diffusion layer 140, the passivation layer 150 and the first metal gate 161 may be configured to extend upward along the sidewall of the first trench 111 as shown in
The interface layer 125 may serve to prevent a defect interface between the semiconductor substrate 100 and the first high-k layer 131. The interface layer 125 may include a low-k material layer whose dielectric constant (k) is equal to or less than about 9. For example, the interface layer 125 may include a silicon oxide layer (k is about 4) or a silicon oxynitride layer (k is about 4 to 8 according to the content of oxygen atoms and nitrogen atoms). In an embodiment of the inventive concept, the interface layer 125 may be formed of silicate, or may be formed of a combination of the above illustrated layers.
The first high-k layer 131 having a dielectric constant equal to or more than about 10 may be disposed on the interface layer 125. In some embodiments of the inventive concept, the first high-k layer 131 may be formed of, e.g., HfO2, Al2O3, ZrO2, TaO2 or the like, but the inventive concept is not limited thereto.
The diffusion layer 140 may be formed on the first high-k layer 131. In this embodiment, the diffusion layer 140 may be, e.g., a metal oxide layer. For example, the diffusion layer 140 may be formed of LaO, Y2O3, Lu2O3, SrO or a combination thereof, but the inventive concept is not limited thereto. A material (e.g., metal) included in the diffusion layer 140 is diffused into the channel region C of the NFET so that a work function of the NFET may be adjusted. Accordingly, it is possible to improve the performance of the NFET.
Further, the material (e.g., metal) included in the diffusion layer 140 may be diffused into the first high-k layer 131 disposed under the diffusion layer 140. Accordingly, the dielectric constant of the first high-k layer 131 may increase to reduce the gate leakage current of the NFET. Meanwhile, the diffusion layer 140 may prevent metal atoms of the first metal gate 161 from infiltrating into the first high-k layer 131, thereby contributing to improvement of the performance of the NFET. This function of the diffusion layer 140 according to inventive concept will be described in detail later in explaining a method for manufacturing the semiconductor device according to the inventive concept.
In some embodiments of the inventive concept, the diffusion layer 140 may be formed on the first high-k layer 131 to have a first thickness. Here, the first thickness may be about 3 to about 10 Å, but the inventive concept is not limited thereto.
The passivation layer 150 may be disposed on the diffusion layer 140. The passivation layer 150 may prevent the diffusion layer 140 from being oxidized in a manufacturing process to be described later. In this embodiment, the passivation layer 150 may be formed of a metal nitride layer. For example, the passivation layer 150 may be formed of at least one of TiN and TaN. In an embodiment of the inventive concept, the passivation layer 150 may be formed of a single layer of TiN, a double layer including a lower layer of TiN and an upper layer of TaN, or the like, but the inventive concept is not limited thereto.
In some embodiments of the inventive concept, the passivation layer 150 may be formed to have a second thickness larger than a first thickness of the diffusion layer 140. For example, the passivation layer 150 may be formed to have a thickness of about 11 to about 70 Å, but the inventive concept is not limited thereto.
The first metal gate 161 may be disposed on the passivation layer 150. The first metal gate 161 may have a single layer structure formed of a metal layer or a multilayer layer structure formed of a metal nitride layer and a metal layer. The metal layer of the first metal gate 161 may be, e.g., Al, W, Ti or a combination thereof, and the metal nitride of the first metal gate 161 may be TiN, TaN or a combination thereof, but the inventive concept is not limited thereto. In this embodiment, the first metal gate 161 may be formed by using a replacement metal gate (RMG) process. This will be described in detail later in explaining a method for manufacturing the semiconductor device according to an embodiment of the inventive concept.
In some embodiments of the inventive concept, the first metal gate 161 may include an N-type work function layer. The N-type work function layer may be formed of, e.g., TiAl, TiAlN, TaC, TaAlN, TiC, HfSi or the like, but the inventive concept is not limited thereto. The N-type work function layer may be formed to have a thickness of about 30 to about 120 Å, but the inventive concept is not limited thereto.
The PFET may include a second trench 112 disposed on the channel region C of the PFET. Specifically, the second trench 112 may be surrounded by the spacers 120. The interlayer insulating layer 110 may be disposed on the outside of the spacers 120. In some embodiments of the inventive concept, the PFET may include a compressive stress layer (not shown) on the substrate the source/drain regions 102. In an embodiment of the inventive concept, the spacers 120 may have an L shape.
The PFET may include the interface layer 125, a second high dielectric constant (high-k) layer 132, and a second metal gate 162. The layers 125, 132, and 162 may be sequentially disposed in the second trench 112. The second high-k layer 132 and the second metal gate 162 may extend upward along the sidewall of the second trench 112 as shown in
The second metal gate 162 may be disposed on the second high-k layer 132. The second metal gate 162 may have a single layer structure formed of a metal layer or a multilayer metal layer including a metal nitride layer and a metal layer.
In some embodiments of the inventive concept, the PFET may include the second metal gate 162 which is different from that of the NFET. For example, the first metal gate 161 may include a metal gate having four layers of TiAl/TiN/Ti/Al, and the second metal gate 162 may include a metal gate having four layers of TiN/TaN/TiN/Al, but the inventive concept is not limited thereto.
In some embodiments of the inventive concept, the second metal gate 162 may include a P-type work function layer. The P-type work function layer may be formed to have a thickness of about 50 to about 100 Å, but the inventive concept is not limited thereto.
In some embodiments of the inventive concept, the second metal gate 162 may include both a lower P-type work function layer and an upper N-type work function layer.
Connection wirings (not shown) may electrically connect contacts (not shown) to the NFET and the PFET through the interlayer insulating layer 110.
As described above, the NFET may include the diffusion layer 140 according to embodiments of the inventive concept to improve the performance of the NFET. The PFET may include the P-type work function layer to improve the performance of the PFET.
Hereinafter, an exemplary method for manufacturing the semiconductor device of
First, referring to
Next, referring to
Next, referring to
Subsequently, the high-k layer 130, the diffusion layer 140 and the passivation layer 150 are sequentially formed in the first and second trenches 111 and 112. In this embodiment, the diffusion layer 140 may be formed a metal oxide layer, and the passivation layer 150 may be formed of a metal nitride layer. For example, the diffusion layer 140 may be formed of LaO and the passivation layer 150 may be formed of TiN. In some embodiments, the diffusion layer 140 may be formed of LaO, Y2O3, Lu2O3, SrO or a combination thereof, and the passivation layer 150 may be formed of TiN, TaN or a combination thereof.
The diffusion layer 140 may have a thickness of about 3 to 10 Å. The diffusion layer 140 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or the like. The passivation layer 150 may have a thickness of about 11 to 70 Å using CVD, ALD or the like.
Next, referring to
Then, the semiconductor substrate 100 is thermally treated. In such thermal treatment, the metal of the diffusion layer 140 formed in the first trench 111 may be diffused into the channel region C of the NFET and the high-k layer 130 formed in the first trench 111. For example, when the diffusion layer 140 is formed of LaO, the La atoms are diffused out of the diffusion layer 140 to the channel region of C and the high-k layer 130 in the first region NFET. Meanwhile, since the diffusion layer 140 is not formed in the second trench 112, the channel region C of the PFET and the high-k layer 130 formed in the second trench 112 are not influenced by the diffusion layer 140 in the thermal treatment.
As described above, the atoms of the diffusion layer 140 diffused into the high-k layer 130 formed in the first trench 111 may increase the dielectric constant of the high-k layer 130 formed in the first trench 111. Further, the La atoms of the diffusion layer 140 diffused into the channel region C of the NFET may adjust a work function of the NFET to improve the performance of the NFET. The metal atoms diffused may not be limited to La atoms, but when the diffusion layer 140 is formed of other metal oxides layer, other metal atoms included in the metal oxides layer may be diffused in the thermal treatment.
In an exemplary embodiment of the inventive concept, the passivation layer 150 may prevent the diffusion layer 140 from being oxidized in the thermal treatment. When the polysilicon layer 135 is formed on the passivation layer 150, the passivation layer 150 may serve to prevent the diffusion film 140 from being oxidized from oxygens which may diffuse through the polysilicon film 135 in the thermal treatment.
Next, the polysilicon layer 135 formed on the first region NFET of the semiconductor substrate 100 is removed by ashing or the like. Then, TiAl, TiN, Ti and Al layers are sequentially formed on the passivation layer 150. Using an Al CMP process, the first metal gate 161 shown in
The second metal gate of
After the formation of the first and second metal gates 161 and 162 is completed, connection wirings may be formed. The connection wirings may connect contacts to the NFET and the PFET through the interlayer insulating layer 110.
Hereinafter, a method for manufacturing the semiconductor device of
As shown in
Referring to
Then, the semiconductor substrate 100 is thermally treated. While the semiconductor substrate 100 is thermally treated, the material (e.g., metal) included in the diffusion layer 140 formed in the first trench 111 may be diffused into the channel region C of the NFET and the high-k layer 130 formed in the first trench 111.
At this time, since the polysilicon layer 135 of
Then, since forming the first metal gate 161 in the first trench 111 and forming the second metal gate 162 in the second trench 112 are the same as described above, further description will be omitted.
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Referring to
The diffusion barrier layer 170 may be formed to extend upward along the sidewall of the second trench 112 as shown in
In some embodiments of inventive concept, the diffusion barrier layer 170 may include a P-type work function layer. A metal nitride layer may be mentioned as an example of the diffusion barrier layer 170. Specifically, the diffusion barrier layer 170 may be formed of, e.g., TiN, but the inventive concept is not limited thereto. Further, in some other embodiments of the inventive concept, the diffusion barrier layer 170 may have a double layer structure including a metal nitride layer and a metal layer. Specifically, the diffusion barrier layer 170 may have a double layer structure including, e.g., TiN and Al, but the inventive concept is not limited thereto. In some other embodiments of the inventive concept, the diffusion barrier layer 170 may have a three-layer layer structure including, e.g., a first metal nitride layer, a metal layer and a second metal nitride layer. Specifically, the diffusion barrier layer 170 may have a three-layer layer structure including, e.g., TiN, Al and TiN, but the inventive concept is not limited thereto. The diffusion barrier layer 170 may have a thickness of, e.g., 1 to 100 Å, but the inventive concept is not limited thereto.
Hereinafter, a method for manufacturing the semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described.
First, as shown in
Then, referring to
In an exemplary embodiment of the inventive concept, the diffusion barrier layer 170 may include a P-type work function layer. For example, the diffusion barrier layer 170 may be formed of TiN, but the inventive concept is not limited thereto.
In an embodiment of the inventive concept, the diffusion barrier layer 170 may have a double layer structure including a metal nitride layer and a metal layer. For example, the metal nitride layer is formed of TiN and the metal layer is formed of Al, but the inventive concept is not limited thereto.
In an embodiment of the inventive concept, the diffusion barrier layer 170 may have a three-layer structure including a first metal nitride layer, a metal layer and a second metal nitride layer. For example, the first and the second metal nitrides are formed of TiN, and the metal is formed of Al, but the inventive concept is not limited thereto. The diffusion barrier layer 170 may have a thickness of about 1 to 100 Å, but the inventive concept is not limited thereto.
Then, after masking the second region PFET of the semiconductor substrate 100, the diffusion barrier layer 170 formed on the first region NFET of the semiconductor substrate 100 is selectively removed. As a result, the diffusion barrier layer 170 may exist in the second trench 112, but may not exist in the first trench 111.
Then, referring to
Then, referring to
Then, referring to
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Referring to
The cobalt layer 175 may be formed on the passivation layer 150 by CVD or the like. In this case, the thickness of the cobalt layer 175 may be about 1 to 20 Å, but the inventive concept is not limited thereto.
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Referring to
The U shape diffusion barrier layer 170 may improve the metal-fill characteristics of a metal gate 162 because the metal gate 162 is formed in the trench 112. to be formed on the diffusion barrier layer 170. Accordingly, since the metal-fill characteristics are improved when the second metal gate 162 is formed on the diffusion barrier layer 170 as illustrated, the second metal gate 162 may be formed more reliably in the second trench 112.
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Referring to
The fin F1 may extend in a second direction Y1. The fin F1 may be a portion of a substrate 200 and may include an epitaxial layer grown from the substrate 200. An isolation 201 may cover the side surface of the fin F1.
The gate electrode 222 may be disposed on the fin F1, extending in a first direction X1. The gate electrode 222 formed on the first high-k layer 131 and the interface layer 125 may include the diffusion layer 140, the passivation layer 150, and the first metal gate 161.
The recess 225 may be formed in a first interlayer insulating layer 202 at both sides of the gate electrode 222. The sidewall of the recess 225 is inclined and the shape of the recess 225 may be widened as it goes farther away from the substrate 100. Meanwhile, as shown in
The source/drain 261 may be formed in the recess 225. The source/drain 261 may have an elevated shape. For example, the upper surface of the source/drain 261 may be higher than the upper surface of the isolation 201. Further, the source/drain 261 and the gate electrode 222 may be isolated from each other by the spacers 120.
The source/drain 261 may include the same material as that of the substrate 200. For example, when the substrate 200 includes Si, the source/drain 261 may be formed of Si. In an embodiment, the source/drain 261 of the NFET may be formed of a material having tensile stress for NFET. For example, when the substrate 200 includes Si, the source/drain 261 may include SiC having a lattice constant smaller than that of Si. The tensile stress may improve the mobility of carriers of the channel region of the fin F1.
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
For the PFET, the source/drain 261 may include a material having compressive stress. For example, the substrate 200 includes Si, the source/drain 261 may be formed of SiGe having a lattice constant larger than that of Si. The compressive stress may improve the mobility of carriers of the channel region of the fin F1.
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Referring to
In an exemplary embodiment of the inventive concept, an SRAM cell of
The first inverter INV1 may include a first load transistor T5 and a first drive transistor T3 which are connected in series. The second inverter INV2 may include a second load transistor T6 and a second drive transistor T4 which are connected in series. Further, the first inverter INV1 and the second inverter INV2 are configured such that the input node of the first inverter INV1 is connected to the output node NC2 of the second inverter INV2 and the input node of the second inverter INV2 is connected to the output node NC1 of the first inverter INV1, thereby forming a latch circuit.
Here, at least one of the first load transistor T5 and the second load transistor T6 may be formed of the P-type field effect transistor (PFET) according to the exemplary embodiments of the inventive concept. Further, at least one of the first transmission transistor T1, the second transmission transistor T2, the first drive transistor T3 and the second drive transistor T4 may be formed of the N-type field effect transistor (NFET) according to the exemplary embodiments of the inventive concept.
In some embodiments of the inventive concept, the peripheral region 400 may include, e.g., an input/output (I/O) region. The peripheral region 400 may be a lower density one than the memory region 300, and distance between transistors larger than that of the memory region 300. The peripheral region 400 may include a logic region 410. Further, a P-type field effect transistor (PFET) according to the embodiments of the inventive concept may be formed in the logic region 410.
For example, the semiconductor device of
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference to
Referring to
In this embodiment, the FETs according to the embodiments of the inventive concept may be formed in the logic regions 610 to 630. For example, the PFET of
Referring to
The memory system 912, the processor 914, the RAM 916 and the user interface 918 may communicate with each other through a bus 920. The processor 914 may control the electronic system 900. The RAM 916 may be used as an operating memory of the processor 914.
For example, the processor 914, the RAM 916 and/or the memory system 912 may include the semiconductor device according to the embodiments of the inventive concept. Further, in some embodiments of the inventive concept, the processor 914 and the RAM 916 may be packaged together in the same package.
The user interface 918 may be used to input/output data to/from the electronic system 900. The memory system 912 may store data processed by the processor 914, or data inputted from the outside. The memory system 912 may include a controller and a memory.
While the inventive concept has been shown and described with reference to exemplary embodiments thereof it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the sprit and scope of the inventive concept as defined by the following claims.
Claims
1. A static random access memory (SRAM) device comprising: a N-type field effect transistor comprising: a high dielectric constant (high-k) layer disposed on a substrate, a diffusion layer including a metal oxide disposed on the high-k layer, a passivation layer disposed on the diffusion layer, and a first metal gate disposed on the passivation layer; and a P-type field effect transistor comprising: the high-k layer disposed on the substrate.
2. The SRAM device of claim 1, wherein the P-type field effect transistor further comprising; a diffusion barrier layer formed on the second high-k layer; the diffusion layer disposed on the diffusion barrier layer; the passivation layer disposed on the diffusion layer; and a second metal gate disposed on the passivation layer, wherein the diffusion barrier layer prevents metal atoms of the diffusion layer from being diffused into the high-k layer.
3. The SRAM device of claim 1, wherein the first metal gate includes a first plurality of conductive layers and the second metal gate includes a second plurality of conductive layers, wherein first plurality of conductive layers include a conductive layer different from that of the second plurality of conductive layers.
4. The SRAM device of claim 1, wherein the N-type field effect transistor and the P-type field effect transistor is configured to be a fin-type transistor.
Type: Application
Filed: Dec 19, 2014
Publication Date: Apr 16, 2015
Inventor: Ju-Youn KIM (Gyeonggi-do)
Application Number: 14/576,268
International Classification: H01L 27/11 (20060101); H01L 29/51 (20060101); H01L 27/092 (20060101);