Complementary Insulated Gate Field Effect Transistors Patents (Class 257/369)
  • Patent number: 10818676
    Abstract: An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10818677
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yangsyu Lin, Chi-Lung Lee, Chien-Chi Tien, Chiting Cheng
  • Patent number: 10811416
    Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: October 20, 2020
    Assignee: SONY CORPORATION
    Inventor: Koichi Matsumoto
  • Patent number: 10811518
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10811413
    Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Reinaldo Vega, Choonghyun Lee, Hari Mallela, Li-Wen Hung
  • Patent number: 10811536
    Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10811253
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 10811405
    Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
  • Patent number: 10804270
    Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10804377
    Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 13, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10804400
    Abstract: This disclosure relates to a semiconductor structure for, e.g., a high-k metal gate fin field-effect transistor, and a manufacturing method therefor. The method may include providing a substrate structure including a first portion for forming a first PMOS device and a second portion for forming a second PMOS device; forming a first P-type work function adjustment layer on the substrate structure; forming a protective layer on the first P-type work function adjustment layer; patterning the protective layer to expose the first P-type work function adjustment layer on the first portion; oxidizing the exposed first P-type work function adjustment layer on the first portion; removing the protective layer; and forming a second P-type work function adjustment layer on the first P-type work function adjustment layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 13, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Xin He
  • Patent number: 10804161
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 10804158
    Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namgyu Cho, Kughwan Kim, Geunwoo Kim, Jungmin Park, Minwoo Song
  • Patent number: 10804257
    Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-young Lee, Jong-hoon Jung, Myoung-ho Kang, Jung-ho Do
  • Patent number: 10790809
    Abstract: An integrated circuit has a CMOS signal path coupled for receiving a data signal. A compensation circuit is coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail. The compensation circuit can be a charge pump operating in response to the data signal to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a voltage regulator and current mirror including an input coupled to the voltage regulator. The replica CMOS signal path receives an operating potential from the voltage regulator. An output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 29, 2020
    Assignee: Semtech Corporation
    Inventor: Jonah Edward Nuttgens
  • Patent number: 10790283
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
  • Patent number: 10784260
    Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongho Park, Wandon Kim, Jeonghyuk Yim, Sangjin Hyun
  • Patent number: 10777463
    Abstract: One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Man Gu, Tao Han
  • Patent number: 10777640
    Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim
  • Patent number: 10777642
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Patent number: 10770353
    Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Wei-E Wang
  • Patent number: 10763863
    Abstract: Structures and methods for the co-optimization of core (logic) devices and SRAM devices include a semiconductor device having a logic portion and a memory portion. In some embodiments, a logic device is disposed within the logic portion. In some cases, the logic device includes a single fin N-type FinFET and a single fin P-type FinFET. In some examples, a static random-access memory (SRAM) device is disposed within the memory portion. The SRAM device includes an N-well region disposed between two P-well regions, where the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and where the N-well region includes a P-type FinFET pull-up (PU) transistor.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10763178
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Patent number: 10756179
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
  • Patent number: 10741668
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bala Haran, Ruilong Xie, Balaji Kannan, Katsunori Onishi, Vimal K. Kamineni
  • Patent number: 10734478
    Abstract: A semiconductor device includes a substrate, a first circuit, and a second circuit. The first circuit is disposed on the substrate and includes a first semiconductor fin and a first gate electrode straddling the first semiconductor fin. The second circuit is different from the first circuit and disposed on the substrate. The second circuit includes a second semiconductor fin and a second gate electrode straddling the second semiconductor fin. A width of the first semiconductor fin is different from a width of the second semiconductor fin.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10734288
    Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Juyoun Kim
  • Patent number: 10734488
    Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Gilbert Dewey
  • Patent number: 10734411
    Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 10727229
    Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; and two fins in a first region of the semiconductor device extending from the substrate and through the isolation structure. Each of the two fins has a channel region and two source/drain (S/D) regions sandwiching the channel region. The semiconductor device further includes a gate stack over the isolation structure and engaging the channel regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. Each of the lower portions of the four S/D features has a cross-sectional profile that is wider at its bottom than at its top. The upper portions of the four S/D features merge into two merged S/D features with one on each side of the gate stack.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu
  • Patent number: 10727231
    Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: July 28, 2020
    Assignees: National Applied Research Laboratories, EPISTAR Corporation
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 10727236
    Abstract: Structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors. A structure includes a first fin, a second fin arranged over the first fin, a first dielectric layer between the first fin and the second fin, and a first inverter. The first inverter includes a first field-effect transistor with a channel region in the first fin and a second field-effect transistor with a channel region in the second fin. The first field-effect transistor and the second field-effect transistor share a first gate structure having an overlapping arrangement with the channel region in the first fin and the channel region in the second fin. The first fin has a longitudinal axis, and the second fin has a longitudinal axis that is aligned at an angle relative to the longitudinal axis of the first fin.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nan Wu, Peter Baars
  • Patent number: 10720436
    Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Kuo-Chiang Ting, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 10707333
    Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Sheng Huang, Hung-Chang Sun, I-Ming Chang, Zi-Wei Fang
  • Patent number: 10707206
    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Patent number: 10699966
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Patent number: 10692925
    Abstract: A method for fabricating a semiconductor device includes forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar, and depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Rizzolo, Theodorus E. Standaert, Isabel Cristina Chu, Chih-Chao Yang, Son Nguyen
  • Patent number: 10692723
    Abstract: A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shuo Hsieh, Shih-Chang Tsai, Chih-Han Lin, Te-Yung Liu
  • Patent number: 10692868
    Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10692779
    Abstract: A method for forming a semiconductor device includes providing a substrate, the substrate including a first trench in an NMOS region and a second trench in a PMOS region. The method also includes depositing a high-K dielectric layer, a cap layer, and a P-type work function metal layer on the bottom and side walls of the first trench and the second trench, removing the P-type work function metal layer and the cap layer from the bottom and sidewalls of the first trench, depositing an N-type work function metal layer on the high-K dielectric layer in the first trench and on the P-type work function metal layer in the second trench, and depositing a metal electrode layer on the N-type work function metal layer.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 23, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10692873
    Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices formed on a substrate. A non-limiting example of the nanosheet FET devices includes a first nanosheet FET having a first channel nanosheet, a second channel nanosheet over the first nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein a first air gap is between the first gate structure and the second gate structure. The nanosheet FET devices further include a second nanosheet FET having a third channel nanosheet, a fourth channel nanosheet over the third nanosheet, a third gate structure around the third channel nanosheet, and a fourth gate structure around the fourth channel nanosheet, wherein a second air gap is between the third gate structure and the fourth gate structure.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Ruqiang Bao, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10685961
    Abstract: A technique relates to fabricating a pFET device and nFET device. A contact trench is formed through an inter-level dielectric layer (ILD) and a spacer layer. The ILD is formed over the spacer layer. The contact trench exposes a p-type source/drain region of the pFET and exposes an n-type source/drain region of the NFET. A gate stack is included within the spacer layer. A p-type alloyed layer is formed on top of the p-type source/drain region in the pFET and on top of the n-type source/drain region of the nFET. The p-type alloyed layer on top of the n-type source/drain region of the nFET is converted into a metallic alloyed layer. A metallic liner layer is formed in the contact trench such that the metallic liner layer is on top of the p-type alloyed layer of the pFET and on top of the metallic alloyed layer of the nFET.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Joseph S. Washington, Tenko Yamashita
  • Patent number: 10686428
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang-Jui Kao, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 10685162
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 10680015
    Abstract: A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hoijin Lee
  • Patent number: 10679997
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
  • Patent number: 10672460
    Abstract: A semiconductor device includes a semiconductor substrate including a fin of semiconductor material having a fin width and a fin length. The fin length is greater than the fin width and extends between a first fin end and a second fin end. A gate electrode extends over the fin at a first fin location between the first fin end and the second fin end. A dummy gate electrode extends over the first fin end.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10672909
    Abstract: A semiconductor device including a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material, a second portion doped with a large species material, and a third portion being undoped by the oxygen-containing material and the large species material.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Shiu-Ko Jangjian, Kun-Tzu Lin, Lan-Fang Chang
  • Patent number: 10665591
    Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 26, 2020
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Kumaraswamy Ramanathan, Damayanti Datta
  • Patent number: 10665512
    Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James Kelly, Balasubramanian Pranatharthiharan