Complementary Insulated Gate Field Effect Transistors Patents (Class 257/369)
  • Patent number: 11145751
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ju Chen, Su-Hao Liu, Chun-Hao Kung, Liang-Yin Chen, Huicheng Chang, Kei-Wei Chen, Hui-Chi Huang, Kao-Feng Liao, Chih-Hung Chen, Jie-Huang Huang, Lun-Kuang Tan, Wei-Ming You
  • Patent number: 11145683
    Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
  • Patent number: 11145512
    Abstract: A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shuo Hsieh, Shih-Chang Tsai, Chih-Han Lin, Te-Yung Liu
  • Patent number: 11145728
    Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11145652
    Abstract: A semiconductor device includes a semiconductor substrate having first and second semiconductor fins, an insulating layer on the semiconductor substrate, the insulating layer including a first recess exposing an upper portion of the first semiconductor fin and a second recess exposing an upper portion of the second semiconductor fin, a gate dielectric layer on the first and second recesses and the exposed upper portions of the first and second semiconductor fins, a first work function adjustment layer on the gate dielectric layer, a functional layer on the first function adjustment layer, and first and second gates on portions of the functional layer of the respective first and second semiconductor fins. The surface area of a lateral opening of the first recess is larger than the surface area of a lateral opening of the second recess.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 12, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yong Li, Jian Hua Xu
  • Patent number: 11145738
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 12, 2021
    Inventors: Jongho Park, Byounghoon Lee, Seungkeun Cha, Wandon Kim
  • Patent number: 11130320
    Abstract: A film including a polyimide-polybenzoxazole copolymer including a repeating unit represented by Chemical Formula 1: wherein in Chemical Formula 1, A1, A1?, A2, A3, m, and n are the same as described in the specification.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Jeong Jeon, Min Sang Kim, Yoon Seok Ko, Byung Hee Sohn
  • Patent number: 11133404
    Abstract: A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The first width is less than the second width. The stem region and the active region also have different compositions. A gate structure is disposed on the active region.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 11133592
    Abstract: A radio frequency module is provided. The module includes a core member, a front-end integrated circuit (FEIC), a first connection member, a second connection member disposed on an upper surface of the core member, a radio frequency integrated circuit (RFIC) disposed on an upper surface of the second connection member, and configured to input or output a base signal and a first radio frequency (RF) signal having a frequency higher than a frequency of the base signal, through a wiring layer, a substrate disposed on a lower surface of the first connection member; and an electrical connection structure configured to electrically connect the first connection member and the substrate. The FEIC is configured to input or output the first RF signal and a second RF signal which has a power different from a power of the first RF signal.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 28, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ho Kyung Kang, Seong Jong Cheon, Hak Gu Kim, Young Sik Hur, Jin Seon Park, Yong Duk Lee
  • Patent number: 11120190
    Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11121313
    Abstract: A semiconductor structure and a formation method thereof are disclosed. The formation method includes: providing a base; forming a dielectric layer on the base; forming a conductive via running through the dielectric layer; forming a conductive plug in the conductive via; forming a protective layer on the dielectric layer, wherein the protective layer covers the conductive plug; forming an aligner trench in the protective layer and the dielectric layer, wherein the aligner trench is isolated from the conductive plug; after forming the aligner trench, removing the protective layer to expose a top portion of the conductive plug; and after removing the protective layer, forming a magnetic tunnel junction (MTJ) laminated structure on the conductive plug.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 14, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Huan Liu
  • Patent number: 11121131
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongsoo Lee, Wonkeun Chung, Hoonjoo Na, Suyoung Bae, Jaeyeol Song, Jonghan Lee, HyungSuk Jung, Sangjin Hyun
  • Patent number: 11121036
    Abstract: A semiconductor device includes a first transistor having a first gate structure and a first source/drain feature adjacent to the first gate structure. The semiconductor device further includes a second transistor having a second gate structure and a second source/drain feature adjacent to the second gate structure. In some examples, the semiconductor device further includes a hybrid poly layer disposed between the first transistor and the second transistor. The hybrid poly layer is adjacent to and in contact with each of the first source/drain feature and the second source/drain feature, and the hybrid poly layer provides isolation between the first transistor and the second transistor.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Huan-Chieh Su, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang
  • Patent number: 11114566
    Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Kai-Chieh Yang, Chia-Wei Su, Jia-Ni Yu, Wei-Hao Wu, Chih-Hao Wang
  • Patent number: 11115010
    Abstract: A dielectric structure is loaded with energy (e.g., charge), which is retained therein until a trigger causes rapid discharge of the loaded energy and generation of an accompanying electromagnetic pulse (EMP). By appropriate design of the dielectric structure and/or trigger, the waveform of the EMP resulting from the rapid discharge can be tailored. Features of the dielectric structure can be modified and/or other devices can be coupled to the dielectric structure to also tailor the EMP, for example, to provide directionality. A modeling unit can predict the discharge in the dielectric structure and/or resulting EMP. The modeling unit can be used to determine charge density spatial distribution within the dielectric structure, shape of the dielectric structure, and/or actuation timing/location necessary to yield a desired waveform for the EMP emanating from the dielectric structure upon discharge.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 7, 2021
    Assignee: UNIVERSITY OF MARYLAND, COLLEGE PARK
    Inventors: Timothy W. Koeth, George Hine
  • Patent number: 11107814
    Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Michael P. Belyansky
  • Patent number: 11107888
    Abstract: A method for manufacturing a semiconductor device includes doping a substrate with a dopant to form a first well region of a first circuit and a second well region of a second circuit; forming a semiconductor fin extending over the first and second well regions, wherein a first section of the semiconductor fin on the first well region has a width different from a second section of the semiconductor fin on the second well region; forming a first gate electrode across first section of the first semiconductor fin and a second gate electrode across the second section of the semiconductor fin; and forming a first source/drain region adjoining the first section of the semiconductor fin and a second source/drain region adjoining the second section of the semiconductor fin.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11101182
    Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 11101267
    Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 24, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-young Lim, Jae-ho Park, Sang-hoon Baek, Hyeon-gyu You, Dal-hee Lee
  • Patent number: 11094596
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, including a first region and a second region; a first doped region in the first region of the substrate, the first doped region having first doping ions; a second doped region in the second region of the substrate, the second doped region having second dopant ions with a conductivity type opposite to the first doping ions; a first metallide on a surface of the first doped region having the first doping ions; and a second metallide on a surface of the second doped region having the second doping ions, the second metallide and the first metallide being made of different materials.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 17, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11094593
    Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi Chan Jun, Chang Hwa Kim, Dae Won Ha
  • Patent number: 11094545
    Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 11088026
    Abstract: A device having co-integrated wimpy and nominal transistors includes first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region. The device also has wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 10, 2021
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 11081551
    Abstract: In accordance with an embodiment, a method for producing a graphene-based sensor includes providing a carrier substrate; forming a carrier structure on the carrier substrate, wherein one or more separating structures are formed on an upper side of the carrier structure; and performing a wet chemical transfer of a graphene layer onto the upper side of the carrier structure that comprises the separating structures, where the separating structures and a tear strength of the graphene layer are matched to one another such that the graphene layer respectively tears at the separating structures during the wet chemical transfer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 3, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christoph Glacer, Stephan Pindl, Werner Weber, Sebastian Wittmann
  • Patent number: 11075283
    Abstract: A method includes forming a dummy gate structure over a substrate, forming a plurality of gate spacers respectively on opposite sidewalls of the dummy gate structure and having a first dielectric constant, removing the dummy gate structure to form a gate trench between the gate spacers, forming a dopant source layer to line the gate trench, annealing the dopant source layer to diffuse k-value reduction impurities from the dopant source layer into the gate spacers to lower the first dielectric constant of the gate spacers to a second dielectric constant, and forming a replacement gate stack in the gate trench.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xu-Sheng Wu, Chang-Miao Liu, Hui-Ling Shang
  • Patent number: 11075281
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Patent number: 11069534
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
  • Patent number: 11069731
    Abstract: According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Lin, Ching-Chun Wang, Dun-Nian Yaung, Chun-Ming Su, Tzu-Hsuan Hsu
  • Patent number: 11069576
    Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Wei-E Wang
  • Patent number: 11063044
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 11056595
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 6, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won Lee, Jin Woo Han, Dae Won Hwang, Kyung Wook Kim
  • Patent number: 11056591
    Abstract: A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Jin Wallner, Heng Yang, Judson Robert Holt
  • Patent number: 11043568
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 22, 2021
    Inventors: Jung-Gun You, Myung-Yoon Um, Young-Joon Park, Jeong-Hyo Lee, Ji-Yong Ha, Jun-sun Hwang
  • Patent number: 11043430
    Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Juyoun Kim
  • Patent number: 11043160
    Abstract: The disclosure discloses a common-gate transistor, a pixel circuit, a driving method and a display, including: a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region; the second doped region, the third doped region, the fourth doped region, and the fifth doped region are indirectly communicated through the first doped region, and the second doped region, the third doped region, and the fourth doped region, the fifth doped region and the first doped region are hetero-doped respectively. The two transistors in the common-gate transistor share one gate doped region, i.e., the first doped region, which can not only save one gate doped region, but also can make the gates of the two transistors have the same electrical parameters, and then the cascode effect of the two transistors is more ideal.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 22, 2021
    Assignee: Everdisplay Optronics (Shanghai) Co., Ltd.
    Inventor: Xingyu Zhou
  • Patent number: 11038046
    Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 15, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11038034
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Patent number: 11038066
    Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: June 15, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11037835
    Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Chih-Sheng Chang, Cheng-Hsien Wu
  • Patent number: 11031480
    Abstract: A semiconductor device is provided that includes an insulated gate field effect transistor series connected with a FET having several parallel conductive layers, a substrate of first conductivity type extending under both transistors, and a first layer of a second conductivity type overlies the substrate. Above this first layer are several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device may be substantially thicker than the directly underlying parallel conductive layers. The JFET is isolated with deep poly trenches of second conductivity type on the source side. The insulated gate field effect transistor is isolated with deep poly trenches of the first conductivity type on both sides. A further isolated region is isolated with deep poly trenches of the first conductivity type on both sides.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 8, 2021
    Assignee: K. EKLUND INNOVATION
    Inventors: Klas-HÃ¥kan Eklund, Lars Vestling
  • Patent number: 11031392
    Abstract: An integrated circuit device includes a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction, an element isolation layer between the first and second fin-type active areas on the substrate, first semiconductor patterns being on a top surface of the first fin-type active area and having channel areas, second semiconductor patterns being on a top surface of the second fin-type active area and having channel areas, a first gate structure extending on the first fin-type active area in a second direction and including a first work function control layer surrounding the first semiconductor patterns and comprising a step portion on the element isolation layer, and a second gate structure extending on the second fin-type active area in the second direction and including a second work function control layer surrounding the second semiconductor patterns.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongho Jeon, Sekoo Kang, Sungwoo Myung, Keunhee Bai
  • Patent number: 11031489
    Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Patent number: 11029720
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Amir Javidi, Daniel Cummings, Glenn Starnes
  • Patent number: 11031398
    Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; two first fins in an N-type region of the semiconductor device; and two second fins in a P-type region of the semiconductor device. Each of the two first fins has a channel region and two source/drain (S/D) regions sandwiching the channel region. The semiconductor device further includes a gate stack engaging the channel regions of the two first fins; and four S/D features over the S/D regions of the two first fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. Each of the lower portions of the four S/D features has a cross-sectional profile that is wider at its bottom than at its top. The upper portions of the four S/D features merge into two merged S/D features with one on each side of the gate stack.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu
  • Patent number: 11031481
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: 11024720
    Abstract: Techniques regarding non-SAC semiconductor devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a gate positioned adjacent a channel region of a semiconductor body for a field effect transistor. The gate can comprise a metal liner, and wherein the metal liner is an interface between a first metal layer of the gate and a second metal layer of the gate.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Hari Prasad Amanapu, Kangguo Cheng, Chanro Park
  • Patent number: 11024536
    Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adra Carr, Vimal Kamineni, Ruilong Xie, Andrew Greene, Nigel Cave, Veeraraghavan Basker
  • Patent number: 11024724
    Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11024550
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Patent number: RE48616
    Abstract: A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Brent A. Anderson, Edward J. Nowak