Complementary Insulated Gate Field Effect Transistors Patents (Class 257/369)
  • Patent number: 11522083
    Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Patent number: 11508737
    Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fang Chen, Kuo-Chiang Ting, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 11508738
    Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin
  • Patent number: 11508625
    Abstract: A semiconductor device includes a first n-type transistor and a first p-type transistor that are positioned side by side over a substrate. The first n-type transistor includes a first n-type source/drain (S/D) region, a first n-type channel region, and a second n-type S/D region that are formed based on a first continuous channel structure extending along a horizontal direction parallel to the substrate. The first n-type channel region is positioned between the first n-type S/D region and the second n-type S/D region. The first p-type transistor includes a first p-type S/D region, a first p-type channel region, and a second p-type S/D region that are formed based on the first continuous channel structure. The first p-type channel region is positioned between the first p-type S/D region and the second p-type S/D region. The second n-type S/D region is in contact with the first p-type S/D region.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: November 22, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Patent number: 11508761
    Abstract: Provided are an inverter circuit structure, a gate driving circuit and a display panel. The inverter circuit structure includes a PMOS transistor and an NMOS transistor, and further includes a first active layer, a gate layer, a second active layer, a first insulating layer between the gate layer and the first active layer, and a second insulating layer between the gate layer and the second active layer. An orthographic projection of the gate on the first active layer is a first region, and a portion of the first active layer in the first region has substantially a same thickness. An orthographic projection of the gate on the second active layer is a second region, and a portion of the second active layer in the second region has substantially a same thickness.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 22, 2022
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Jieliang Li, Yuping Xu
  • Patent number: 11502078
    Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics International N.V.
    Inventor: Vishal Kumar Sharma
  • Patent number: 11495633
    Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hisanori Ihara
  • Patent number: 11495676
    Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 8, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 11488651
    Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
  • Patent number: 11476351
    Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
  • Patent number: 11476159
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Patent number: 11462441
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: October 4, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Wei Su, Hao-Che Feng, Hsuan-Tai Hsu, Chun-Yu Chen, Wei-Hao Huang, Bin-Siang Tsai, Ting-An Chien
  • Patent number: 11456218
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 27, 2022
    Inventors: Guilei Wang, Henry H Radamson, Zhenzhen Kong, Junjie Li, Jinbiao Liu, Junfeng Li, Huaxiang Yin
  • Patent number: 11450758
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Patent number: 11443979
    Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first transistor includes a first gate structure. The first gate structure of the first transistor may include a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially disposed on the substrate. The second transistor includes a second gate structure. The second gate structure comprises a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate. The first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Da-Yuan Lee
  • Patent number: 11444079
    Abstract: A semiconductor device includes: a semiconductor substrate; a VNW transistor being a functional element provided with a first projection formed on the semiconductor substrate, having a semiconductor material, and having a lower end and an upper end; a dummy functional element provided with a second projection formed on the semiconductor substrate, having a semiconductor material, having a lower end and an upper end, and arranged side by side with the first projection; and a first wiring formed above the first projection and above the second projection, electrically connected to the upper end of the first projection, and electrically isolated from the upper end of the second projection. Consequently, the semiconductor device capable of suppressing variation in characteristics of the VNW transistors is realized.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 13, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Hidetoshi Tanaka
  • Patent number: 11424243
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Chih-Liang Chen, Shi Ning Ju
  • Patent number: 11417571
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 16, 2022
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Tien-Wei Yu
  • Patent number: 11410984
    Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 9, 2022
    Assignee: Silicon Genesis Corporation
    Inventors: Michael I. Current, Theodore E. Fong
  • Patent number: 11411107
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Patent number: 11404326
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; and a gate layer crossing over the first active region, the second active region, and the isolation region, wherein the gate layer includes a first impurity doped portion overlapping with the first active region, a second impurity doped portion overlapping with the second active region, and a diffusion barrier portion positioned between the first impurity doped portion and the second impurity doped portion.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: August 2, 2022
    Assignee: SK hynix Inc.
    Inventor: Keon Yoo
  • Patent number: 11398499
    Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 26, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae-Woo Seo, Youngsoo Shin
  • Patent number: 11393677
    Abstract: A s semiconductor device structure is provided. The structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The structure also includes a spacer element extending along a sidewall of the gate stack. The spacer element has a first portion, a second portion, a third portion, and a fourth portion. Each of the first portion, the second portion, the third portion, and the fourth portion conformally extends along the sidewall of the gate stack. The second portion is sandwiched between the first portion and the third portion, and the third portion is sandwiched between the second portion and the fourth portion. Each of the first portion and the third portion has a first atomic concentration of carbon, and each of the second portion and the fourth portion has a second atomic concentration of carbon. The second atomic concentration of carbon is different than the first atomic concentration of carbon.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Yao Tu, Yu-Yun Peng
  • Patent number: 11387344
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Lee, Hung-Chin Chung, Chung-Chiang Wu, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen, Chi On Chui
  • Patent number: 11387234
    Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehyung Kim, Panjae Park, Jaeseok Yang
  • Patent number: 11387346
    Abstract: A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11381226
    Abstract: The present disclosure includes storage circuits, such latches. In one embodiment, a circuit includes a plurality of latches, each latch including a first N-type transistor formed in a first P-type material, a first P-type transistor formed in a first N-type material, a second N-type transistor formed in a second P-type material, and a second P-type transistor formed in a second N-type material. The first and second N-type transistors are formed in different P-wells and the first and second P-type transistors are formed in different N-wells. In other storage circuits, charge extraction transistors are coupled to data storage nodes and are biased in a nonconductive state. These techniques make the data storage circuits more resilient, for example, to an ionizing particle striking the circuit and generating charge carriers that would otherwise change the state of the storage node.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: July 5, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yanzhong Xu, Tracey DellaRova
  • Patent number: 11380782
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chien-Tai Chan, Liang-Yin Chen, Yee-Chia Yeo, Szu-Ying Chen
  • Patent number: 11380761
    Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Seong-Wan Ryu
  • Patent number: 11367722
    Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Stephen Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar, Rishabh Mehandru, Sean Ma, Ehren Mannebach, Anh Phan, Cheng-Ying Huang
  • Patent number: 11362091
    Abstract: A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: June 14, 2022
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I Gardner
  • Patent number: 11362002
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Patent number: 11362092
    Abstract: A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: June 14, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Masanori Yoshitani
  • Patent number: 11362176
    Abstract: A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Ta Wu, Chiu Hua Chen
  • Patent number: 11362109
    Abstract: The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ko-Tao Lee, Xin Zhang, Todd Edward Takken
  • Patent number: 11362051
    Abstract: Making a semiconductor-on-insulator substrate provided with an eddy current blocking structure (20) formed in a segment (22) doped according to doping of a first type, of doped regions (23) periodically distributed on one or more parallel rows and according to a pattern (M2) and an improved arrangement.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 14, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Pierre Colinge, Louis Hutin, Maxime Moulin, Thibaud Fache
  • Patent number: 11348837
    Abstract: A semiconductor device includes a semiconductor substrate, first gate structure, a first metal layer, a first protective layer, and a first contact plug. The first gate structure includes a plurality of first U-shaped layers stacked one another between the first gate spacers in a cross-sectional view and first gate spacers on opposite sides of the first U-shaped layers. The first metal layer is over the first U-shaped layers and has a different shape than the first U-shaped layers in the cross-sectional view. The first protective layer is over the first metal layer and between the first gate spacers. The first contact plug extends through the first protective layer and the first metal layer, and is in contact with the first gate structure.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Soon Lim, Zi-Wei Fang
  • Patent number: 11349461
    Abstract: A flip-flop circuit includes gate circuits of which the number is N being an integer of 3 or more, and in which an output signal from the (N?1)th gate circuit is used as an input signal of the N-th gate circuit, the gate circuit being configured to output the output signal in response to a clock signal and the input signal. The N gate circuits include a first MOS transistor group including MOS transistors which are in an OFF state when a potential of an output signal node that outputs the output signal is held, and a second MOS transistor group including MOS transistors which are in an ON state when the potential of the output signal node is held. A threshold voltage of at least one MOS transistor in the first MOS transistor group is higher than a threshold voltage of at least one MOS transistor in the second MOS transistor group.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 31, 2022
    Inventor: Yasunari Furuya
  • Patent number: 11342338
    Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hao Lin, Kian-Long Lim, Chih-Chuan Yang, Chia-Hao Pao, Jing-Yi Lin
  • Patent number: 11342340
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yangsyu Lin, Chi-Lung Lee, Chien-Chi Tien, Chiting Cheng
  • Patent number: 11328670
    Abstract: The present disclosure is related to a pixel circuit. The pixel circuit may include a first transistor, a photoelectric sensor, a switch transistor, a second transistor, a third transistor, and a light-emitting component. The first transistor may be configured to transmit a data voltage in response to a scanning signal of an N-th row. The second transistor may be configured to generate a driving current based on a data voltage transmitted by the first transistor and to generate a leakage current based on an electric signal transmitted by the switching transistor. The third transistor may be configured to compensate a threshold voltage of the second transistor in response to a scanning signal of an N-th row. The light-emitting component may be configured to emit light under an action of a driving current generated by the second transistor.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 10, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hao Zhang, Kuo Sun, Haijun Yin
  • Patent number: 11322396
    Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ping Tung, Jen Hung Wang, Shing-Chyang Pan
  • Patent number: 11315934
    Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Peng Zheng, Varun Mishra, Tahir Ghani
  • Patent number: 11309190
    Abstract: In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
  • Patent number: 11302586
    Abstract: A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: April 12, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Amitay Levi, Dafna Beery, Andrew J. Walker
  • Patent number: 11302395
    Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric overlying a semiconductor having a first conductivity type, a conductor overlying the dielectric, first and second extension region bases formed in the semiconductor and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Haitao Liu
  • Patent number: 11302567
    Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11295956
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 5, 2022
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Patent number: 11296077
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11296078
    Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byounghoon Lee, Jongho Park, Wandon Kim, Sangjin Hyun