Complementary Insulated Gate Field Effect Transistors Patents (Class 257/369)
  • Patent number: 11961768
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 11955484
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Patent number: 11955483
    Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device includes: a base substrate; a gate structure on the base substrate including a first portion in a first region and a second portion in a second region; and a separation section in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region. A top surface of the separation section is higher than a top surface of the gate structure.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 9, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11948973
    Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang
  • Patent number: 11929433
    Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 12, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ignasi Cortes, Alban Zaka, Tom Herrmann, El Mehdi Bazizi, Richard Francis Taylor, III
  • Patent number: 11929289
    Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Juyoun Kim
  • Patent number: 11923249
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11923434
    Abstract: A method is presented for forming a vertical transport field effect transistor (VTFET). The method includes forming a plurality of fins over a substrate, depositing a sacrificial material adjacent the plurality of fins, forming self-aligned spacers adjacent the plurality of fins, removing the sacrificial material to define openings under the self-aligned spacers, filling the openings with bottom spacers, depositing an interlayer dielectric (ILD) after patterning, laterally etching the substrate such that bottom surfaces of the plurality of fins are exposed, the lateral etching defining cavities within the substrate, and filling the cavities with an epitaxial material such that epitaxial regions are defined each having a symmetric tapered shape under a twin-fin structure. The single fin device can be formed through additional patterning and bottom epi under the single fin device that has an asymmetric tapered shape.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 5, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tao Li, Ruilong Xie, Sung Dae Suk, Heng Wu
  • Patent number: 11923354
    Abstract: A semiconductor device includes standard cells in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, and filler cells between ones of the standard cells. Each of the standard cells includes an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines. Each of the filler cells includes a filler active region and a filler gate structure that intersects the filler active region. The standard cells include first to third standard cells in first to third rows sequentially in the second direction, respectively. First interconnection lines are arranged with a first pitch, second interconnection lines are arranged with a second pitch, and third interconnection lines are arranged with a third pitch different from the first and second pitches.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dayeon Cho, Hyungock Kim, Sangdo Park
  • Patent number: 11925011
    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Jhon Jhy Liaw
  • Patent number: 11915981
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Soon Lim, Zi-Wei Fang
  • Patent number: 11908857
    Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 20, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Yanping Shen, Haiting Wang, Sipeng Gu
  • Patent number: 11908750
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Patent number: 11908866
    Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Lien Jung Hung, Shih-Hao Lin
  • Patent number: 11907633
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 11881484
    Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: January 23, 2024
    Assignee: SOCIONEXT INC.
    Inventors: Toshio Hino, Junji Iwahori
  • Patent number: 11869812
    Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Huimei Zhou, Miaomiao Wang, Alexander Reznicek
  • Patent number: 11862562
    Abstract: A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lai, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11862637
    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
  • Patent number: 11854960
    Abstract: A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Lu, Chih-Chiang Chang, Chung-Chieh Yang, Yung-Chow Peng
  • Patent number: 11855070
    Abstract: A semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The at least one conductive via connects the first conductor and the second conductor through the third conductor.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hsin Tsai, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11855069
    Abstract: A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Sing Li, Chi-Yu Lu, Hui-Zhong Zhuang, Chih-Liang Chen
  • Patent number: 11855176
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 11848242
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Chih-Liang Chen, Tzu-Chiang Chen, I-Sheng Chen, Lei-Chun Chou
  • Patent number: 11848326
    Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
  • Patent number: 11842947
    Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 12, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11842928
    Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Patent number: 11842998
    Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin Kuo Chao, Hemanth Jagannathan, Choonghyun Lee, Chun Wing Yeung, Jingyun Zhang
  • Patent number: 11837604
    Abstract: An approach provides a semiconductor structure with a first crystalline surface orientation and a first nanosheet stack on the semiconductor substrate with the first crystalline surface orientation. The semiconductor substrate structure includes a second nanosheet stack with a second crystalline surface orientation above the first nanosheet stack, wherein the first nanosheet stack and the second nanosheet stack are separated by a dielectric material.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: December 5, 2023
    Assignee: International Business Machine Corporation
    Inventors: Kangguo Cheng, Shogo Mochizuki, Juntao Li
  • Patent number: 11830742
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
  • Patent number: 11824098
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first silicon-germanium film which is conformally formed inside a surface of the substrate of the first region and defines a first gate trench, a first gate insulating film which extends on the first silicon-germanium film along a profile of the first gate trench and is in physical contact with the first silicon-germanium film, a first metallic gate electrode on the first gate insulating film, a source/drain region formed inside the substrate on both sides of the first metallic gate electrode, a second gate insulating film in the second region and a second metallic gate electrode on the second gate insulating film.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: November 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Kyun An, Su Min Cho
  • Patent number: 11817497
    Abstract: Embodiments of the invention include a vertical field-effect transistor (VTFET) inverter. The VTFET inverter may include a p-channel field-effect transistor (P-FET) with a P-FET top source/drain and a P-FET bottom source/drain. The VTFET inverter may also include an n-channel field-effect transistor (N-FET) comprising an N-FET top source/drain and a N-FET bottom source/drain. The VTFET inverter may also include a buried contact located at a boundary between the P-FET bottom source/drain and the N-FET bottom source/drain. The VTFET inverter may also include a Vout contact electrically connected to one of the P-FET bottom source/drain and the N-FET bottom source/drain.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Ruilong Xie, Alexander Reznicek, Chen Zhang
  • Patent number: 11810909
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiang-Bau Wang, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ming-Ching Chang
  • Patent number: 11804415
    Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Markus Kahn, Oliver Humbel, Philipp Sebastian Koch, Angelika Koprowski, Christian Maier, Gerhard Schmidt, Juergen Steinbrenner
  • Patent number: 11798988
    Abstract: A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 24, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Sergei V. Gronin, Raymond L. Kallaher, Michael James Manfra
  • Patent number: 11791217
    Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Patent number: 11791221
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer
  • Patent number: 11769795
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Patent number: 11764219
    Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 19, 2023
    Assignee: Intel Corporation
    Inventors: Harshitha Vishwanath, Renukprasad Hiremath, Sukru Yemenicioglu, Ranjith Kumar, Ruth Amy Brain
  • Patent number: 11764218
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 11756972
    Abstract: According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Lin, Ching-Chun Wang, Dun-Nian Yaung, Chun-Ming Su, Tzu-Hsuan Hsu
  • Patent number: 11749558
    Abstract: A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 5, 2023
    Assignees: Quantum Silicon Inc., The Governors of the University of Alberta, National Research Council of Canada
    Inventors: Bruno Vieira Da Cunha Martins, Robert A. Wolkow, Marco Taucer, Jason Pitters
  • Patent number: 11749681
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J. H. Wang
  • Patent number: 11742345
    Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inchan Hwang, Hwichan Jun
  • Patent number: 11742351
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 29, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongsoo Lee, Wonkeun Chung, Hoonjoo Na, Suyoung Bae, Jaeyeol Song, Jonghan Lee, HyungSuk Jung, Sangjin Hyun
  • Patent number: 11735661
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 11735593
    Abstract: A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Jingyun Zhang, Koji Watanabe, Jing Guo
  • Patent number: 11735590
    Abstract: A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
  • Patent number: 11728431
    Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a first plurality of channel members, and a second GAA transistor that includes a second plurality of channel members. The first plurality of channel members has a first pitch (P1) and the second plurality of channel members has a second pitch (P2) smaller than the first pitch (P1).
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11728401
    Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang