High Speed Backside Illuminated, Front Side Contact Photodiode Array
The present specification discloses front-side contact back-side illuminated (FSC-BSL) photodiode array having improved characteristics such as high speed of each photodiode, uniformity of the bias voltage applied to different photodiode, low bias voltage, reduced resistance of each photodiode, and an associated reduction in noise. The photodiode array is made of photodiodes with front metallic cathode pads, front metallic anode pad, back metallic cathode pads, n+ doped regions and a p+ doped region. The front metallic cathode pads physically contact the n+ doped regions and the front metallic anode pad physically contacts the p+ doped region. The back metallic cathode pads physically contact the n+ doped region.
The present invention is a continuation-in-part of 1) U.S. patent Ser. No. 12/559,498, filed on Sep. 15, 2009, 2) U.S. patent Ser. No. 12/744,908, filed on May 7, 2007, 3) U.S. patent Ser. No. 11/422,246, filed on Jun. 5, 2006, 4) U.S. patent Ser. No. 12/637,557, filed on Dec. 14, 2009, 5) Ser. No. 12/637,529, filed on Dec. 14, 2009, 6) U.S. patent Ser. No. 12/499,203, filed on Jul. 8, 2009, 7) U.S. patent Ser. No. 11/849,623, filed on Sep. 4, 2007, 8) U.S. patent Ser. No. 12/325,304, filed on Dec. 1, 2008, and 9) U.S. patent Ser. No. 12/505,610, filed on Jul. 20, 2009. All of the aforementioned specifications are incorporated herein by reference in their entirety.
FIELD OF INVENTIONThe present invention relates generally to the field of radiation detectors and more specifically to back side illuminated, front side contact photodiode/photodiode arrays having high speed at low biasing.
BACKGROUND OF THE INVENTIONPhotodiodes comprise of multiple radiation sensitive junctions formed in semiconductor material. Within a photodiode, charge carriers are created by light that illuminates the junction and photo current is generated dependent upon the degree of illumination. Similarly, photodiode array comprises of large number of light sensitive spaced-apart elements, comprising of a semiconductor junction and a region of high response where the photo-generated charge carriers are collected. Array of photodiodes or basically photodiodes are used in various applications including, but not limited to, optical position encoding, and low light-level imaging, such as night photography, nuclear medical imaging, photon medical imaging, multi-slice computer tomography (CT) imaging, radiation detection and ballistic photon detection.
Photodiodes are characterized by certain characteristics, such as electrical, optical, current (I), voltage (V), and noise. Electrical characteristics of photodiode dominantly include shunt resistance, series resistance, junction capacitance, rise or fall time and frequency response. Noise in photodiodes is generated by a plurality of sources including, but not limited to, thermal noise, quantum or photon noise, and flicker noise.
Detection devices are susceptible to numerous radiation damage mechanisms due to increased reverse-bias current and decreased forward voltage over time. Change in doping level, due to radiation damage, adversely affects the width of the depletion region and a decrease in carrier lifetime results in signal loss as carriers recombine while traversing the depletion region.
Also, in certain applications, optical detectors having small lateral dimensions and spaced closely together are favourably produced. For example in certain medical applications, it would be beneficial to increase the optical resolution of a detector array in order to permit for improved image scans, such as computer tomography scans. However, the diffusion length of minority carriers by photon interaction in the semiconductor is in the range of at least many tens of microns in conventional doping levels utilized for diode arrays. Such minority carriers have potential to affect signals at diodes away from the region at which the minority were generated. Therefore, the spatial resolution obtainable may be limited by diffusion of the carriers within the semiconductor itself, even if other components of the optical system are optimized and scattered light is reduced.
Furthermore, another disadvantage of the abovementioned structure of the typical photodiode is for high speed application. Since the cathode contact is located only on the front side, it requires a higher voltage to fully deplete the device and even after the device is fully depleted, under reverse bias the electrons need to travel the undepleted high resistivity zone at the side of the chip to the top contact. The consequence of this is a high series resistance and a low speed due to a high RC-time component of the device. Due to high series resistance and low speed the photodiodes are rendered inappropriate for high speed applications.
In light of the abovementioned disadvantages, there is a need for front side contact, back side illuminated photodiode array having improved characteristics, including high production throughput, low cost manufacturing, uniform as well as high photocurrent density. Further, there is also a need for photodiode/photodiode array having high speed at low biasing voltages.
SUMMARY OF THE INVENTIONThe present specification discloses a photodiode array having a front side and a back side separated by a layer of silicon and a top edge, a bottom edge, a right edge, and a left edge, comprising: a plurality of metallic cathode pads extending from said front side of the photodiode array wherein each of said metallic cathode pads is in physical contact with at least one n+ doped region; a plurality of metallic cathode pads extending from said back side of the photodiode array wherein each of said metallic cathode pads is in physical contact with a second n+ doped region; a metallic grid on the front side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said front side of the photodiode array; and a metallic grid on the back side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said back side of the photodiode array.
Optionally, the photodiode array is comprised of a plurality of photodiodes, each of said photodiodes comprising a first metallic cathode pad and a second metallic cathode pad extending from said front side of the photodiode array. Each of said photodiodes has an anode pad extending from the said front side of the photodiode array and wherein said anode pad is positioned between said first cathode pad and second metallic cathode pad. The anode pad is in physical contact with a p+ doped region. The layer of silicon is in the range of 80 to 200 microns thick. The second n+ doped region is on the order of 0.3 micrometers. The second n+ doped region has a resistivity of approximately 0.005 Ohm-centimeter. The photodiode array is comprised of a plurality of photodiodes, each of said photodiodes having a resistance on the order of 10 to 100 ohm. The photodiode array has a rise time of 40 nanoseconds or less. In one embodiment, the metallic grid on the front said of said array defines a universal, multi-element array of cells wherein each cell comprises a photodiode. In one embodiment, the metallic grid on the front side of said array defines at least 64 cells, each of said cells comprising a photodiode.
The present specification discloses a photodiode array having a front side and a back side separated by a layer of silicon and a top edge, a bottom edge, a right edge, and a left edge, comprising: a plurality of metallic cathode pads extending from said front side of the photodiode array wherein each of said metallic cathode pads is in physical contact with at least one n+ doped region; a plurality of metallic cathode pads extending from said back side of the photodiode array wherein each of said metallic cathode pads is in physical contact with a second n+ doped region; a plurality of anode pads extending from the front side of the photodiode array, wherein each of said anode pads is positioned between a first metallic cathode pad and a second metallic cathode pad; and a metallic grid on the back side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said back side of the photodiode array.
Optionally, the photodiode array is comprised of a plurality of photodiodes, each of said photodiodes comprising at least two metallic cathode pads extending from said front side of the photodiode array. The anode pad is in physical contact with a p+ doped region. The layer of silicon is on the order of 130 microns thick. The second n+ doped region is on the order of 0.3 micrometers. The second n+ doped region has a resistivity of approximately 0.005 Ohm-centimeter. The photodiode array is comprised of a plurality of photodiodes, each of said photodiodes having a resistance on the order of 10 to 100 ohm. The photodiode array has a rise time of 40 nanoseconds or less. The photodiode array further comprises a metallic grid on the front side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said front side of the photodiode array. The metallic grid on the front side and back side of said array defines a universal, multi-element array of cells, wherein each of said cells comprises a photodiode.
These and other features and advantages of the present invention will be appreciated, as they become better understood by reference to the following detailed description when considered in connection with the accompanying drawings:
The present invention is directed towards detector structures, detector arrays, and design and implementation of detector arrays for a variety of applications including but not limited to computerized tomography (CT) and non CT applications. Specifically, the present invention is directed towards high density photodiode arrays manufactured at high throughput and low cost, capable of generating uniform as well as high density photocurrent
The present invention is directed towards multiple embodiments. The following disclosure is provided in order to enable a person having ordinary skill in the art to practice the invention. Language used in this specification should not be interpreted as a general disavowal of any one specific embodiment or used to limit the claims beyond the meaning of the terms used therein. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
More specifically, the present invention is directed towards front-side contact back-side illuminated (FSC-BSL) photodiode array having improved characteristics such as high speed of each photodiode, uniformity of the bias voltage applied to different photodiode, low bias voltage, reduced resistance of each photodiode, and an associated reduction in noise.
The prior art photodiode 100 has substantial disadvantages, however, with respect to high speed applications. As the metallic cathode contacts 102,104 are located only on the front side, a higher voltage is required to fully deplete the photodiode 100. Even in instances where the device is fully depleted under reverse bias, electrons 117, at the back side of the photodiode 100, need to travel the undepleted high resistivity zone 116 to reach the metallic cathode contacts 102,104 at the front side. The high resistivity zone 116 is typically of the order of 8000 Ohm-centimeter. This results in high series resistance amongst the photodiodes and photodiode array and is of the order of 10 kohm-100 kohm. The high series resistance further results in low speed due to high RC time component, thus making the photodiode 100 inappropriate for high speed applications.
In the photodiode 200 of the present invention, as the cathode contact pads 208, 210 are provided on the back side of the photodiode 200, therefore, when the device is fully depleted the electrons 217 need not travel the high resistivity zone 220 and can be collected at the back metallic cathodes 208, 210. In one embodiment the high resistivity zone 220 is typically of the order of 8000 Ohm-centimeter. The electrons 217 do not traverse the high resistivity zone 220 and bypasses it by traveling via the back metallic cathodes 208, 210. This bypass results in lower resistance amongst the photodiodes and photodiode array. In an embodiment, since the carriers travel through the very low resistance back side N+ doped region 216 to reach the metal contact 208,210 the series resistance of the photodiode 200 is low and is of the order of 10 to 100 ohm. The low series resistance further results in high speed due to low RC time component, thus enabling it to be used in wide variety of high speed applications.
The photodiode array 300, of the present invention, further comprises cathode pad 310, anode pads 312 and a cathode metal grid 314. The cathode metal grid 314 runs through the entire array 304 interconnecting every photodiode via cathode pad 310. In one embodiment, a single bias voltage enables all the photodiodes via cathode metal grid 314.
At step 810, the device wafer 801a is subjected to a standard mask oxidation process that grows silicon oxide layers 802a, 803a on front and back sides, respectively, of the device wafer 801a. In one embodiment, the oxidation mask is made of silicon oxide (SiO2) or silicon nitride (Si3N4) and thermal oxidation is employed to achieve mask oxidation.
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In one embodiment of the present invention, the device wafer 801b is subjected to n+ masking. N+ masking is employed to protect portions of device wafer 801b. Generally, photographic masks are high precision plates containing microscopic images of preferred pattern or electronic circuits. They are typically fabricated from flat pieces of quartz or glass with a layer of chrome on one side. The mask geometry is etched in the chrome layer. In one embodiment, the n+ mask comprises a plurality of diffusion windows with appropriate geometrical and dimensional specifications. The photoresist coated device wafer 801b is aligned with the n+ mask. An intense light, such as UV light, is projected through the mask, exposing the photoresist layer in the pattern of the n+ mask. The n+ mask allows selective irradiation of the photoresist on the device wafer. Regions that are exposed to radiation are hardened while those that are reserved for deep diffusion remain shielded by the n+ mask and easily removed. The exposed and remaining photoresist is then subjected to a suitable chemical or plasma etching to reveal the pattern transfer from the mask to the photoresist layer. An etching process is then employed to remove the silicon dioxide layer. In one embodiment, the pattern of the photoresist layer and/or n+ mask defines at least one region 802b, 803b devoid of the oxide layer deposited in the step 810 and is ready for n+ diffusion.
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Nuisance effects, which transpire when superfluous drive-in steps occur as an artifact of the overall process, tend to be a key problem in drive-in diffusion. More specifically, nuisance effects are compounded during each subsequent high temperature drive-in step, which causes further diffusion of the dopant into the substrate. Each high temperature step results in alterations, these alterations are then accounted to arrive at a thermal budget value. Thus, the thermal budget of an overall process is dependent on number of steps undertaken.
In one embodiment, the low thermal budget deep diffusion process used to manufacture the back side illuminated front side contact photodiode of the present invention comprises two steps; first, deposition/diffusion step, and a second drive-in oxidation step. The two step example provided above is by way of example only and no way limiting to the present invention. It should be understood by those of ordinary skill in the art that any number of steps may be performed keeping in mind overall cost efficiency and thermal budget of the device.
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The above examples are merely illustrative of the many applications of the system of present invention. Although only a few embodiments of the present invention have been described herein, it should be understood that the present invention might be embodied in many other specific forms without departing from the spirit or scope of the invention. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims.
Claims
1. A photodiode array having a front side and a back side separated by a layer of silicon and a top edge, a bottom edge, a right edge, and a left edge, comprising:
- a. a plurality of metallic cathode pads extending from said front side of the photodiode array wherein each of said metallic cathode pads is in physical contact with at least one n+ doped region;
- b. a plurality of metallic cathode pads extending from said back side of the photodiode array wherein each of said metallic cathode pads is in physical contact with a second n+ doped region;
- c. a metallic grid on the front side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said front side of the photodiode array; and
- d. a metallic grid on the back side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said back side of the photodiode array.
2. The photodiode array of claim 1 wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes comprising a first metallic cathode pad and a second metallic cathode pad extending from said front side of the photodiode array.
3. The photodiode of claim 2 wherein each of said photodiodes has an anode pad extending from the said front side of the photodiode array and wherein said anode pad is positioned between said first cathode pad and second metallic cathode pad.
4. The photodiode of claim 3 wherein said anode pad is in physical contact with a p+ doped region.
5. The photodiode array of claim 1 wherein the layer of silicon is in the range of 80 to 200 microns thick.
6. The photodiode array of claim 1 wherein the second n+ doped region is on the order of 0.3 micrometers.
7. The photodiode array of claim 1 wherein the second n+ doped region has a resistivity of approximately 0.005 Ohm-centimeter.
8. The photodiode array of claim 1 wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes having a resistance on the order of 10 to 100 ohm.
9. The photodiode array of claim 1 wherein said photodiode array has a rise time of 40 nanoseconds or less.
10. The photodiode array of claim 1 wherein said metallic grid on the front side of said array defines at least 64 cells, each of said cells comprising a photodiode.
11. A photodiode array having a front side and a back side separated by a layer of silicon and a top edge, a bottom edge, a right edge, and a left edge, comprising:
- a. a plurality of metallic cathode pads extending from said front side of the photodiode array wherein each of said metallic cathode pads is in physical contact with at least one n+ doped region;
- b. a plurality of metallic cathode pads extending from said back side of the photodiode array wherein each of said metallic cathode pads is in physical contact with a second n+ doped region;
- c. a plurality of anode pads extending from the front side of the photodiode array, wherein each of said anode pads is positioned between a first metallic cathode pad and a second metallic cathode pad; and
- d. a metallic grid on the back side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said back side of the photodiode array.
12. The photodiode array of claim 11 wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes comprising at least two metallic cathode pads extending from said front side of the photodiode array.
13. The photodiode of claim 11 wherein said anode pad is in physical contact with a p+ doped region.
14. The photodiode array of claim 11 wherein the layer of silicon is in the range of 80 to 200 microns thick.
15. The photodiode array of claim 11 wherein the second n+ doped region is on the order of 0.3 micrometers.
16. The photodiode array of claim 11 wherein the second n+ doped region has a resistivity of approximately 0.005 Ohm-centimeter.
17. The photodiode array of claim 11 wherein said photodiode array is comprised of a plurality of photodiodes, each of said photodiodes having a resistance on the order of 10 to 100 ohm.
18. The photodiode array of claim 11 wherein said photodiode array has a rise time of 40 nanoseconds or less.
19. The photodiode array of claim 11 further comprising a metallic grid on the front side of said array, wherein said metallic grid forms a plurality of rows in parallel to said top edge and bottom edge and perpendicular to said right edge and left edge, wherein said metallic grid forms a plurality of columns in parallel to said right edge and left edge and perpendicular to said top edge and bottom edge, and wherein said metallic grid interconnects each of said plurality of metallic cathode pads extending from said front side of the photodiode array.
20. The photodiode array of claim 19 wherein said metallic grid on the front side of said array defines at least 64 cells, each of said cells comprising a photodiode.
Type: Application
Filed: Nov 3, 2014
Publication Date: May 21, 2015
Inventors: Peter Steven Bui (Cerritos, CA), Narayan Dass Taneja (Long Beach, CA)
Application Number: 14/531,287
International Classification: H01L 27/146 (20060101);