SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES
One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.
1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a semiconductor device using a layer of material having a plurality of trenches formed therein and the resulting semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width (for a tri-gate device). Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
As device dimensions continue to shrink, the physical size of the fins (width and height) of a FinFET device are also reduced. As a result, the fins are very small structures in the world of semiconductor processing. Moreover, due to the prior art manner in which FinFET devices are made, the fins are subjected to numerous cleaning and etching processes that undesirably remove portions of the fin structures in the source/drain regions of the device despite best efforts to use highly selective etch/cleaning chemistries. Traditionally, the fins are the first components of a FinFET device that are formed. They are formed by performing an etching process through a patterned etch mask to define the fins in the substrate. Thereafter, a gate structure (either a final gate structure or a sacrificial gate structure) is formed above the channel region of the fins, by performing one or more reactive ion etching processes to pattern the gate materials and a gate cap layer. Thereafter, sidewall spacers are formed adjacent the gate structure by depositing a layer of spacer material and performing another reactive ion etching process to remove desired portions of the layer of spacer material, leaving sidewall spacers formed adjacent the gate structure. Later in the processing operation, an epi pre-clean process will be performed on the fins in the source/drain region of the device prior to forming an epi semiconductor material on the fins in the source/drain regions. From the brief explanation above, the fins in the source/drain regions are subjected to at least two reactive ion etching processes (gate patterning and spacer formation), as well as the epi pre-clean process, all of which tend to undesirably remove fin material.
In some cases, damage to the fin structures in the source/drain regions of the device may not be a significant concern, i.e., an application in which there may be significant growth of epi material in the source/drain regions. Nevertheless, even in those situations, problems can occur if too much of the epi material is grown in the source/drain regions of the device, e.g., epi-to-epi shorting between adjacent devices or around the end of the gate structure on a single device.
Another area of potential concern is related to the formation of so-called self-aligned contacts. The typical process flow for forming such contacts involves forming an opening in a layer of silicon dioxide that is supposed to stop on a silicon nitride gate cap layer and a silicon nitride sidewall spacer (that are formed to protect the gate materials). Unfortunately, there is a risk of consuming too much of the gate cap layer and/or the sidewall spacer during the contact opening etching process which can lead to exposure of the gate materials. When the contact is formed in the contact opening, there is a chance of creating a contact-to-gate electrical short due to the loss of the cap and/or spacer material.
The present disclosure is directed to various methods of forming a semiconductor device using a layer of material having a plurality of trenches formed therein and the resulting semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to a semiconductor device with a layer of material having a plurality of trenches formed therein. One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.
Another illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, the layer of material having a dielectric constant equal to or less than 7, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, wherein the first conductive source/drain contact structure abuts and engages sidewalls of the first source/drain trench and the second conductive source/drain contact structure abuts and engages sidewalls of the second source/drain trench, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, wherein the gate structure abuts and engages sidewalls of the gate trench, and a gate cap layer positioned above the gate structure.
Yet another illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches formed in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches, wherein first portions of the layer of material remain positioned between the first and second source/drain trenches and the gate trench above the active region and second portions of the layer of material remain positioned between the first and second source/drain trenches and the gate trench outside of the active region, wherein the second portions of the layer of material are thicker in a gate length direction of the device than are the first portions of the layer of material, and a gate structure positioned within the gate trench, wherein a first portion of sidewalls of the gate structure are positioned adjacent the first portions of the layer of material and a second portion of the sidewalls of the gate structure are positioned adjacent the second portions of the layer of material.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure generally relates to various methods of forming a semiconductor device using a layer of material having a plurality of trenches formed therein and the resulting semiconductor device. Moreover, as will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. The methods and devices disclosed herein may be employed in manufacturing products using a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory devices, logic devices, ASICs, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
In one embodiment, the illustrative device 100 will be formed in and above the semiconductor substrate 102, having a bulk configuration. The device 100 may be either an NMOS or a PMOS transistor. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. The substrate 102 may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.
As will be appreciated by those skilled in the art after a complete reading of the present application, the methods and structures disclosed herein may be used when forming either planar or 3D transistor devices. An illustrative device 100 in the form of a 3D, FinFET device 100 will be depicted for purposes of disclosing the subject matter set forth herein. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. Moreover, the transistor devices that are depicted in the attached drawings may be either NMOS or PMOS devices. The various components and structures of the device 100 disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application.
In general, the subsequent drawings contain a simplistic plan view and various cross-sectional views. As shown in a simplistic plan drawing shown in the upper right corner of
At the point in fabrication depicted in
The width and height of the fin structures 106 as well as the depth of the trenches 104 may vary depending upon the particular application. Additionally, the overall size, shape and configuration of the fin-formation trenches 104 and fins 106 may vary depending on the particular application. In the illustrative examples depicted in the attached drawings, the fin-formation trenches 104 and fins 106 are all depicted as having a uniform size and shape. However, such uniformity in the size and shape of the fin-formation trenches 104 and the fins 106 is not required to practice at least some aspects of the inventions disclosed herein. In the attached figures, the fin-formation trenches 104 are depicted as having been formed by performing an anisotropic etching process that results in the fin-formation trenches 104 having a schematically depicted, generally rectangular configuration. In an actual real-world device, the sidewalls of the fin-formation trenches 104 may be somewhat inwardly tapered, although that configuration is not depicted in the attached drawings. In some cases, the fin-formation trenches 104 may have a reentrant profile (not shown) near the bottom of the fin-formation trenches 104. To the extent the fin-formation trenches 104 are formed by performing a wet etching process, the fin-formation trenches 104 may tend to have a more rounded configuration or non-linear configuration as compared to the generally rectangular configuration of the fin-formation trenches 104 that are formed by performing an anisotropic etching process. Thus, the size and configuration of the fin-formation trenches 104, and the manner in which they are made, as well as the general configuration of the fins 106, should not be considered a limitation of the present invention. For ease of disclosure, only the substantially rectangular fin-formation trenches 104 and fins 106 will be depicted in the subsequent drawings. Moreover, the device 100 may be formed with any desired number of fins 106.
With continuing reference to
First, an anisotropic etching process was performed through the opening between the spacers 122 of the gate mask 117 to define gate trenches 136 in the material layer 112. The anisotropic etching process stops on the etch stop layer 110 and thereby exposes the etch stop layer 110 for further processing. Next, the exposed portions of the etch stop layer 110 were removed by performing an etching process. The removal of the etch stop layer 110 exposes an upper surface 106U of the fin 106 within the gate trench 136 in an area that will become the channel region 106C of the device 100. Note that, due to the nature of the anisotropic etching process, the sidewalls of the gate trenches 136 are inwardly tapered to some degree, as reflected by the angle 138, which may be about 89-86 degrees. The tapered sidewalls of the gate trench 136 will make the formation of the gate structure for the device easier and reduce the chances of the formation of undesirable voids in the gate structure. The plan view in the upper right portion of
Of course, in the example wherein separate material layers 112 are each positioned above a single active region, as depicted in the right-hand side of
Next, as shown in
As will be appreciated by those skilled in the art after a complete reading of the present application, a novel transistor device has been disclosed herein. More specifically, one embodiment of the device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material 112 positioned above at least the entire active region, a plurality of laterally spaced-apart source/drain trenches 126 formed in the layer of material 112 above the active region, a conductive source/drain contact structure 146 formed within each of the source/drain trenches 126, a gate trench 136 formed in the layer of material 112 between the spaced-apart source/drain trenches 126 in the layer of material 112, wherein portions 112X of the layer of material 112 remain positioned between the source/drain trenches 126 and the gate trench 136, a gate structure 140 positioned within the gate trench 136 and a gate cap layer 142 positioned above the gate structure 140. In the depicted example, the gate structure 140 abuts and engages the sidewalls of the gate trench 136, while each of the conductive source/drain contact structures abuts and engages the sidewalls of its corresponding source/drain trench 126.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a short-hand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A device, comprising:
- an active region defined in a semiconductor substrate;
- a layer of material positioned above said semiconductor substrate;
- first and second laterally spaced-apart source/drain trenches defined in said layer of material above said active region;
- first and second conductive source/drain contact structures positioned within said first and second laterally spaced-apart source/drain trenches, respectively;
- a gate trench formed at least partially in said layer of material between said first and second laterally spaced-apart source/drain trenches in said layer of material, wherein portions of said layer of material remains positioned between said first and second laterally spaced-apart source/drain trenches and said gate trench;
- a gate structure positioned within said gate trench; and
- a gate cap layer positioned above said gate structure.
2. The device of claim 1, wherein said device is a FinFET device and wherein said first and second laterally spaced-apart source/drain regions are each comprised of at least one fin.
3. The device of claim 1, wherein said device is a planar device and wherein said first and second laterally spaced-apart source/drain regions are each comprised of a substantially uniform layer of semiconductor material having a substantially uniform and planar upper surface.
4. The device of claim 1, wherein said gate structure is comprised of a high-k gate insulation material layer and a layer of conductive material positioned above said high-k gate insulation material layer.
5. The device of claim 1, wherein said layer of material is a material having a dielectric constant equal to or less than 7.
6. The device of claim 1, wherein said gate structure abuts and engages sidewalls of said gate trench.
7. The device of claim 1, wherein said first conductive source/drain contact structure abuts and engages sidewalls of said first source/drain trench and said second conductive source/drain contact structure abuts and engages sidewalls of said second source/drain trench.
8. The device of claim 1, wherein said gate trench is formed entirely within said layer of material.
9. The device of claim 1, wherein said layer of material is comprised of one of silicon-carbon-boron-nitride (SiBxCyN) or silicon nitride (SiN).
10. The device of claim 1, wherein each of said first and second conductive source/drain contact structures have first and second upper surfaces, respectively, wherein said first and second upper surfaces are each positioned level with or below an upper surface of said first and second laterally spaced-apart source/drain trenches, respectively.
11. The device of claim 1, further comprising first and second semiconductor material regions positioned within said first and second laterally spaced-apart source/drain trenches, respectively, and below said first and second conductive source/drain contact structures, respectively, at least a portion of said first and second semiconductor material regions being positioned at a level that is above a level of an upper surface of said semiconductor substrate.
12. A device, comprising:
- an active region defined in a semiconductor substrate;
- a layer of material positioned above said semiconductor substrate, said layer of material having a dielectric constant equal to or less than 7;
- first and second laterally spaced-apart source/drain trenches defined in said layer of material above said active region;
- first and second conductive source/drain contact structures positioned within said first and second laterally spaced-apart source/drain trenches, respectively, wherein said first conductive source/drain contact structure abuts and engages sidewalls of said first source/drain trench and said second conductive source/drain contact structure abuts and engages sidewalls of said second source/drain trench;
- a gate trench formed at least partially in said layer of material between said first and second laterally spaced-apart source/drain trenches in said layer of material, wherein portions of said layer of material remain positioned between said first and second laterally spaced-apart source/drain trenches and said gate trench;
- a gate structure positioned within said gate trench, wherein said gate structure abuts and engages sidewalls of said gate trench; and
- a gate cap layer positioned above said gate structure.
13. The device of claim 12, wherein said gate trench is formed entirely within said layer of material and wherein said gate structure abuts and engages all sidewalls of said gate trench.
14. The device of claim 12, wherein each of said first and second conductive source/drain contact structures have first and second upper surfaces, respectively, wherein said first and second upper surfaces are each positioned level with or below an upper surface of said first and second laterally spaced-apart source/drain trenches, respectively.
15. The device of claim 12, further comprising first and second semiconductor material regions positioned within said first and second laterally spaced-apart source/drain trenches, respectively, and below said first and second conductive source/drain contact structures, respectively, at least a portion of said first and second semiconductor material regions being positioned at a level that is above a level of an upper surface of said semiconductor substrate.
16. A device, comprising:
- an active region defined in a semiconductor substrate, a layer of material positioned above said semiconductor substrate;
- first and second laterally spaced-apart source/drain trenches formed in said layer of material above said active region;
- first and second conductive source/drain contact structures positioned within said first and second laterally spaced-apart source/drain trenches, respectively;
- a gate trench formed at least partially in said layer of material between said first and second laterally spaced-apart source/drain trenches, wherein first portions of said layer of material remain positioned between said first and second source/drain trenches and said gate trench above said active region and second portions of said layer of material remain positioned between said first and second source/drain trenches and said gate trench outside of said active region, wherein said second portions of said layer of material are thicker in a gate length direction of said device than are said first portions of said layer of material; and
- a gate structure positioned within said gate trench, wherein a first portion of sidewalls of said gate structure are positioned adjacent said first portions of said layer of material and a second portion of said sidewalls of said gate structure are positioned adjacent said second portions of said layer of material.
17. The device of claim 16, wherein said layer of material is a material having a dielectric constant equal to or less than 7.
18. The device of claim 16, wherein said gate structure abuts and engages said first and second portions of said layer of material.
19. The device of claim 16, wherein said first conductive source/drain contact structure abuts and engages sidewalls of said first source/drain trench and said second conductive source/drain contact structure abuts and engages sidewalls of said second source/drain trench.
20. The device of claim 16, wherein said gate trench is formed entirely within said layer of material.
21. The device of claim 16, wherein each of said first and second conductive source/drain contact structures have first and second upper surfaces, respectively, wherein said first and second upper surfaces are each positioned level with or below an upper surface of said first and second laterally spaced-apart source/drain trenches, respectively.
22. The device of claim 16, further comprising first and second semiconductor material regions positioned within said first and second laterally spaced-apart source/drain trenches, respectively, and below said first and second conductive source/drain contact structures, respectively, at least a portion of said first and second semiconductor material regions being positioned at a level that is above a level of an upper surface of said semiconductor substrate.
Type: Application
Filed: Aug 11, 2015
Publication Date: Dec 3, 2015
Inventors: Ruilong Xie (Niskayuna, NY), William J. Taylor, JR. (Clifton Park, NY), Ryan Ryoung-Han Kim (Albany, NY)
Application Number: 14/823,226