ASSIST ENGINE FOR TRANSMIT AND RECEIVE FUNCTIONS IN A MODULAR WIRELESS NETWORK ACCESS DEVICE
A wireless network access device comprising a radio interface with a serial communication line, a switch, and M serial connections to M connectors for connecting up to M corresponding detachable radio modules. The radio interface forms up to M individually addressable radio communications paths. Each radio module includes a radio configured to communicate with client devices in a coverage area and a radio processor configured to manage at least one radio receiving buffer. The radio receiving buffers store receiver buffer identifiers to corresponding received data space. A processor manages communication between the client devices that communicate with the radio modules and a data network via the radio interface and a network interface when N≦M radio modules are connected to the radio interface. An assist engine is connected in the serial connection between the processor and the switch to manage allocation of receive buffer identifiers to the radio modules.
This application claims priority of U.S. Provisional Application Ser. No. 61/544,942, titled “Modular Wireless Network Array Having Transmit/Receive Assist Functions,” filed on Oct. 7, 2011, which is incorporated by reference herein in its entirety.
Reference is made to U.S. Provisional Application Ser. No. 61/521,218, titled “Modular Wireless Network Array,” filed on Aug. 9, 2011, the contents of which are incorporated by reference herein.
Reference is made to U.S. patent application Ser. No. 13/566,711, titled “Modular Wireless Network Access Device,” filed on Aug. 3, 2012, which is incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates generally to systems and methods for providing wireless networking resources and more particularly to, modular wireless networking that include radio packet transmission and reception performance enhancement.
2. Related Art
The use of wireless communication devices for data networking is growing at a rapid pace. Data networks that use “WiFi” (“Wireless Fidelity”), also known as “Wi-Fi,” are relatively easy to install, convenient to use, and supported by the IEEE 802.11 standard. WiFi data networks also provide performance that makes WiFi a suitable alternative to a wired data network for many business and home users. Wireless communications for data networks also include using the cellular telephone and mobile communications infrastructure. The use of Bluetooth® and other standards implementing a wide variety of wireless technologies is also growing.
In WiFi networks, wireless access points provide users having wireless (or “client”) devices in proximity to the access point with access to data networks. The wireless access points include a radio that operates according to different aspects of the IEEE 802.11 specification. Generally, radios in the access points communicate with client devices by utilizing omnidirectional antennas that allow the radios to communicate with client devices in any direction. The access points are then connected (by hardwired connections) to a data network system, which completes the access of the client device to the data network.
WiFi access points typically include a single omnidirectional radio that communicates with the clients in proximity to the access point. Recently, WiFi systems have incorporated multiple radios with an integrated controller connected to a LAN, or other data network infrastructure. Examples of such multiple radio WiFi systems are disclosed in:
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- U.S. patent application Ser. No. 11/816,003, filed on Aug. 10, 2007, titled “Wireless LAN Array,” and incorporated herein by reference in its entirety;
- U.S. patent application Ser. No. 11/816,060, filed on Aug. 10, 2007, titled “Assembly and Mounting for Multi-Sector Access Point Array,” and incorporated herein by reference in its entirety;
- U.S. patent application Ser. No. 11/816,061, filed on Aug. 10, 2007, titled “Media Access Controller for Use in a Multi-Sector Access Point Array,” and incorporated herein by reference in its entirety;
- U.S. patent application Ser. No. 11/816,064, filed on Apr. 3, 2008, titled “Antenna Architecture of a Wireless LAN Array,” and incorporated herein by reference in its entirety;
- U.S. patent application Ser. No. 11/816,065, filed on Aug. 10, 2007, titled “System for Allocating Channels in a Multi-Radio Wireless LAN Array,” and incorporated herein by reference in its entirety.
WiFi access points that employ multiple radios use radios specifically configured for operation in the specific WiFi access point implementation. The multiple radios are also provided as multiple radio chains in a single structure, or in multiple modules in which single radios do not operate or may not be removed or added independently of each other. As such, the access points lack the flexibility to use independently configured radios, or technologies.
There is a need for wireless networking solutions that allow control over radios that operate independently without any functional or physical dependency on other radios, interchangeably to allow radios to be replaced with other radios in an implementation, and differently using different standards or variations of standards or technologies.
SUMMARYA wireless network access device comprising a radio interface with a serial communication line, a switch, and M serial connections to M connectors for connecting up to M corresponding detachable radio modules. The radio interface forms up to M individually addressable radio communications paths. Each radio module includes a radio configured to communicate with client devices in a coverage area and a radio processor configured to manage at least one radio receiving buffer. The radio receiving buffers store receiver buffer identifiers to corresponding received data space. A processor manages communication between the client devices that communicate with the radio modules and a data network via the radio interface and a network interface when N≦M radio modules are connected to the radio interface. An assist engine is connected in the serial connection between the processor and the switch to manage allocation of receive buffer identifiers to the radio modules.
The examples of the invention described below can be better understood with reference to the following figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.
In the following description of example embodiments, reference is made to the accompanying drawings that form a part of the description, and which show, by way of illustration, specific example embodiments in which the invention may be practiced. Other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.
I. OverviewExamples of modular wireless network platforms are described below as wireless network arrays that may be implemented in a circular housing having a plurality of radial sectors and a plurality of antennas arranged to provide coverage in the radial sectors. One or more of the plurality of antennas may be arranged within individual radial sectors of the plurality of radial sectors.
The radial sectors may be configured to define radiation patterns, or coverage patterns, that cover airspace in targeted sections, or sectors. The coverage patterns may be configured in a manner that, when combined, a continuous coverage is provided for a client device that is in communication with the wireless network array. The radiation patterns may overlap to ease management of a plurality of client devices by allowing adjacent sectors to assist each other. For example, adjacent sectors may assist each other in managing the number of client devices served with the highest throughput as controlled by an array controller. The arrangement of antennas in radial sectors provides increased directional transmission and reception gain that allow the wireless network array and its respective client devices to communicate at greater distances than standard omnidirectional antenna systems, thus producing an extended coverage area when compared to an omnidirectional antenna system.
The antennas used in the radial sectors may include any suitable number and type of antenna in each sector. Examples of antenna arrays that may be used are described in:
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- PCT Patent Application No. PCT/US2006/008747, filed on Jun. 9, 2006, titled “WIRELESS LAN ANTENNA ARRAY,” and incorporated herein by reference in its entirety,
- U.S. patent application Ser. No. 12/269,567 filed on Nov. 12, 2008, titled “MIMO Antenna System,” and incorporated herein by reference in its entirety,
- U.S. patent application Ser. No. 12/987,040 (“'040”) filed on Dec. 31, 2010, titled “MIMO Antenna System,” and incorporated herein by reference in its entirety, and
- U.S. patent application Ser. No. 13/115,091 (“'091”) filed on May 24, 2011, titled “MIMO Antenna System having Beamforming Networks,” and incorporated herein by reference in its entirety.
For purposes of maintaining clarity in the description of the example wireless network arrays below, the antennas in the examples are described as employing multiple input, multiple output (“MIMO”) schemes. It is to be understood by those of ordinary skill in the art that example implementations are not limited to the type of antennas described.
The examples of wireless network access devices described below include independently operating radio modules in each radial sector. The radio modules may provide a coverage pattern as described above, or each radio module may be configured to generate independent coverage patterns, which may include directional or omni-directional radiation patterns. The number of radio modules used in the wireless network access device may also be varied and various different radio module types may be combined to provide scalability of performance, cost, and diversity of functionality in any given implementation.
II. Modular Wireless Network ArrayThe radio interface 212 is configured to connect the radio modules 204a-204p to data network resources as individual, independently operating radios configured to communicate with client devices in the radial sector in which the radios operate. Each radio module 204a-204p includes a single radio operating independently of the other radio modules 204a-204p. For example, one or more radio modules 204a-204p may be configured to operate as 3×3 1.11n radios, others may be configured to operate as 2×2 802.11n radios, others may have a single antenna chain, and others may be configured to communicate with cellular devices. One or more of the radio modules 204a-204p may also be configured to operate with an omnidirectional coverage pattern while one or more of the remaining radio modules 204a-204p may operate with a directional coverage pattern in the same installation. Each radio module 204a-204p includes an interface configured to operate with the radio interface 212 on the controller 202.
In one example implementation, the radio interface 212 operates using the standard PCI Express® (“PCIe®”) peripheral interface. The radio interface 212 on the controller 202 communicates with each radio module 204a-204p connected to the controller 202 in accordance with the PCIe® standard. The radio interface 212 manages serial links to each radio module in accordance with the PCIe® standard. The PCIe® standard is not intended to be limiting. It is to be understood by those of ordinary skill in the art that any interface, whether standard or proprietary, may be used for communication to the radio modules 204a-204p.
The network interface 214 provides the radio modules 204a-204p with access to the data network resources allowing client devices in communication with the radio modules 204a-204p to communicate over data networks such as the Internet. Any suitable scheme may be used for the network interface 214, which may include hardware and software components that allow connectivity for a variety of radio types, including WiFi radios, cellular radios, and any other radio configured for operation in the wireless network access device 200 in
The wireless network access devices 100, 200 shown in
In an example implementation, the central processor 302 may include built-in interfaces and connections for any of the network interface 306 and the radio interface in accordance with selected standards. For example, the central processor 302 in the controller 300 in
The controller 300 includes other processor support components, such as for example, a non-volatile memory 318, including for example, a boot ROM and a USB FLASH drive interface. The controller 300 may include other support components 316, such as for example, a clock, EPROM, and a temperature sensor. An auxiliary processor 330 may also be included to offload housekeeping or administrative functions (such as watchdog) from the central processor 302. An integrated interface control bus 324 may also be included to allow the central processor 302 to address processing peripherals, such as the supporting processing components including the EPROM at 316, the auxiliary processor 330, and the assist engine 312 by software functions programmed to access the components. These support components, the integrated interface control bus and auxiliary processors are optional or basic computing equipment components that require no further discussion.
The central processor 302 in
One of the two radio interface paths 322a, 322b may connect directly to the signal switch 308. The other radio interface path 322a, 322b may include an assist engine 312 operating in-line, or as a “look-aside” component for performing functions that assist the operation of the controller 300. These operations may provide boosts in performance, the ability to test performance, or other operation assisting functions. The signal switch 308 couples the selected radio interface path 322a, 322b to a single interface link 325 connected to the fanout device 310.
The radio path fanout device 310 connects the single two-lane interface link 325 to one of up to 8 single lane radio paths 326. The 8 single lane radio paths 326 extend to corresponding connectors on the controller 300 as illustrated in the controller 102 in
In an example implementation, the central processor 402 may include built-in interfaces and connections for any of the network interface 406 and the radio interface in accordance with selected standards. For example, the central processor 402 in the controller 400 in
The controller 400 may include other processor support components similar to the controller 300 in
Similar to the central processor 302 in
It is noted that the described examples of radio interface paths 322a, 322b (with reference to
One of the two radio interface paths 422a, 422b may connect directly to the signal switches 408a, 408b. Each switch 408a, 408b connects corresponding pairs of the multiple lanes that form the radio interface paths 422a, 422b. A single switch block that accommodates the four lanes may also be implemented. The other radio interface path 422a, 422b may include an assist engine 412 operating in-line, or as a “look-aside” component for performing functions that assist the operation of the controller 400. These operations may provide boosts in performance, the ability to test performance, or other operation assisting functions. The signal switches 408a, 408b couple the selected radio interface path 322a, 322b to a single four lane interface link 425 connected to the fanout device 310.
The radio path fanout devices 410a, 410b connects the single four-lane interface link 425 to one of up to 16 single lane radio paths 420a and 420b. Each radio path fanout device 410a, 410b connects to a corresponding group of 8 radio paths 420a, 420b. The 16 single lane radio paths 426 extend to corresponding connectors on the controller 400 as illustrated in the controller 202 in
The wireless network access devices 100, 200 shown in
The modularity provided by the radio module platform facilitates a system configuration and provides flexibility using easily interchangeable radio modules. This flexibility in the choice of radio technology may remain throughout the lifetime of the system and may even expand the flexibility available for enhancing system operation via field upgrades. Future radio modules may be designed using increasingly powerful chipsets that may be designed on to the radio module platform and inserted into the system as required.
The size and shape of the radio module also allow for the inclusion of the antennas directly onto the module. While different radio modules would most likely have different antennas (in terms of geometry, layout, and type of channel formed), space on the radio module allows them to be included directly on the module. In other example implementations, antennas could be off-board and adapted to connect using cable assemblies.
The electrical interface to the radio module from the controller (such as 102, 202 in
In configuring a modular wireless network access device, radio modules may be adapted to:
- 1) Operate with an integrated wireless LAN AP/Controller with embedded, directionalized antenna systems that may be used in multiple product platforms.
- 2) Include multiple antenna systems suited for operation under platform specific requirements.
- 3) Mate electrically to the central processing unit through a PCI Express or other standardized interface protocols.
- 4) Mate mechanically to the central processing unit with a combination of a standardized connector and custom latching system.
The first spatial stream 504 and second spatial stream 506 include corresponding first and second antennas 505, 507. In an example implementation of the radio board 500, the first and second antennas 505, 507 may be configured to operate as described in the '040 and the '091 applications listed above. The first and second antennas 505, 507 each connect to tx/rx switches 510, 512, respectively in
Each tx/rx switch 510, 512 connects to diplexers that multiplex or demultiplex data over two lanes in each spatial stream 504, 506. In an example implementation, the diplexers switch the bandwidth of the radio operation between different radio bands. For example, the radio 500 in
The chain 0 transmitter diplexer 516a multiplexes the data received from parallel transmitting paths at outputs of a first and second chain 0 power amplifier 532a, 532b and outputs the multiplexed signal to the first transmit/receive (“tx/rx”) switch 510 for transmitting data wireless via the antenna 505 when switched to transmit. The first and second chain 0 power amplifiers 532a, 532b receive analog RF signals configured by the radio board processor 502 for wireless transmission pursuant to a selected specification understood by a client device to which the RF signals are directed. The analog RF signals are output by the radio board processor 502 on a pair of chain 0 transmitting lanes 542 connected to the first and second chain 0 power amplifiers 532a, 532b.
With respect to the second chain, chain 1, the second tx/rx switch 512 connects to a chain 1 receiver diplexer 514b for receiving data from the antenna 507, and a chain 1 transmitter diplexer 516b for transmitting data. The chain 1 receive diplexer 514b receives data from the second antenna 507 via the tx/rx switch 512 (when triggered to receive data). The chain 1 diplexer 514b demultiplexes the data received from the second antenna 507 for output along parallel paths having a first and second chain 1 low noise amplifier 530c, 530d. The first and second chain 1 low noise amplifiers 530c, 530d output received signals along respective chain 1 receiving lanes 546 to the radio board processor 502. The chain 1 receiving lanes 546 communicate analog RF signals that are processed by the radio board processor 502 consistent with the specifications under which the signal was communicated.
The chain 1 transmit diplexer 516b multiplexes the data received from parallel transmitting paths at outputs of a first and second chain 1 power amplifier 532c, 532d and outputs the multiplexed signal to the second tx/rx switch 512. The first and second chain 1 power amplifiers 532c, 532d receive analog RF signals configured by the radio board processor 502 for wireless transmission pursuant to a selected specification understood by a client device to which the RF signals are directed. The analog RF signals are output by the radio board processor 502 on a pair of chain 1 transmitting lanes 548 connected to the first and second chain 1 power amplifiers 532c, 532d.
The three spatial streams 604, 606, 608 include corresponding first, second and third antennas 605, 607, 609. In an example implementation of the radio board 600, the three antennas 605, 607, 609 may be configured to operate as described in the '040 and the '091 applications listed above. The three antennas 605, 607, 609 each connect to corresponding tx/rx switches 610, 612, 614, respectively in
Each tx/rx switch 610, 612, 614 connects to diplexers that multiplex or demultiplex data over two lanes in each spatial stream 604, 606, 608. For example, the first tx/rx switch 610 connects to a chain 0 receiver diplexer 616a for receiving data, and a chain 0 transmitter diplexer 618a for transmitting data. The chain 0 receiver diplexer 616 a receives data from the first antenna 605 via the tx/rx switch 610 (when triggered to receive data). The chain 0 receiver diplexer 616a de-multiplexes the data received from the first antenna 605 for output along parallel paths or lanes, each lane having a first and second chain 0 low noise amplifier 620a, 620b. The first and second chain 0 low noise amplifiers 620a, 620b output the received signals along respective chain 0 receiving lanes 630 to the radio board processor 602. The chain 0 receiving lanes 630 communicate analog RF signals that are processed by the radio board processor 602 consistent with the specifications under which the signal was communicated.
The chain 0 transmitter diplexer 618a multiplexes the data received from parallel transmitting paths or lanes at outputs of a first and second chain 0 power amplifier 622a, 622b and outputs the multiplexed signal to the first tx/rx switch 610 for transmitting data wireless via the antenna 605 when switched to transmit. The first and second chain 0 power amplifiers 622a, 622b receive analog RF signals configured by the radio board processor 602 for wireless transmission pursuant to a selected specification understood by a client device to which the RF signals are directed. The analog RF signals are output by the radio board processor 602 on a pair of chain 0 transmitting lanes 632 connected to the first and second chain 0 power amplifiers 622a, 622b.
With respect to the second chain, chain 1, the second tx/rx switch 612 connects to a chain 1 receiver diplexer 616b for receiving data from the antenna 607, and a chain 1 transmitter diplexer 618b for transmitting data. The chain 1 receive diplexer 616b receives data from the second antenna 607 via the tx/rx switch 612 (when triggered to receive data). The chain 1 diplexer 616b demultiplexes the data received from the second antenna 607 for output along parallel paths or lanes having a first and second chain 1 low noise amplifier 620c, 620d. The first and second chain 1 low noise amplifiers 620c, 620d output received signals along respective chain 1 receiving lanes 634 to the radio board processor 602. The chain 1 receiving lanes 634 communicate analog RF signals that are processed by the radio board processor 602 consistent with the specifications under which the signal was communicated.
The chain 1 transmit diplexer 618b multiplexes the data received from parallel transmitting paths or lanes at outputs of first and second chain 1 power amplifiers 622c, 622d and outputs the multiplexed signal to the second tx/rx switch 612. The first and second chain 1 power amplifiers 622c, 622d receive analog RF signals configured by the radio board processor 602 for wireless transmission pursuant to a selected specification understood by a client device to which the RF signals are directed. The analog RF signals are output by the radio board processor 602 on a pair of chain 1 transmitting lanes 636 connected to the first and second chain 1 power amplifiers 622c, 622d.
With respect to the third chain, chain 2, the third tx/rx switch 614 connects to a chain 2 receiver diplexer 616c for receiving data from the antenna 609, and a chain 2 transmitter diplexer 618c for transmitting data. The chain 2 receiver diplexer 616c receives data from the third antenna 609 via the tx/rx switch 614 (when triggered to receive data). The chain 2 diplexer 616c demultiplexes the data received from the third antenna 609 for output along parallel paths or lanes having a first and second chain 2 low noise amplifier 620e, 620f. The first and second chain 2 low noise amplifiers 620e, 620f output received signals along respective chain 2 receiving lanes 638 to the radio board processor 602. The chain 2 receiving lanes 638 communicate analog RF signals that are processed by the radio board processor 602 consistent with the specifications under which the signal was communicated.
The chain 2 transmit diplexer 618c multiplexes the data received from parallel transmitting paths or lanes at outputs of first and second chain 2 power amplifiers 622e, 622f and outputs the multiplexed signal to the third tx/rx switch 614. The first and second chain 2 power amplifiers 622e, 622f receive analog RF signals configured by the radio board processor 602 for wireless transmission pursuant to a selected specification understood by a client device to which the RF signals are directed. The analog RF signals are output by the radio board processor 602 on a pair of chain 2 transmitting lanes 640 connected to the first and second chain 2 power amplifiers 622e, 622f.
The radio boards 500 and 600 shown in
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- Antenna configuration (i.e. SISO, 2×2 MIMO, 2×3 MIMO, 3×3 MIMO, etc)
- Antenna types
- Directional vs Omnidirectional
- Various chip suppliers
- Qualcomm, Intel, Broadcom, Marvel, etc.
- Differing transmit power capabilities
- Internal vs. External power amplifiers
- Different types of RF technologies
- WiFi
- 802.11 a/b/g/n/ac/ad
- Cellular
- UMTS
- HSPA
- LTE
- Bluetooth®
- WiFi
It is noted that the above description is not intended to be limiting in view of references to specific standards and known configurations. Rather, the modularity and flexibility provided by the radio module platforms enhances the variety of systems that may be configured.
It is also noted that example implementations of the radio modules 500 and 600 described with reference to
V. High-Speed Radio Module Interface with In-Line Processing
A. Intelligent High-Speed Radio Module Interface
The second radio path fanout device 708 may include a fanout device coupling 770 to the first radio path fanout device 706. The fanout device coupling 770 may be a four lane link configured to permit any of the up to eight radio modules 728 connected to the second radio path fanout device 708 to connect via the first radio path fanout device 706 to the controller processor 702. The connections from the first radio path fanout device 706 to the first group of radio modules 726 may include 8 1×1 links forming 8 single lane links that are connected to one of the two four-lane links, which are the radio interface paths 720a, 720b. The second radio path fanout device 708 may also include four single lane links at 780 connected to corresponding external output ports in the external device interface 750.
The example illustrated in
In an example implementation, the assist engine 710 may be a field-programmable gate array (“FPGA”) programmed with any suitable or desirable assisting function. In general, the radio interface paths 720a, 720b may be configurable by control software operating under control of the controller processor 702 to select between the two paths 720a, 720b. The controller processor 702 may select between the first radio interface path 720a having a direct connection to the controller processor 702 and the second radio interface path 720b with the assist engine 710 inserted into the path 720b. The assist engine 710 may be used to process data and/or control traffic in-line with the radio processing path 720b (“in-line processing” functions), as look-aside hardware assist engines (“look-aside processing” functions) for the controller processor 702, or as an auxiliary processor that controls communication between the controller processor 702 and one or more external devices connected to the external device interface 750.
The assist engine 710 may perform a variety of functions depending on the use case of the wireless network access device (such as 200 in
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- Counting data packets
- Inspecting packets for specific content and then acting on what it finds (like setting an interrupt for example).
- Queuing data traffic
- Policing data traffic
- Memory address checking
Functions that may be implemented with look-aside processing include the following:
-
- Encryption/Decryption
- Frame aggregation/de-aggregation
- Packet parsing
- Frame translation
The assist engine 710 may include functions that use the connections 780 to the external device interface 750 for any suitable purpose. For example, the four device connections in the external device interface 750 may be used to connect to one or more external radio modules 782. The external radio modules 782 may be configured in a variety of ways. For example, the external radio module 782 may be any radio module having at least an electrical interface configured to communicate with the controller 700. The external radio module 782 may or may not have the same form factor that would allow it to operate as one of the radio modules 726, 728 configured to operate with the controller 700. The external radio module 782 may be used to provide a specialized link to specially selected clients, or clients located in a specific area. The external radio module 782 may also implement a different type of wireless communication link than the radio modules 726, 728 configured to operate with the controller 700. In another example, the external radio module 782 may not be a ‘radio’ module, but rather a wireless connection using a different type of wireless signal, such as infrared, laser, any optical, any electromagnetic other than radio, or any other type of wireless signal. The external radio module 782 may be implemented to expand functions, capacity, or performance, or to provide diagnostic testing.
B. High-Speed Radio Module Interface Bridge
The assist engine 710 shown in
The interface bridge having in-line data processing 820 also includes a first internal interface bridge 822 and a second internal interface bridge 824, but with an in-line data processing function 850 operating between the first and second interface bridges 822, 824 over an internal bus 860. The in-line data processing function 850 may be configured to perform any desired function. The in-line data processing function 850 intercepts the communications traffic from the external interfaces and may perform functions on the intercepted data. Examples of the types of functions that may be performed on the data include:
-
- Counting data packets
- Inspecting packets for specific content and then acting on what it finds (like setting an interrupt for example).
- Queuing data traffic
- Policing data traffic
The interface bridge 820 with internal processing may be implemented in either custom silicon such as a standard cell chip or programmable silicon such as an FPGA.
C. Transmit/Receive Assist Functions
The assist engine 710 in
The controller processor 702 and the radio modules 726, 728 in
1. Assist Engine for Data Reception
The radio modules 908a-n include a plurality of radio receiving buffers 910a-n. In the example shown in
The radio receiving buffers 910a-n may be implemented as first in, first out (FIFO) buffers in which pointers, or other suitable information access elements, are stored. The controller may provide the radio module 908a-n with the information access elements for storage in the radio receiving buffers 910a-n. The controller and radio modules 908a-n may also be configured to permit direct access from the controller processor 902 on the controller to the radio receiving buffers 910a-n on the radio modules 908a-n. The information access elements may be added to the radio receiving buffers 910a-n as needed. The radio modules 908a-n receive data from client devices as signals over wireless connections. The radio processors in the radio modules 908a-n process the signals as data packets formatted for storage and eventual use by the controller processor 902 in the controller. The radio processors obtain an information access element, typically a pointer to a data storage space, from the radio receiving buffers 910a-n. When an information access element is obtained from a radio receiving buffer, the element is taken off the radio receiving buffer 910a-n leaving the radio receiving buffer 910a-n with one fewer storage options. The controller processor 902 in the controller is tasked with replacing the information access element. In a given radio receiving buffer 910-n, the information access elements may be removed successively at a high rate when experiencing a high level of data traffic at a given radio. The controller processor 902 may not be able to replace the used information access elements particularly when the controller processor 902 is operating with a large number of radio modules.
The assist engine 904 may be configured as shown in
The assist engine 904 provides in-line processing between the controller processor 902 and the radio modules 908a-n. The assist engine 904 receives information access elements from the controller processor 902 for storage in the AE receiving queues 914, and provides information access elements to the radio modules from the AE receiving queues 914. The assist engine 904 may be further configured to monitor the status of the radio receiving buffers 910, which allows the assist engine 904 to determine when to provide information assist elements to the radio modules. When data traffic is high, the assist engine 904 may provide the information access elements more quickly than the controller processor 902, which helps ensure that the radio receiving buffers do not reach an empty state.
The controller processor 902 supplies information access elements to the assist engine 904 while allocating data storage in system memory 912 for the data received by the radio modules 908. The information access elements may provide information for accessing selected data buffers 916a-n, which may be allocated as multiple storage areas for each radio. The information access elements may be pointers, or other data structures that may include a pointer to the buffers 916a-n. When a radio reads or removes an information access element from the radio receiving buffer, the radio stores the received data packet(s) in the data buffer 916 corresponding to, or pointed to, by the information access element.
The AE receiving queues 914a-n and the management of the AE receiving queues 914a-n by the assist engine 904 may be implemented in a variety of ways.
-
- 1. Queues 914a-n are implemented as linked lists.
- 2. An information access element is a “SKB,” or “socket buffer,” which is known to those of ordinary skill in the art as a type of data storage element.
FIG. 9C shows examples of data structures that may be used in implementing an example of the method described with reference toFIG. 9B .FIG. 9C includes diagrams illustrating examples of data structures for an SKB 930, a receiver linked list element 940, and a receiver linked list status block 950.
The SKB 930 shown in
The AE receiving queues 914a-n may be created by any available processing unit, which includes the controller processor 902 and the assist engine 904. In an example implementation, the AE receiving queues 914a-n are created by the controller processor 902 and managed by the assist engine 904. For each radio module 908, each radio receiving buffer 910 has a corresponding AE receiving queue 914 managed by the assist engine 904. For example, if radio 1 908a uses two radio receiving buffers 910a, the assist engine 904 maintains two AE receiving queues 914a, one AE receiving queue 914a for each radio receiving buffer 910a. Each AE receiving queue 914 may store elements such as a AE receiving queue element 940 shown in
The AE receiving queue element 940 includes a flags field having 2 bits. In the illustrated example, the two bits are defined as the end-of-list (EOL) detected bit and the receive-done bit. The EOL bit may be set by the assist engine 904 when a null link pointer is encountered to indicate that the end of the linked list has been reached. The EOL flag bit may be used to empirically determine how long the linked list needs to be to avoid the EOL condition. The assist engine 904 may be configured to set the receive-done bit in a given linked list element to indicate that the assist engine 904 has determined that a packet is fully buffered in the SKB 930 that is associated with the AE receiving queue element 940.
The assist engine 904 monitors the status of the AE receiving queues 914 and uses the receiver linked list status block 950 to track the state of packet reception for a corresponding AE receiving queue 914. The receiver linked list status block 950 includes the following status elements:
-
- 1. a radio head pointer 952, which identifies the AE receiving queue element 940 corresponding to the SKB 930 allocated to store the next packet received by the radio.
- 2. a RAE head pointer 954, which identifies the AE receiving queue element 940 corresponding to the next SKB 930 that will be used by the radio for storage in the radio receiving buffer 910.
- 3. a depth field 956, which indicates the number of SKBs that are currently stored in the receiver data buffer 910.
- 4. a current SKB pointer 958, which identifies the SKB 930 allocated to store the next packet received by the radio.
The assist engine 904 monitors the status of the data reception by polling, snooping, or performing other suitable state-tracking mechanisms to track the accesses to the SKB identified in the current SKB pointer 958 in order to determine when the data- and descriptor-writes are complete. The completion of the data- and descriptor-writes triggers the assist engine 904 to set, or write, the receive-done bit in the corresponding AE receiving queue element 940 (for example, the linked list element identified in the radio head pointer 954) and to write the next available SKB (given in the RAE head) to the radio receiving buffer 910.
Referring to
The example shown in
On the controller side 980, the storage of the received packet in ‘SKB2’ is reflected at 976. The assist engine 904 manages the receive linked list elements stored in the radio 1 AE receiving queue 914-1. The radio 1 AE receiving queue 914-1 includes the following AE receiving queue elements:
-
- AE receiving queue Element: SKB2—a linked list element corresponding to SKB2,
- AE receiving queue Element: SKB1—a linked list element corresponding to SKB1,
- AE receiving queue Element: SKB0—a linked list element corresponding to SKB0,
- AE receiving queue Element: SKB (next to buffer)—a linked list element corresponding to the next SKB to be put in radio data buffer,
- AE receiving queue Element
It is to be understood by those of ordinary skill in the art that the state of the data structures shown in
Given the state reflected by the values of the linked list status block 950 shown in Table 1, the receiver linked list element 974 in this example is the current linked list element as indicated by the Radio Head Pointer. The current linked list element 974 corresponds to SKB2, which is the SKB that the radio module 908a will use, or is using, for storing the received data packet 970. The current linked list element 974 is linked to the next linked list element, which is the element labeled ‘AE receiving queue Element: SKB1.’ The link to AE receiving queue Element: SKB1 is indicated in the link field 942 (in
The RAE Head Pointer in the linked list status block 950 shown in Table 1 is a pointer to AE receiving queue Element: SKB (next to buffer), which is the linked list element corresponding to the next SKB to be added to the radio receiving buffer 910-1 on the radio side 990. The Radio Buffer Depth is set to 3 to indicate that @SKB0, @SKB1, and @SKB2 are stored in the radio receiving buffer 910-1 of radio 1 908a. The Current SKB Pointer is @SKB2 to indicate that the next radio packet will be, or is being, stored in SKB2.
The assist engine 904 monitors the status of the SKB 916 by polling or snooping, or otherwise checking whether the storage of the received data has completed. The assist engine 904 may monitor the status by detecting when the descriptor field 932 of the current SKB 974 (‘SDB2’ as indicated by the current SKB pointer in Table 1) has been written. While checking for completion of the storage of the received data, the assist engine 904 determines the next linked list element corresponding to the next SKB to be used by the radio 1 908a for the next packet by referring to the link field 942 (in
When the storage of the received packet data in SKB2 has completed, the assist engine 904 sets the Receive-Done bits at 904 (in
The assist engine 904 also determines the next SKB pointer to add to the radio receiving buffer 910-1 of the radio module 908a by reference to the link field 942 (in
It is noted that if the assist engine 904 is not generating a sufficiently long linked list, an End-Of-List condition may be detected when the link field value of the linked list element identified by the RAE Head Pointer is null. This condition may be avoided by prior testing and analysis of the performance of the system to adjust the number and size of buffers and queues used for receiving data. It is noted as well that the Radio FIFO Depth value in the linked list status block 950 did not change when a new SKB was added pursuant to the removal of an SKB. Depending on the amount of data being received by the radio module 908a at any given time, the assist engine 904 may be able to provide SKBs to the radio module 908a as the radio module 908auses the SKBs in the radio receiving buffer, thus keeping the Radio FIFO Depth consistently unchanged. In an example implementation, the assist engine 904 fills the radio receiving buffers 910 with SKBs during initialization of the system 900 before data reception and transmission has begun ensuring that the radio receiving buffers 910 can be filled before data can be received. After the system 900 has initialized, each radio module 908a-n is serviced in a round robin fashion. If the assist engine 904 detects that a packet was received into an SKB, a new SKB is added to the radio receiving buffer 910 to replace it in the same round-robin interval assuming the end of the linked list has not been reached. In the example implementation, one packet is processed per radio in each roundrobin interval, and the round-robin interval determines the maximum rate at which SKBs can be provided to the radio receiving buffers 910a-n. In periods of high input traffic to the radio module 908a, the Radio FIFO Depth may decrease. By selecting suitable buffer and queue sizes, the likelihood of emptying any one radio receiving buffer 910 may be minimized
2. Assist Engine for Data Transmission
The radio modules 908a-n include a plurality of radio transmit buffers 960a-n. In the example shown in
The assist engine 904 manages multiple assist engine (“AE”) transmit queues 964a-n per radio module 908a-n. The assist engine 904 manages the AE transmit queues 964a-n with the objective of keeping each FIFO radio transmit buffer 960a-n in non-empty state as long as there are packets available to send.
In operation, the controller processor 902 configures data packets to transmit to client devices being serviced by the radio modules 908a-n as data to transmit 954. The data to transmit 954 is communicated over the PCIe bus connection to the switch 906 where it is subject to in-line processing by the assist engine 904. The assist engine 904 configures AE transmit queues 96a-n corresponding to elements of the data to transmit 954. For example, the data to transmit 954 may be provided a packet at a time, or multiple packets at a time, which may be stored in memory. Information about the packets, which may include the memory location in which they are stored, their destination, their size, their priority, and any other suitable information, may be provided or packaged by the assist engine 904 as “control descriptors.” The control descriptors are the elements of data that are stored in the radio transmit buffers 960a-n where they wait to be retrieved and transmitted by the radio module 908a-n. A control descriptor may correspond to data packets provided as “aggregate packets,” which are, for example, multiple MAC layer packets with a single PHY header. The control descriptor for aggregate packets may point to additional control descriptors that also point to data packets.
The assist engine 904 provides the control descriptors to the radio for storage on the radio transmit buffers 960a-n providing the radio module 908a-n with information (such as a pointer) regarding the data to be transmitted. The process of managing the AE transmit queues 964a-nto provide control descriptors to keep the radio transmit buffers 960a-n in a non-empty state may be implemented by the assist engine 904 using a plurality of data structures. Examples of data structures that may be used by the assist engine 904 are described with reference to
Referring to
In operation, when an available AE transmit queue element, which may have a structure described below with reference to
When there are no linked list AE transmit queue elements in the AE transmit queue, and a new element is added, the backlog bit is set and the AE transmit queue pointer becomes the beginning of the linked list that forms the AE transmit queue. If only one AE transmit queue element in the linked list of the corresponding AE transmit queue is used, the backlog bit is set and then cleared as soon as the last AE transmit queue element is removed from the AE transmit queue.
Referring to
The assist engine 904 may manage a status ring having the status ring structure 1040 in
At initialization, the start pointer 1042 and current pointer 1046 are set to the same value and address the same sub-block. When transmit completion status is written to the current pointer 1046, the current pointer 1046 is incremented by the size of the sub-blocks (for example, 9 dwords). When the current pointer 1046 and end pointer 1044 become equal and transmit completion status is written to the area indicated by the current pointer 1042 (and end pointer 1044 in this case), the current pointer 1046 will be set back to the start pointer 1042.
Referring to
The radio transmit buffer depth state 1060 is used by the assist engine 904 to keep track of the queue depths of each radio transmit buffer 960. The radio transmit buffers 960 in an example implementation store a maximum of 8 control descriptors in each of the 10 radio transmit buffers 960. The assist engine increments the depth of a given radio transmit buffer 960 when a control descriptor is pushed on to the radio transmit buffer 960. When transmit complete status is received from the radio module 908 for that same radio transmit buffer 960, the assist engine 904 decrements the queue depth in the slot in the transmit buffer depth state 1060 that corresponds to the given radio transmit buffer 960. The assist engine 904 will not push additional control descriptors on to a radio transmit buffer 960 that already has a maximum number of control descriptors outstanding.
It is noted that the AE transmit queues 964 are managed to ensure that the radio transmit buffers 960 are not empty of control descriptors as long as the controller processor 902 has packets to send for the corresponding radio module 908. If there are no packets to send via a given radio module 908, the radio transmit buffer 960 for that radio module 908 may be empty and there may be no linked list elements in the AE transmit queue 964 corresponding to the empty radio transmit buffers 960. When a substantial number of data packets are prepared by the controller processor 902 for transmission via a given radio module 908, the radio module 908 may transmit the data from the control descriptors in its radio transmit buffers 960 faster than the controller processor 902 can provide control descriptors for data that is ready to be transmitted. The AE transmit queues 964 are managed to keep the radio transmit buffers 960 in a non-empty state by maintaining ready-to-transmit control descriptors to push to the radio transmit buffers 960 during times when the controller processor 902 would otherwise be unable to push the control descriptors.
In the state of the system 1000 as shown in
On the controller side 980, the controller processor 902 may have a new data packet packaged in a control descriptor with data to transmit via radio module 908a. The control descriptor is placed in an AE transmit queue element 1030 (in
The controller processor 902 pushes the new transmit linked list element on to the AE transmit queue 964-1 at 1030 in
When the backlog bit is set, either by the new linked list element at 1080 or by a previous linked list element in the AE transmit queue 964-1, the backlog bit is detected by the assist engine 904. If the corresponding radio transmit buffer 960-1 is not filled at its maximum level, the assist engine 904 pops the next linked list element off the AE transmit queue 964-1 at 1082 and loads the control descriptor corresponding to the AE transmit queue element on the radio transmit buffer 960-1 at 1084. The backlog bit is not cleared until the AE transmit queue 964-1 is left empty. In the example in
When the control descriptor is added to the radio transmit buffer 960-1 at 1084, the assist engine 904 increments the depth of the radio transmit buffer 960-1 in the transmit buffer depth state 1060 (in
It will be understood that the foregoing description of numerous implementations has been presented for purposes of illustration and description. It is not exhaustive and does not limit the claimed inventions to the precise forms disclosed. For example, the above examples have been described as implemented according to IEEE 802.11an and 802.11bgn. Other implementations may use other standards. In addition, examples of the wireless access points described above may use housings of different shapes, not just round housing. The number of radios in the sectors and the number of sectors defined for any given implementation may also be different. Modifications and variations are possible in light of the above description or may be acquired from practicing the invention. The claims and their equivalents define the scope of the invention.
Claims
1. A wireless network access device comprising:
- a radio interface comprising a serial communication line, a switch, and M serial connections to M connectors for connecting up to M corresponding detachable radio modules, the radio interface configured to form up to M individually addressable radio communications paths via the switch;
- each radio module comprising a radio configured to communicate with client devices in a corresponding coverage area and a radio processor configured to manage at least one radio receiving buffer configured to store receiver buffer identifiers, each receiver buffer identifier identifying a corresponding received data space, the radio processor configured to store a next received data packet in the received data space corresponding to a current receiver buffer identifier and to identify a next receiver buffer identifier as the current receiver buffer identifier;
- a network interface configured to provide data network access;
- a processor configured to manage communication between the client devices that communicate with the radio modules and a data network via the radio interface and the network interface when N radio modules are connected to the radio interface, where N≦M;
- N receive buffers in a system memory corresponding to the N connected radio modules, each receive buffer comprising a plurality of receiver buffer identifiers identifying the received data spaces in system memory designated for storing received data from the corresponding radio module, the processor configured to communicate a next-in-queue receiver buffer identifier to a selected one of the N radio modules after the selected one of the N radio modules has used the current receiver buffer identifier to store a received data packet;
- an assist engine connected in the serial connection between the processor and the switch, the assist engine configured to receive the next-in-queue receiver buffer identifier,
- to store the next-in-queue receiver buffer identifier in an assist engine receive queue corresponding to the selected one of the N radio modules, and
- to communicate a next-to-radio receiver buffer identifier to the selected one of the N radio modules from the assist engine receive queue.
2. The wireless network access device of claim A where the assist engine is configured:
- to generate an assist engine receive queue element for storing the next-in-queue receiver buffer identifier received from the processor and receiver queue management information,
- to add the assist engine receive queue element to the assist engine receive queue, the assist engine receive queue comprising a plurality of assist engine receive queue elements containing queued receiver buffer identifiers to be sequentially provided to the selected one of the N radio modules starting with a next-to-radio assist engine receive queue element,
- to communicate a next-to-radio receiver buffer identifier in the next-to-radio assist engine receive queue element, and
- to determine another next-to-radio assist engine receive queue element according to the receiver queue management information.
3. The wireless network access device of claim 2 where the assist engine is configured:
- to generate the assist engine receive queue as a linked list of assist engine receive queue elements where the receiver queue management information in each assist engine receive queue element includes an identifier to a next linked list and the assist engine includes a linked list status block.
4. The wireless network access device of claim 3 where the assist engine is configured:
- to generate multiple assist engine receive queues as linked lists of fixed length queues.
5. The wireless network access device of claim 1 where:
- the received data spaces identified by the received buffer identifiers are socket buffers; and
- the received buffer identifiers are pointers to the socket buffers.
6. The wireless network access device of claim 1 where:
- the at least one radio receiving buffer in each radio module is configured to have a fixed number of receive buffer entries, and
- the radio processor generates additional radio receiving buffers as each at least one radio receiving buffer is filled.
7. The wireless network access device of claim 1 where:
- the at least one radio receiving buffer in each radio module is configured to have a fixed number of receive buffer entries, and
- the radio processor generates a number of the at least one radio receiving buffer based on an expected input traffic.
8. The wireless network access device of claim 1, where:
- the radio processor in the radio module is further configured to manage at least one radio transmit buffer configured to store transmit data buffer identifiers, each transmit data buffer identifiers identifying a corresponding data space containing data to be transmitted, the radio processor configured to retrieve a next data packet to transmit from the data space corresponding to a current transmit data buffer identifier and to identify a next transmit data buffer identifier as the current transmit data buffer identifier;
- the wireless network access device further comprising N transmit buffers in a system memory corresponding to the N connected radio modules, each transmit buffer comprising a plurality of transmit data buffer identifiers identifying the data spaces in system memory containing data to be transmitted by the corresponding radio module, the processor configured to communicate a next-in-queue transmit data buffer identifier to a selected one of the N radio modules after the selected one of the N radio modules has used the current transmit data buffer identifier to transmit the corresponding data packet;
- where the assist engine is configured: to receive the next-in-queue transmit data buffer identifier, to store the next-in-queue transmit data buffer identifier in an assist engine transmit queue corresponding to the selected one of the N radio modules, and to communicate a next-to-radio transmit data buffer identifier to the selected one of the N radio modules from the assist engine transmit queue.
9. The wireless network access device of claim 8, where the assist engine is configured:
- to generate an assist engine transmit queue element for storing the next-in-queue transmit data buffer identifier received from the processor and transmitter queue management information,
- to add the assist engine transmit queue element to the assist engine transmit queue, the assist engine transmit queue comprising a plurality of assist engine transmit queue elements containing queued transmit data buffer identifiers to be sequentially provided to the selected one of the N radio modules starting with a next-to-radio assist engine transmit queue element,
- to communicate a next-to-radio transmit data buffer identifier in the next-to-radio assist engine transmit queue element, and
- to determine another next-to-radio assist engine transmit queue element according to the transmitter queue management information.
10. The wireless network access device of claim 9 where the assist engine is configured:
- to generate the assist engine transmit queue as a linked list of assist engine transmit queue elements where the transmit queue management information in each assist engine transmit queue element includes an identifier to a next linked list and the assist engine includes a linked list transmit status block.
11. The wireless network access device of claim 10 where the assist engine is configured:
- to generate multiple assist engine transmit queues as linked lists of fixed length queues.
12. The wireless network access device of claim 1 where:
- the transmit data spaces identified by the transmit data buffer identifiers are control descriptors having links to additional control descriptors and a link to the transmit data space containing the data to be transmitted; and
- the transmit data buffer identifiers are pointers to the control descriptors.
13. The wireless network access device of claim 1 where:
- the at least one radio transmit buffer in each radio module is configured to have a fixed number of radio transmit buffer entries, and
- the radio processor generates additional radio transmit buffers as each at least one radio transmit buffer is filled.
14. The wireless network access device of claim 1 where:
- the at least one radio transmit buffer in each radio module is configured to have a fixed number of transmit buffer entries, and
- the radio processor generates a number of the at least one radio transmit buffer based on an expected input traffic.
15. A wireless network access device comprising:
- a radio interface comprising a serial communication line, a switch, and M serial connections to M connectors for connecting up to M corresponding detachable radio modules, the radio interface configured to form up to M individually addressable radio communications paths via the switch;
- each radio module comprising a radio configured to communicate with client devices in a corresponding coverage area and a radio processor configured to manage at least one radio transmit buffer configured to store transmit data buffer identifiers, each transmit data buffer identifiers identifying a corresponding data space containing data to be transmitted, the radio processor configured to retrieve a next data packet to transmit from the data space corresponding to a current transmit data buffer identifier and to identify a next transmit data buffer identifier as the current transmit data buffer identifier;
- a network interface configured to provide data network access;
- a processor configured to manage communication between the client devices that communicate with the radio modules and a data network via the radio interface and the network interface when N radio modules are connected to the radio interface, where N≦M;
- N transmit buffers in a system memory corresponding to the N connected radio modules, each transmit buffer comprising a plurality of transmit data buffer identifiers identifying the data spaces in system memory containing data to be transmitted by the corresponding radio module, the processor configured to communicate a next-in-queue transmit data buffer identifier to a selected one of the N radio modules after the selected one of the N radio modules has used the current transmit data buffer identifier to transmit the corresponding data packet;
- an assist engine connected in the serial connection between the processor and the switch, the assist engine configured: to receive the next-in-queue transmit data buffer identifier, to store the next-in-queue transmit data buffer identifier in an assist engine transmit queue corresponding to the selected one of the N radio modules, and to communicate a next-to-radio transmit data buffer identifier to the selected one of the N radio modules from the assist engine transmit queue.
16. The wireless network access device of claim 15 where the assist engine is configured:
- to generate an assist engine transmit queue element for storing the next-in-queue transmit data buffer identifier received from the processor and transmitter queue management information,
- to add the assist engine transmit queue element to the assist engine transmit queue, the assist engine transmit queue comprising a plurality of assist engine transmit queue elements containing queued transmit data buffer identifiers to be sequentially provided to the selected one of the N radio modules starting with a next-to-radio assist engine transmit queue element,
- to communicate a next-to-radio transmit data buffer identifier in the next-to-radio assist engine transmit queue element, and
- to determine another next-to-radio assist engine transmit queue element according to the transmitter queue management information.
17. The wireless network access device of claim 15, where:
- the radio processor in the radio module is further configured to manage at least one radio receiving buffer configured to store receiver buffer identifiers, each receiver buffer identifier identifying a corresponding received data space, the radio processor configured to store a next received data packet in the received data space corresponding to a current receiver buffer identifier and to identify a next receiver buffer identifier as the current receiver buffer identifier;
- the wireless network access device further comprising N receive buffers in a system memory corresponding to the N connected radio modules, each receive buffer comprising a plurality of receiver buffer identifiers identifying the received data spaces in system memory designated for storing received data from the corresponding radio module, the processor configured to communicate a next-in-queue receiver buffer identifier to a selected one of the N radio modules after the selected one of the N radio modules has used the current receiver buffer identifier to store a received data packet;
- where the assist engine is configured: to receive the next-in-queue receiver buffer identifier, to store the next-in-queue receiver buffer identifier in an assist engine receive queue corresponding to the selected one of the N radio modules, and to communicate a next-to-radio receiver buffer identifier to the selected one of the N radio modules from the assist engine receive queue.
18. The wireless network access device of claim 17, where the assist engine is configured:
- to generate an assist engine receive queue element for storing the next-in-queue receiver buffer identifier received from the processor and receiver queue management information,
- to add the assist engine receive queue element to the assist engine receive queue, the assist engine receive queue comprising a plurality of assist engine receive queue elements containing queued receiver buffer identifiers to be sequentially provided to the selected one of the N radio modules starting with a next-to-radio assist engine receive queue element,
- to communicate a next-to-radio receiver buffer identifier in the next-to-radio assist engine receive queue element, and
- to determine another next-to-radio assist engine receive queue element according to the receiver queue management information.
Type: Application
Filed: Mar 31, 2015
Publication Date: Jan 14, 2016
Inventors: DREW BERTAGNA (THOUSAND OAKS, CA), DAVID ROSEN (WOODLAND HILLS, CA)
Application Number: 14/675,250