Gate Leakage Based Low Power Circuits
A low power voltage divider facility using gate leakage characteristics to divide voltage levels of sub-threshold and near-threshold circuits. The divider comprises a gate leakage based divider facility, and, optionally, a capacitive divider facility.
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This application is related to the following:
1. Provisional Application Ser. No. 62/066,218, filed 20 Oct. 2014 (“Parent Provisional”);
2. PCT Application No. PCT/US15/50239 filed 15 Sep. 2015 (“Related Application 1”);
3. U.S. application Ser. No. 14/855,105, filed 15 Sep. 2015 (“Related Application 2”);
4. U.S. application Ser. No. [Docket No. JAM012], filed simultaneously herewith (“Related Application 3”);
5. U.S. application Ser. No. [Docket No. JAM014], file simultaneously herewith (“Related Application 4”); and
6. U.S. application Ser. No. [Docket No. JAM015], filed simultaneously herewith (“Related Application 5”).
This application claims priority to the Parent Provisional, and hereby claims benefit of the filing date thereof pursuant to 37 CFR §1.78(a)(4).
The subject matter of the Parent Provisional and the Related Applications, each in its entirety, is expressly incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to gate leakage-based (“GL-based”) circuits and more specifically, to ultra-low power, high accuracy voltage divider circuits using GL-based circuits.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Shown in
Shown by way of example in
As is known, minimizing power is useful in low-power MCU applications. Many functions performed in a low-power MCU require various forms of voltage dividers. For example, detecting fluctuation in a power source output voltage such as a battery output or an energy harvester output is useful in low-power MCU applications. One known means of detecting these fluctuations is to continuously monitor voltage during low-power MCU operation. However, as is also known, continuous monitoring during low-power MCU operation may consume non-trivial amounts of power, due in part to large power dissipated by voltage dividers that are part of the voltage monitoring circuits. Likewise, regulators and ADCs use various forms of voltage dividers that consume power.
What is needed is a method and apparatus adapted to perform voltage division while consuming less power than known prior art.
BRIEF SUMMARY OF THE INVENTIONIn one embodiment, a voltage divider facility comprising a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages, and a first capacitive facility coupled between the first and second voltages and adapted to adjust a transient behavior of the first gate-leakage based divider facility.
In another embodiment, a voltage divider facility includes a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages. The first gate leakage-based divider facility further includes a first MOS transistor adapted to receive the first voltage at a gate terminal of the first MOS transistor, and output the first divided voltage at a source and a drain terminal of the first MOS transistor, and a second MOS transistor adapted to receive the first divided voltage at a gate terminal of the second MOS transistor, and couple to a second voltage at a source and a drain terminal of the second MOS transistor. The first gate leakage-based divider facility further includes a plurality of parallel connected MOS transistors, and wherein the first gate leakage-based divider facility further includes one or more switches to select one or more of the plurality of parallel connected MOS transistors.
In another embodiment, a voltage divider facility includes a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages. The first gate leakage-based divider facility further includes a first MOS transistor adapted to receive the first voltage at a gate terminal of the first MOS transistor, and output the first divided voltage at a source and a drain terminal of the first MOS transistor, and a second MOS transistor adapted to receive the first divided voltage at a gate terminal of the second MOS transistor, and couple to a second voltage at a source and a drain terminal of the second MOS transistor. The first gate leakage-based divider facility further includes one or more switches to select one or more of the first MOS transistor and the second MOS transistor.
In another embodiment, a method for dividing a voltage comprises the steps of: [1] developing a divided voltage as a function of the voltage using a gate leakage-based divider facility; and [2] applying an adjustment function to the divided voltage using a capacitance-based divider facility.
The several embodiments may be more fully understood by a description of certain preferred embodiments in conjunction with the attached drawings in which:
In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers, and is not intended to imply or suggest that identity is required in either function or structure in the several embodiments.
DETAILED DESCRIPTIONIn the illustrated embodiment, the GL-based voltage divider facility 38 includes a stack of transistors that includes, in this simple example, a first transistor 42 and a second transistor 44. The first transistor 42 has its gate terminal coupled to a measured voltage 46, here labeled as “VMEAS”, and has both source and drain terminals shorted together. Alternatively, in a taller stack, the gate terminal of the first transistor 42 may be coupled to the measured voltage 46 via one or more additional transistors (see, e.g.,
In the illustrated embodiment, the capacitive facility 40 includes a stack of compensation capacitors including, in this simple example, a first compensation capacitor 50 and a second compensation capacitor 52. As is known, and according to other embodiments, capacitive facility 40 may comprise a single capacitive element (not shown) or more than the two illustrated capacitive elements (not shown). As is also known, these capacitive elements may be actual capacitors, MOSFETs, MoM capacitors, MiM capacitors, or any other means that would be understood by one of ordinary skill in the art. The leakage current of the capacitive element is significantly less than the leakage current of the gate oxides, thus ensuring that the capacitors affect only the AC coupling and do not affect DC current levels. The first compensation capacitor 50 has one of its terminals or plates coupled to the measured voltage 46 and its other terminal or plate coupled to the intermediate node 48. The second compensation capacitor 52 has one of its terminals or plates coupled to the intermediate node 48, and its other terminal or plate coupled to the ground node.
During operation, the divided version, “VDIV”, of the measured voltage “VMEAS” 46 is developed as a function of the GL-based voltage divider facility 38 and the capacitive facility 40. Generally, as is known, current is conducted through the gate oxide of the transistors. According to one embodiment, thin-oxide native devices are utilized in the GL-based voltage divider facility. As is known, these devices are always on and will constitute a constant capacitance value. A voltage level commiserate with a target technology is applied at the gate of the first transistor 42, i.e., the uppermost oxide of the first transistor 42. This in turn develops a voltage across the first oxide causing charge to tunnel through the oxide, thus developing current. This current charges the oxide layers of subsequent devices until all oxides in the stack have substantially identical current flowing through each device. According to one embodiment, the gate-oxides of the devices are substantially identical and, consequently, the voltages across all oxides are substantially identical. Thus, according to this embodiment, the circuit acts as a voltage divider. As is known by one of ordinary skill in the art of circuit design, the small leakage current through the oxide emulates a high-value resistor, with voltage division corresponding to a ratio of oxide leakage as determined by stacking, relative oxide thicknesses and relative oxide areas.
GL-based voltage divider facility 38 illustrated in
Though gate leakage current can be extremely low, it does not react quickly to high frequency fluctuations on VMEAS. However, at high frequencies the capacitive characteristics of the GL-based voltage divider facility 38 overtake the resistive divide action of the same transistor stack. Each transistor in the stack looks electrically like a capacitor at high frequency and thus acts as a capacitive divider instead of a resistive divider. Consequently, the divider has good response times at both high and low frequencies.
Due to the effects of parasitic capacitances and the non-linear capacitive behavior of the GL-based voltage divider facility 38 illustrated in
According to some embodiments, it may be desirable to alter selectively the divide ratio of the GL-based voltage divider facility 38 illustrated in
During operation, the selected number of transistors in the GL-based divider facility 38′ alters the divide ratio and concomitantly the voltage value of the divided voltage 48. By way of example, closing the first switch 72 bypasses and effectively eliminates the first transistor 42 from the GL-based divider facility 38′. Likewise, closing the second switch 74 bypasses and effectively eliminates the second transistor 44 from the GL-based divider facility 38′. In this way, the divide ratio is selectively altered, effectively allowing a single circuit to monitor different voltage levels. Similarly, first compensation capacitor 50 and second compensation capacitor 52 may be selectively added or removed from tunable capacitive facility 40′ through the use of third switch 73 and fourth switch 75. These switches, i.e., the first switch 72, the second switch 74, the third switch 73, and the fourth switch 75 may each be implemented using pass transistors or transmission gates, embodiments of which are well known to one of ordinary skill in the art of circuit design. Selectively altering the divide ratio may be controlled via software means, by hardware means, i.e., hardware fuses or non-volatile memory, or by any other means known to one of ordinary skill in the art of circuit design.
As is known, the effects of process variation on effective transistor size may impact the divide ratio of the GL-based voltage divider facility 38 illustrated in
During operation, the effective size of the first transistor 42 may be modified to compensate for the prior mentioned process variation effects, thus altering or tuning the divide ratio of the GL-based voltage divider facility 38″, and concomitantly the voltage value of the divided voltage 48. By way of example, closing the first switch 78 and connecting transistor 42a into the circuit. Likewise, closing the second switch 80 connects transistor 42b in parallel with transistor 42a, and closing the third switch 82 connects transistor 42c in parallel with transistors 42a and 42b. As is understood by one of ordinary skill in the art of circuit design, various combinations of transistor sizes may be used in different device size tuning methodologies, i.e., linear, binary-weighted, etc.
According to another embodiment, an adjustment to the transient behavior of intermediate node 48 “VDIV” is not needed and the capacitive facility, illustrated and discussed previously, is accordingly not needed.
Similarly,
As is known, gate leakage is minimally dependent upon temperature. As such, in addition to being useful for voltage dividers, gate leakage based circuits may also be used as current reference generators with reasonably good temperature tolerance.
In accordance with some embodiments, the GL-based resistive element 132 may be implemented using various configurations of NMOS and/or PMOS devices. According to one embodiment as illustrated in
Referring back to
The current mirror 130, illustrated in
As discussed earlier in this application, process variations may impact the effective transistor size of GL-based elements. As is known, one method of compensating for process variations is to selectively alter, or tune, the sizes of the transistors comprising the particular devices of interest.
During operation the size of the tunable gate leakage resistive facility 144 may be modified to compensate for the prior-mentioned process variation effects. By way of example, closing the first switch 146 connects transistor 132a into the circuit. Likewise, closing the second switch 148 connects transistor 132b in parallel with transistor 132a, and closing the third switch 150 connects transistor 132c in parallel with transistors 132a and 132b. As is understood by one of ordinary skill in the art of circuit design, various combinations of transistor sizes may be used in different device size tuning methodologies, i.e., linear, binary-weighted, etc.
Generally, as is understood, the temperature coefficient of the reference voltage generator 92 or reference voltage generator 126 will set to be close to 0, i.e., the output voltage will be stable across temperature. However, gate leakage has a small temperature dependence. This dependence may be compensated with a positive to absolute temperature (“PTAT”) or complimentary to absolute temperature (“CTAT”) characteristic on the voltage reference generator 92 or reference voltage generator 126. Consequently, an implementation according to some embodiments may include a voltage reference generator with a CTAT or PTAT characteristic. The analog voltage buffer may also apply the temperature compensation if its gain value has a CTAT or PTAT characteristic.
Although described in the context of particular embodiments, one of ordinary skill in this art will readily realize that many modifications may be made in such embodiments to adapt either to specific implementations.
Thus it is apparent that an improved method and apparatus to voltage division with increased accuracy while consuming less power than known prior art has been disclosed. Further, the method and apparatus provides performance generally superior to the best prior art techniques.
Claims
1. A voltage divider facility comprising:
- a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages; and
- a first capacitive facility coupled between the first and second voltages and adapted to adjust a transient behavior of the first gate-leakage based divider facility.
2. The voltage divider facility of claim 1 wherein said first gate leakage-based divider facility further comprises:
- a first MOS transistor adapted to: receive said first voltage at a gate terminal of said first MOS transistor; and output said first divided voltage at a source and a drain terminal of said first MOS transistor;
- a second MOS transistor adapted to: receive said first divided voltage at a gate terminal of said second MOS transistor; and couple to a second voltage at a source and a drain terminal of said second MOS transistor.
3. The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS transistor are of type NMOS.
4. The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS devices are of type PMOS.
5. The voltage divider facility of claim 2 wherein said first MOS transistor is of type NMOS and said second MOS device is of type PMOS.
6. The voltage divider facility of claim 2 wherein said first MOS transistor is of type PMOS and said second MOS device is of type NMOS.
7. The voltage divider facility of claim 2 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said first MOS transistor and said second MOS transistor.
8. The voltage divider facility of claim 2 wherein said first MOS transistor is further characterized as comprising a plurality of parallel connected MOS transistors.
9. The voltage divider facility of claim 8 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
10. The voltage divider facility of claim 2 wherein said second MOS transistor is further characterized as comprising a plurality of parallel connected MOS transistors.
11. The voltage divider facility of claim 10 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
12. The voltage divider facility of claim 2 wherein said first MOS transistor and said second MOS transistor are further characterized as comprising a plurality of parallel connected MOS transistors.
13. The voltage divider facility of claim 12 wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
14. The voltage divider facility of claim 1 wherein said first capacitive facility further comprises:
- a first capacitor adapted to: receive said first voltage at a first terminal of said first capacitor; and output said first divided voltage at a second terminal of said first capacitor;
- a second capacitor adapted to: receive said first divided voltage at a first terminal of said second capacitor; and couple to a second voltage at a second terminal of said second capacitor.
15. The voltage divider facility of claim 14 wherein said first capacitor is further characterized as comprising a plurality of parallel connected capacitors.
16. The voltage divider facility of claim 15 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.
17. The voltage divider facility of claim 14 wherein said second capacitor is further characterized as comprising a plurality of parallel connected capacitors.
18. The voltage divider facility of claim 17 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.
19. The voltage divider facility of claim 14 wherein said first capacitor and said second capacitor are further characterized as comprising a plurality of parallel connected capacitors.
20. The voltage divider facility of claim 19 wherein said first capacitive facility further comprises one or more switches to select one or more of said plurality of parallel connected capacitors.
21. An electrical facility comprising a voltage divider facility according to claim 1.
22. The electrical facility of claim 21 further characterized as a low dropout regulating facility.
23. The electrical facility of claim 21 further characterized as an analog to digital conversion facility.
24. The electrical facility of claim 21 further characterized as a voltage monitor facility.
25. The electrical facility of claim 24 wherein said voltage monitoring facility further comprises:
- a first reference voltage generator adapted to output a first reference voltage; and
- a first comparator adapted to: receive said first divided voltage; receive said first reference voltage; and compare said first divided voltage to said first reference voltage, and, in response, to output: a logic_1 value if said first divided voltage is greater than said first reference voltage; and a logic _0 value if said first divided voltage is not greater than said first reference voltage.
26. A voltage divider facility comprising:
- a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages;
- wherein said first gate leakage-based divider facility further comprises: a first MOS transistor adapted to: receive said first voltage at a gate terminal of said first MOS transistor; and output said first divided voltage at a source and a drain terminal of said first MOS transistor; a second MOS transistor adapted to: receive said first divided voltage at a gate terminal of said second MOS transistor; and couple to a second voltage at a source and a drain terminal of said second MOS transistor;
- wherein said first gate leakage-based divider facility further comprises a plurality of parallel connected MOS transistors; and
- wherein the first gate leakage-based divider facility further comprises one or more switches to select one or more of said plurality of parallel connected MOS transistors.
27. A voltage divider facility comprising:
- a first gate leakage-based divider facility coupled between first and second voltages and adapted to develop a first divided voltage intermediate the first and second voltages;
- wherein said first gate leakage-based divider facility further comprises: a first MOS transistor adapted to: receive said first voltage at a gate terminal of said first MOS transistor; and output said first divided voltage at a source and a drain terminal of said first MOS transistor; a second MOS transistor adapted to: receive said first divided voltage at a gate terminal of said second MOS transistor; and couple to a second voltage at a source and a drain terminal of said second MOS transistor; and
- wherein said first gate leakage-based divider facility further comprises one or more switches to select one or more of said first MOS transistor and said second MOS transistor.
28. A method for dividing a voltage, the method comprising the steps of:
- [1] developing a divided voltage as a function of said voltage using a gate leakage-based divider facility; and
- [2] applying an adjustment function to said divided voltage using a capacitance-based divider facility.
29. The method of claim 28 wherein said method further comprises the step of:
- [3] selectively tuning a number of series connected transistor devices in said gate leakage-based divider facility.
30. The method of claim 29 wherein said method further comprises the step of:
- [4] selectively tuning a number of parallel connected transistors devices in said gate leakage-based divider facility.
31. The method of claim 28 wherein said method further comprises the step of:
- [3] selectively tuning a number of parallel connected transistors devices in said gate leakage-based divider facility.
32. An electrical facility configured to perform the steps of a method according to any one of claims 28 to 31.
33. The electrical facility of claim 32 further characterized as a low dropout regulating facility.
34. The electrical facility of claim 32 further characterized as an analog to digital conversion facility.
35. The electrical facility of claim 32 further characterized as a voltage monitor facility.
36. An electronic system comprising an electrical facility according to claims 32 to 35.
37. A computer readable medium including executable instructions which, when executed in a processing system, causes the processing system to perform the steps of a method according to any one of claims 28 to 31.
Type: Application
Filed: Oct 20, 2015
Publication Date: Apr 21, 2016
Applicant: AMBIQ MICRO, INC (Austin, TX)
Inventors: Scott Hanson (Austin, TX), Donald Mark Bartlett (Fort Collins, CO), Yanning Lu (Austin, TX)
Application Number: 14/918,384