PULSE DENSITY MODULATION DIGITAL-TO-ANALOG CONVERTER WITH TRIANGLE WAVE GENERATION
A phase accumulator style circuit generates an output stream of pulses. The density of the pulse stream is proportional to the input data value relative to the maximum value supported by the bit width of an adder. The output pulse density is representative of the desired output voltage. The pulse stream may be filtered with a resistor-capacitor (RC) low pass filter to yield an analog voltage. Faster clock rates support the use of smaller output filters that reduce circuit cost. This circuit provides triangle wave generation wherein the DAC output ramps up and down at a user specified rate (slope) between user specified maximum and minimum amplitude values. The up and down triangle wave ramp rates (up and down slopes) may be different and independent or the same.
The present disclosure relates to pulse width modulation (PWM) audio applications, and, more particularly, to a digital-to-analog converter (DAC) comprising slope and pulse density modulation (PDM) generators, blanking and delay logic, and a low pass filter; and that provides triangle wave generation used for converting an analog waveform into a digital PWM train of pulses.
BACKGROUNDAll Class D modulation techniques encode information about the audio signal into a stream of pulses. Generally, the pulse widths are linked to the amplitude of the audio signal, and the spectrum of the pulses includes the desired audio. The most common modulation technique is pulse-width modulation (PWM). Conceptually, PWM compares the input audio signal to a triangular or ramping up and down waveform that runs at a fixed carrier frequency. This creates a stream of pulses at the carrier frequency. Within each period of the carrier frequency, the duty ratio of the PWM pulse is proportional to the amplitude of the audio signal. PWM is attractive because it allows 100-dB or better audio-band SNR at PWM carrier frequencies of a few hundred kilohertz, low enough to limit switching losses in the output stage. Also many PWM modulators are stable up to nearly 100 percent modulation, in concept permitting high output power up to the point of overloading. Therefore it is desirable for the amplitude (height) and slope of the triangle wave to be adjusted for optimal performance of the PWM modulator with a given analog input signal.
SUMMARYTherefore, a need exists for a pulse density modulation (PDM) digital-to-analog converter (DAC) that generates a triangular waveform automatically with parameters, such as ramp rate and voltage levels that may be set by a user in digital logic of the PDM DAC.
According to an embodiment, a pulse density modulated digital-to-analog converter (PDM DAC) with triangle wave generation may comprise: a pulse density modulation (PDM) generator; a low pass filter coupled to an output of the PDM generator; and a triangle wave generator having an output that may be coupled to the PDM generator, wherein the output of the PDM generator may be determined by digital values generated by the triangle wave generator.
According to a further embodiment, the triangle wave generator may generate monotonically increasing digital values until a maximum digital value may be reached then monotonically decreasing digital values until a minimum digital value may be reached. According to a further embodiment, the monotonically increasing digital values may go from the minimum digital value to the maximum digital value, and the monotonically decreasing digital values may go from the maximum digital value to the minimum digital value. According to a further embodiment, the monotonically increasing digital values and the monotonically decreasing digital values may repeat. According to a further embodiment, the maximum digital value may be programmable. According to a further embodiment, the minimum digital value may be programmable. According to a further embodiment, a rate of change of the monotonically increasing digital values may be programmable. According to a further embodiment, a rate of change of the monotonically decreasing digital values may be programmable.
According to a further embodiment, a pulse density from the PDM generator may be proportional to the digital values. According to a further embodiment, an output from the low pass filter may provide an analog triangle wave. According to a further embodiment, a rate of change of the monotonically increasing digital values may determine a positive slope of the analog triangle waveform. According to a further embodiment, the rate of change of the monotonically decreasing digital values may determine a negative slope of the analog triangle waveform. According to a further embodiment, the maximum digital value may determine a maximum amplitude of the analog triangle waveform. According to a further embodiment, the minimum digital value may determine a minimum amplitude of the analog triangle waveform.
According to a further embodiment, the PDM generator may comprise: an accumulator; an increment register; an adder having an output coupled to an input of the accumulator, a first input coupled to an output of the increment register, and a second input coupled to an output of the accumulator; and a flip-flop having an input coupled to a carry output from the adder. According to a further embodiment, the low pass filter may have at least one pole. According to a further embodiment, the low pass filter may comprise at least one resistor and at least one capacitor.
According to a further embodiment, triangle wave generator may comprise: a slope accumulator; a high value comparator coupled to an output of the slope accumulator; a low value comparator coupled to the output of the slope accumulator; an adder; a slope register having an output coupled to an input of the adder; and control logic, wherein the digital values may be provided by the triangle wave generator. According to a further embodiment, a first slope step multiplexer and control logic may be provided for selecting a larger than normal slope value to cause the low pass filter to quickly track a change in slope direction. According to a further embodiment, the PDM generator, low pass filter and triangle wave generator may be provided in a mixed signal integrated circuit. According to a further embodiment, the mixed signal integrated circuit may be a microcontroller. According to a further embodiment, the mixed signal integrated circuit may be selected from the group consisting of a microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), and programmable logic array (PLA).
According to a further embodiment, a system for converting an analog waveform into a pulse width modulation (PWM) pulse train may comprise: an analog comparator having a first input coupled to an analog signal; and a second input coupled to the PDM DAC that may comprise: a pulse density modulation (PDM) generator; a low pass filter coupled to an output of the PDM generator; and a triangle wave generator having an output coupled to the PDM generator, wherein the output of the PDM generator may be determined by digital values generated by the triangle wave generator and an output from the analog comparator may comprise a PWM pulse train representative of the analog signal.
A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
DETAILED DESCRIPTIONThe PDM DAC with triangle wave generation provides a low cost way to generate triangle wave reference voltages to an analog comparator for generating a digital pulse width modulation (PDM) pulse train representation of the time varying amplitude of an analog signal. The PDM DAC with triangle wave generation is substantially a digital design, so design porting is not an issue when moving to new process technologies. The large digital content thereof scales well with process scaling. “Triangle wave” and “triangle waveform” will be used interchangeable herein. A triangle wave is a non-sinusoidal waveform named for its triangular shape. It is a periodic, piecewise linear, continuous real function. In physics, a wave is a disturbance or oscillation that travels through matter or space, accompanied by a transfer of energy.
According to various embodiments of this disclosure, a phase accumulator style circuit generates an output stream of pulses. The density of the pulse stream is proportional to the input data value relative to the maximum value supported by the bit width of an adder. The output pulse density is representative of the desired output voltage. The pulse stream may be filtered with a resistor-capacitor (RC) low pass filter to yield an analog voltage. Faster clock rates support the use of smaller output filters that reduce circuit cost. This circuit provides triangle wave generation wherein the DAC output ramps up and down at a user specified rate (slope) between user specified maximum and minimum amplitude values. The up and down triangle wave ramp rates (up and down slopes) may be different and independent or the same.
Referring now to the drawings, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to
Referring to
The accumulator register 310 and the adder 314 constantly add an increment value from the increment value register 318 to an accumulated sum in the adder 314. For non-zero input values, the accumulated sum will eventually overflow, wherein this overflow may be indicated via the CO signal 316 from the adder 314. The rate that the overflow occurs is related to the size of the increment value from the increment value register 318 versus the maximum value that the adder 314 can handle. For example, a 12-bit adder 314 has a maximum output of 0xFFF. If the inputs to the adder 314, the accumulator value and the input value, exceed 0xFFF, then a CO signal 316 is generated. The larger the input value, the more frequently the CO signal 316 may be generated. The resultant pulse stream from the CO signal 316 may then be filtered with a low pass filter 350. The resultant analog output voltage from the low pass filter 350 is proportional to the data input increment value from the increment value register 318. The low pass filter 350 may be the dominant “cost” for the complete PDM DAC 106. Using higher clock rates for the PDM DAC 106 allows the use of smaller components in the low pass filter 350, thus reducing the cost thereof. Higher clock rates also support higher conversion speeds making the PDM DAC 106 useable for a wider range of applications. However, the use of higher clock rates will also increase the current consumption of the PDM DAC 106. It is contemplated and within the scope of this disclosure that any low pass filter circuit design may be used to filter the Q-output of the D-latch 320 to produce an analog voltage signal, and one having ordinary skill in circuit design and the benefit of this disclosure may readily be able to design such a low pass filter circuit.
SFR (Special Function Register) DACLOW 332 and DACDAT 330 are input registers that store the desired DAC voltage settings as specified by the user's software. The DACLO 328 and DACHI 326 registers transfer the user's settings from the SFR registers in the processor clock domain to the high speed clock domain of the PDM DAC. Multiplexer 324 selects either the DACLO 328 or the DACHI 326 as specified by the control logic during the rising nor falling portion of the triangle waveform generation. Multiplexer 322 selects either the data from multiplexer 324 or data from the slope accumulator 458. During triangle waveform operation, multiplexer 322 always selects the data from the slope accumulator 458. In triangle wave generation, the data selected by multiplexer 324 is sent to the input of the slope accumulator 458 via the multiplexer 460. The low data from DACLO 328 register is used to initialize the slope accumulator 458 at the start of the upward slope portion of the triangle wave. The high data from DACHI 326 register is used to initialize the slope accumulator 458 at the start of the downward slope portion of the triangle wave.
Referring to
The control logic 456 has many purposes, but for triangle wave generation, the circuit shown in
Referring to
The rise and fall times and the frequency of the triangle wave may be controlled via the SLPCON register 472. The very first clock cycle of the slope process may select a scaled value instead of the specified value to provide prompt DAC response to the DAC trajectory. For all subsequent clocks cycles of the slope process, the slope generator uses the specified data value from the SLPCON register 472 for incrementing/decrementing the DAC data value. The triangle wave mode is useful in digital audio applications where an analog input signals are sampled via an analog comparator using an triangle wave reference signal (see
The Triangle wave function is a “4” step process: The cleared wave direction flip-flop 582 selects the DACDAT register 330 as the slope maximum limit value. The slope direction may be set as positive. The DACHIGEQ digital comparator 452 is selected as the signal to terminate the rising edge portion of the cycle. The slope accumulator 458 increases in value until the output from the DACHIGEQ comparator 452 is asserted. The wave direction flip-flop 582 is set. The wave direction flip-flop 582 selects the DACLO register 328 as the slope minimum limit value. The slope direction is set as negative. The DACLOLEQ comparator 454 is selected as the signal to terminate the falling edge portion of the cycle. The slope accumulator 458 decreases in value until the DACLOLEQ signal is asserted from the DACLOLEQ comparator 454. The wave direction flip-flop 582 is cleared. The cycle repeats. The DACDAT register 330 and DACLO register 328 specify the maximum and the minimum values for the triangle wave form. The DAT register 330 specifies the ramp up and ramp down rates for the triangle waveform.
The FSS signal may be asserted for the first iteration of the slope or ramp process. The FSS signal may then select a larger than normal slope increment/decrement value, e.g., 16×, to provide enough change in DAC voltage to enable the low pass filter 350 to promptly track the desired slope so as to quickly get the analog low pass filter 350 to track the intended slope function. This small step change in DAC value creates a voltage differential that helps the low pass filter 350 to respond. On the first clock cycle of the slope process (including triangle wave segments), a wave direction change signal (
The wave direction flip-flop 582 is set and cleared as the slope generator 400 passes above the high DAC value in the DACDAT register 330 or below the low DAC value in the DACLOW register 332. The wave direction flip-flop 582 alternates as the slope ramps up to the positive limit and then downward to the negative limit. The cycle repeats as long as triangle wave mode is enabled (TWME=1). To quickly get the analog filter to track the intended slope function, the first cycle of a slope process may use a 16× scaled increment/decrement value (not shown). This small step change in DAC value creates a voltage differential that helps the filter to respond. On the first clock cycle of the slope process, a wave direction change signal is asserted from the output of the Exclusive-OR gate 586.
The aforementioned circuit functions, e.g., PDM generator, low pass filter and triangle wave generator may be provided in a mixed signal integrated circuit, e.g., a microcontroller, a microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), a programmable logic array (PLA) and the like.
Additional background information on a PDM DAC is more fully disclosed in commonly owned U.S. patent application Ser. No. 14/202,420; filed Mar. 10, 2014; entitled “Pulse Density Digital-to-Analog Converter with Slope Compensation Function,” by Bryan Kris, Andreas Reiter and Tibor Futo; and is hereby incorporated by reference herein for all purposes.
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.
Claims
1. A pulse density modulated digital-to-analog converter (PDM DAC) with triangle wave generation, comprising:
- a pulse density modulation (PDM) generator having an input;
- a low pass filter coupled to an output of the PDM generator; and
- a triangle wave generator having an output providing digital values representing a triangle waveform to the input of the PDM generator, wherein an output pulse sequence of the PDM generator is determined by the digital values generated by the triangle wave generator and the low pass filter outputs the triangle waveform.
2. The PDM DAC according to claim 1, wherein the triangle wave generator generates monotonically increasing digital values until a maximum digital value is reached then monotonically decreasing digital values until a minimum digital value is reached.
3. The PDM DAC according to claim 2, wherein the monotonically increasing digital values go from the minimum digital value to the maximum digital value and the monotonically decreasing digital values go from the maximum digital value to the minimum digital value.
4. The PDM DAC according to claim 3, wherein the monotonically increasing digital values and the monotonically decreasing digital values repeat.
5. The PDM DAC according to claim 4, wherein the maximum digital value is programmable.
6. The PDM DAC according to claim 4, wherein the minimum digital value is programmable.
7. The PDM DAC according to claim 4, wherein a rate of change of the monotonically increasing digital values is programmable.
8. The PDM DAC according to claim 4, wherein a rate of change of the monotonically decreasing digital values is programmable.
9. The PDM DAC according to claim 1, wherein a pulse density from the PDM generator is proportional to the digital values.
10. The PDM DAC according to claim 2, wherein an output from the low pass filter provides an analog triangle wave.
11. The PDM DAC according to claim 10, wherein a rate of change of the monotonically increasing digital values determines a positive slope of the analog triangle waveform.
12. The PDM DAC according to claim 10, wherein the rate of change of the monotonically decreasing digital values determines a negative slope of the analog triangle waveform.
13. The PDM DAC according to claim 10, wherein the maximum digital value determines a maximum amplitude of the analog triangle waveform.
14. The PDM DAC according to claim 10, wherein the minimum digital value determines a minimum amplitude of the analog triangle waveform.
15. The PDM DAC according to claim 1, wherein the PDM generator comprises:
- an accumulator;
- an increment register;
- an adder having an output coupled to an input of the accumulator, a first input coupled to an output of the increment register, and a second input coupled to an output of the accumulator; and
- a flip-flop having an input coupled to a carry output from the adder.
16. The PDM DAC according to claim 1, wherein the low pass filter has at least one pole.
17. The PDM DAC according to claim 16, wherein the low pass filter comprises at least one resistor and at least one capacitor.
18. The PDM DAC according to claim 1, wherein the triangle wave generator comprises:
- a slope accumulator;
- a high value comparator coupled to an output of the slope accumulator;
- a low value comparator coupled to the output of the slope accumulator;
- an adder;
- a slope register having an output coupled to an input of the adder; and
- control logic, wherein the digital values are provided by the triangle wave generator.
19. The PDM DAC according to claim 18, further comprising a first slope step multiplexer and control logic for selecting a larger than normal slope value to cause the low pass filter to quickly track a change in slope direction.
20. The PDM DAC according to claim 1, wherein the PDM generator, low pass filter and triangle wave generator are provided in a mixed signal integrated circuit.
21. The PDM DAC according to claim 19, wherein the mixed signal integrated circuit is a microcontroller.
22. The PDM DAC according to claim 19, wherein the mixed signal integrated circuit is selected from the group consisting of a microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), and programmable logic array (PLA).
23. A system for converting an analog waveform into a pulse width modulation (PWM) pulse train, said system comprising:
- an analog comparator having a first input coupled to an analog signal; and
- a second input coupled to the PDM DAC according to claim 1, wherein an output from the analog comparator comprises a PWM pulse train representative of the analog signal.
24. A pulse density modulated digital-to-analog converter (PDM DAC) with triangle wave generation, comprising:
- a pulse density modulation (PDM) generator comprising an accumulator, an increment register, an adder having an output coupled to an input of the accumulator, a first input coupled to an output of the increment register, and a second input coupled to an output of the accumulator; and a flip-flop having an input coupled to a carry output from the adder;
- a low pass filter coupled to an output of the PDM generator; and
- a triangle wave generator comprising a slope accumulator, a high value comparator coupled to an output of the slope accumulator, a low value comparator coupled to the output of the slope accumulator, an adder, a slope register having an output coupled to an input of the adder and control logic, wherein digital values are provided by the triangle wave generator to the increment register of the PDM generator, wherein the output of the PDM generator is determined by the digital values generated by the triangle wave generator.
Type: Application
Filed: Nov 11, 2014
Publication Date: May 12, 2016
Inventor: Bryan Kris (Gilbert, AZ)
Application Number: 14/538,036