POWER MOSFETS WITH IMPROVED EFFICIENCY FOR MULTI-CHANNEL CLASS D AUDIO AMPLIFIERS AND PACKAGING THEREFOR
A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.
The application is a continuation of application Ser. No. 11/874,182, filed Oct. 17, 2007, now U.S. Pat. No. ______, issued ______, 2013, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTIONHigh fidelity audio amplification using linear amplification suffers from poor efficiency, excess heating and reduced reliability of power electronic components, and the need for heavy and bulky heat sinking. In portable applications, poor efficiency also leads to shorter and generally unacceptable battery life.
High fidelity linear amplification using class-A amplifiers offers the least distortion but requires its power transistors to continuously carry current and dissipate power. Class B amplifiers introduces a dead-band in the circuit operation where neither transistor conducts but at the expense of increased distortion. Class-AB amplifiers attempt a compromise, but still sacrifice audio quality for efficiency and current consumption.
With the advent of power MOSFETs, a new type of audio amplification with higher efficiency became possible using class-D amplification methods. Class-D amplifiers operate by driving the speaker digitally using a push-pull power output stage or H bridge comprising continuously switched power MOSFETs. By driving a speaker on and off digitally at high frequencies, generally above the audible range, and through control of the pull-up and pull-down times using pulse width modulation (PWM) techniques, the speaker can be made only to respond to the audio content encoded in the PWM modulation.
The switching noise is naturally filtered by the inertial mass of the speaker's voice coil, unable to react to higher frequencies. Further filtering can also be performed digitally in the signal processing and decoding scheme, and additionally through a passive LC network as needed. Additional digital signal processing requires increased computing and more power consumption in digital circuitry. This extra power loss in part offsets the benefits of increased power efficiency of class D audio power amplification, especially at lower output power levels. Ignoring signal processing related power consumption, the power efficiency of a class D power amplifier relies on using low-resistance power MOSFETs, typically four per speaker, i.e. for each “channel”. Cost, on the other hand, depends on using the smallest power MOSFETs implemented in the lowest cost process to minimize the cost per MOSFET switch. For a given MOSFET, a smaller area decreases cost at the expense of increased on-resistance. Larger die have lower on-resistance and improved power efficiency, but higher cost. This area and cost versus power efficiency tradeoff for any power MOSFET is expressed as the product of on-resistance RDS(on) and the die area A, so that a MOSFET constructed with a given technology and specific-on-resistance RDSA and of a given size A1 will have an on-resistance R1 given by
The power output stage may comprise monolithically integrated power MOSFETs or separately-packaged discrete power MOSFETs. Monolithic solutions are desirable for integrating drive electronic circuitry with the power devices themselves, but require much larger die sizes because the on-resistance of lateral devices are typically much higher than vertical discrete devices, especially for devices with blocking voltages over 12 volts. This is because the area efficiency of lateral devices is at best, no better than half that of vertical devices since a lateral device devotes valuable silicon real estate to both drain and source contacts. In contrast, a vertical power MOSFET uses almost the entire top-side as its source connection and 100% of its backside as its drain connection. The RDSA area efficiency and specific on-resistance of vertical devices can be one-fifth and even one-tenth that of a comparable breakdown lateral device.
Trench & Planar Vertical DMOS:
One such vertical prior art device, an N-channel vertical trench-gate DMOS power MOSFET 1 is illustrated in
Between adjacent trench gates, P-type body regions PB are implanted and optionally diffused to form the body or channel region 5 of the MOSFET. Heavily doped P+ region 6 is used to make Ohmic contact to P-body region 5. Inside said PB body regions, N+ source regions 7 are masked and implanted abutting the trench gates 4, forming the N-channel MOSFET's heavily-doped source regions. The device is called DMOS because the device has two junctions one inside the other, i.e. where body 5 is formed and contained within drain epitaxy 3 and source 7 is formed and contained with body 5, hence the acronym D for “double”. The term DMOS originally stood for a MOSFET with a double diffused source-channel, but new fabrication methods have emerged for forming the double junctions with minimal or no high temperature diffusions.
Top source metal 13, typically comprising aluminum, aluminum silicon, or aluminum-copper-silicon is used to contact both N+ source regions 7 and P+ regions 6, and short them together. Aside from top metal 13, a barrier metal, typically a refractory metal such as titanium, platinum or tungsten is preferably employed to prevent metal alloying from spiking through the junction and shorting out the device. Conduction is vertical, with a positive potential applied via metal 16 onto poly gates 15 and 10, an N type inversion layer is induced in PB body regions 5 along the side of trenches 4, allowing current to flow from positively biased N+ drain 2, through epitaxial layer 3, into said channel, through N+ region, and out grounded source metal 13. Ohmic contact is made to the backside of N+ substrate 2 using gold or titanium-nickel-silver sandwich metal after substrate 2 is mechanically thinned and etched to provide good Ohmic contact and contribute a reduced magnitude of substrate resistance.
Ohmic contact to the top-side source and body regions is also critical to achieve reliable device operation. A source-body-short is important to bias the body at the source potential to eliminate any body-effect induced threshold shifts, and to prevent parasitic NPN bipolar transistor conduction. The parasitic NPN bipolar transistor comprising N+ 7 as the parasitic emitter, PB body 5 as the bipolar's base and N− epitaxy 3 as the collector is in parallel with the vertical MOSFET. So long that the emitter-base regions remains shorted during current transients the bipolar remains off and its collector-to-emitter breakdown is equal to the device's BVCES, the same as the MOSFET's BVDSS. If substantial voltage drop occurs in the silicon so that VB>VE despite the emitter-to-base surface short, then the N+ region will begin to inject electrons and the bipolar will snapback to a lower breakdown which will likely destroy the device.
An optional deep P+ region dP+ layer 8 may be included in every cell, in a few of the cells, or along the device's periphery and under than gate pad and gate bus regions. If region 8 is doped more heavily than PB body region 5 and is slightly deeper, then avalanche breakdown will occur first in N− epitaxy layer 3 under dP+ diodes 8 and not in the active cells. By avoiding avalanche in the active cells and in PB body regions 5, the likelihood of device snapback from parasitic NPN conduction is greatly reduced. The device is therefore made avalanche rugged.
The on-resistance is made low by integrating a plurality of active trench gated cells at a high density, by doping N− epitaxy layer 3 to the highest possible concentration to meet the requisite breakdown voltage of the device, and by keeping the channel length, the distance between the bottom of N+ 7 and PB 5, as short as possible without inducing punch-through breakdown. In a device with no deep region 8 in the active cells, the higher the active cell density, the lower the RDSA of the device.
Trench power MOSFETs have become an industry standard device since the early 1990's and are well known in the prior art. A description of a prior art trench DMOS fabrication methods is discussed in U.S. Pat. No. 6,413,822 “A Super-Self-Aligned Trench-Gate DMOS with Reduced On-Resistance” as an example.
Trench power-MOSFETs are manufactured and commercially available in complementary processes. Device 1 of
Generally the same barrier metal is used for fabricating both N-channel and P-channel trench devices. The doping of polysilicon gate material 28 in device 20 may be either P-type or N-type depending on threshold voltage considerations, but in general P-type polysilicon is preferred for making P-channel devices, and N-type polysilicon is preferred for N-channel devices. Mask sets and cell geometries are interchangeable, meaning the same mask set can be used to make both N-channel and P-channel trench DMOS transistors, generally in only 4 to six masking steps. Wafer fabrication is much simpler and lower cost than CMOS wafer fabrication. Whether P-channel or N-channel DMOS, the drain contact to such vertical devices is made on the wafer's back-side.
A less efficient predecessor to the trench DMOS device is the vertical planar DMOS. Dating back to the late 1970's, the planar DMOS has its channel located along the silicon surface rather than on the side of a vertical trench. N-channel planar DMOS 40 in
Polysilicon gate 47 formed atop gate oxide 46 is typically used as a mask to implant the body region 43. The body is then diffused at a high temperature for twelve to twenty hours to diffuse laterally along the surface and vertically into the epitaxial layer. The N+ source 45 requires little subsequent diffusion to complete the channel structure.
Unlike the trench DMOS devices of
The body diffusion can be replaced with a high energy tilt implant at 45 degrees, thereby implanting dopant at an angle to reach laterally beyond the edge of polysilicon gate 47. The wafers must be rotated during the tilt implant to maintain a directionally uniform penetration beneath the polysilicon gates. The cell density of the planar DMOS structure remains limited since a deeper body region 43, regardless how it's formed, has a risk of causing the unwanted pinching effect and offsetting the lower channel resistance with a greater pinch resistance.
Even so, the vertical planar DMOS can achieve specific on-resistances substantially lower than integrated lateral MOSFETs. Like the trench DMOS, it is a vertical device utilizing backside wafer contact for Ohmic connection to the drain.
For completeness, device 60 of
DMOS Equivalent Electrical Network:
The electrical network of vertical DMOS, whether trench or planar in construction, involves a large number of transistors each of high resistance, connected in a massively paralleled arrangement up to million or even tens of millions of cells, all connected with a common gate, a common source and a common drain. One simplified model of a vertical DMOS power transistor is shown in schematic 80 of
A slightly more detailed equivalent schematic 90 in
Provided the device is not switched into the megahertz range, the gate resistance 92 can largely be ignored and the source-drain series resistance be lumped into a single resistance term called drain resistance. The resulting equivalent circuit is shown in schematic 100 of
While vertical power MOSFETs, either vertical planar DMOS or vertical trench gated DMOS have many performance advantages over lateral devices used in integrated circuits, one of their major disadvantages is their inability to integrated multiple independent devices. This limitation stems from the fact that all these devices share a common drain with other MOSFETS in the die. This issue is illustrated in schematic 120 of
Class D Audio Speaker Drivers:
The output stage for a class D audio output is typically a set of power MOSFETs configured in an “H-bridge” circuit topology. The speaker driver typically comprises two push-pull complementary half bridges with outputs A and B driven out of phase per speaker.
A complementary half bridge comprises a P-channel power MOSFET with its source tied to the positive supply rail and an N-channel power MOSFET with a grounded source sharing a common drain as its output. As shown in schematic 140 of
Each half-bridge can in theory deliver an output voltage that switches between Vcc and ground, for a total voltage swing γVout equal to a full Vcc. By suspending an electrical load, in this case speaker 144, between nodes A and B of two half-bridges and by driving the two half-bridges out of phase, the voltage polarity across the speaker can reverse from +Vcc on node A and ground on node B, to a case where node A is biased to ground and node B is biased at Vcc, representing a total voltage swing ΔVout equal to a full 2·Vcc, double that of the half bridge's drive capability. So for the same supply voltage and load current, an H bridge can deliver twice the output power of a half-bridge.
The advantage of using a P-channel MOSFET such as 141 or 143 as a high-side connected switch is that they are easy to drive. Biasing the gate to Vcc, its source potential, turns the device off. Biasing a P-channel MOSFET's gate to ground or any voltage more negative than one threshold voltage Vtp below its source potential Vcc, i.e. whenever VGP<(Vcc−Vtp), turns the P-channel “on” and into a conducting state. The gate driver buffer must be designed to limit the maximum gate-to-source voltage to a potential less than the gate oxide rupture voltage VGS(max).
Because P-channel MOSFETs have a specific on-resistance at least twice that of an N-channel with comparable voltage ratings, another popular alternative to the complementary H-bridge is one comprising the two N-channel totem pole half-bridge outputs as shown in circuit 160 in
Like in the complementary H-bridge or half-bridge, an N-channel H-bridge comprising two half-bridge totem-pole outputs are driven out of phase to maximize the power delivered speaker 165. Unlike in driving low-side N-channel MOSFETs 162 and 164, however, high-side devices 161 and 163 are difficult to drive and must employ special floating gate drive circuits to operate properly from rail-to-rail, including driving their gates to voltages higher than Vcc, the most positive voltage in the system.
Limitations in Class-D Audio Output Stage ImplementationIn Class D switching amplifiers, each H-bridge drives a single speaker, so that four power MOSFETs are needed per each speaker output. Accordingly stereo requires 8 power devices, and five-channel surround sound systems need over 20 power MOSFETs, excluding the subwoofer driver.
Aside from fully integrated versions suffering a huge area penalty, class D power amplifier implementations using discrete devices require too many components. Moreover, no package exists to efficiently co-package the large number of discrete power device die and reduce the number of discrete components requiring mounting on a printed circuit board (PCB). Such a package should low thermal resistance, exhibit minimal resistance contributions from bonding and interconnection, and maintain uniform efficiency and drive capability among its audio channels.
Moreover, what is really needed is any design, architecture or circuit technique that enables the number of packaged die to be reduced, ideally down to two or three pieces of silicon, and still employ vertical power MOSFET technology with low specific on-resistance and simple fabrication techniques. Only then can class D audio amplification be achieved in an efficient and cost effective manner, especially at higher voltages and power outputs.
SUMMARY OF THE INVENTIONThe present invention includes several class D audio amplifiers that use vertical power MOSFET technology with low specific on-resistance and simple fabrication techniques. One such class D audio amplifier uses four P-channel high-side devices paired with four N-channel low-side devices as four half bridges. The N-channel devices share a common ground-connected source and have separate drain connected outputs. Similarly, the P-channel share a common Vcc-connected source and have separate drain connected outputs.
Using vertical DMOS technology, each power N and P channel device is implemented as a discrete device. The N and P channel devices are paired and the backside metal drain contact of each pair is attached to a shared die pad. The four pairs are included in a package along with leads for Vcc and ground (connected to the sources of the N and P channel devices respectively) and leads for the gates of each N and P channel. In a preferred embodiment the die pads comprise copper with lead extending to the package's exterior providing a current path with low electrical resistance and a heat path with low thermal resistance.
A second embodiment of a class D audio amplifier uses eight N-channel devices configured as four totem poles. Each totem includes a high-side N-channel device and a low-side N-channel device. All low-side N-channel devices share a common ground-connected source and have separate drain connected outputs. Conversely, all high-side N-channel devices share a common Vcc-connected drain and have separate source connected outputs. In a preferred embodiment, the Vcc-connected N-channels share a common copper die pad including leads extending to the package's exterior providing a current path with low electrical resistance and a heat path with low thermal resistance.
Using vertical DMOS technology, each low-side common-source connected power MOSFET is manufactured as a discrete device. However, all common-drain connected high-side N-channels can share a single piece of silicon. As such, the packaging of such a multi-chip solution requires a leadframe to accommodate six discrete die arranged in a regular and well matched symmetry. For one implementation four die pads are used to mounting the low-side N-channel devices and a fifth die pad is used for mounting the four high-side devices. The entire assembly is enclosed and encapsulated in plastic mold compound. In an alternative embodiment, common-drain connected high-side N-channels can be implemented as two pieces of silicon each comprising dual vertical power MOSFETs. In such implementations a total six die require assembly into a package.
As a preferred embodiment of this invention, a circuit-architecture is newly disclosed that eliminates the problem of co-packaging too many components and avoids the adverse costs associated with such complex assemblies. Instead of utilizing a half-bridge output comprising the aforementioned complementary or totem-pole push-pull configuration its uses an array of common-drain N-channel followers on the high-side and another array of common-drain P-channel followers on the low side.
While it may be considered wasteful, even illogical, to employ P-channel devices on the low-side because of their higher on-resistance for a given die area and the added difficulty imposed in realizing gate drive voltage below ground, it offers an unexpected benefit toward integration when employing vertical power MOSFET devices and fabrication processes. Properly implemented, the unexpected benefits of vertical device integration can more than offset the detriments of higher resistance and complex gate drive.
Specifically, a complementary follower for multiple channels can be realized in only two silicon dice using a monolithic array of grounded P-channel MOSFETs that share a common drain connection. Implemented as vertical P-channel DMOS, either trench-gated or planar, the drain connection comprises the backside of the die. The gate and source connections for each of the common drain P-channel MOSFETs are connected through bond wires to separate pins. In a preferred embodiment, the ground-connected P-channels share a common copper die pad including leads extending to the package's exterior providing a current path with low electrical resistance and a heat path with low thermal resistance.
The pull-up or high-side devices are included in a second silicon die containing an array of common drain N-channel DMOS power MOSFETs sharing a common drain connected to the positive power supply rail Vcc. Implemented as vertical N-channel DMOS, either trench-gated or planar, the drain connection comprises the backside of the die. The gate and source connections for each of the common drain N-channel MOSFETs are connected through bond wires to separate pins. In a preferred embodiment, the Vcc-connected N-channels share a common copper die pad including leads extending to the package's exterior providing a current path with low electrical resistance and a heat path with low thermal resistance.
In a class D audio amplifier, corresponding source connections from the high and low-side devices are electrically shorted together to form four complementary follower half-bridge outputs. Typically, the high-side N-channel vertical DMOS array is mounted on a Vcc-connected die pad and the low-side P-channel vertical DMOS array is mounted on a grounded die pad and both are contained in a single plastic package. The Two die pads can be shaped in several different ways for differing distributions with in the package.
To support operation of the complementary follower topology just described, it is necessary to provide gate voltages in excess of the rail voltage for the high-side devices, i.e. greater than the positive supply rail Vcc. Similarly, it is necessary to provide gate voltages that are less than ground for the low-side devices, gate voltages more negative than the negative supply rail.
One solution is to provide floating gate buffers that include bootstrap circuitry to provide the necessary gate drive voltages. Typically, this can be accomplished by including a bootstrap capacitor to boost the voltage available to drive the high and low-side devices (in the case of the low-side devices it is more accurate to provide a boosted inverted voltage). In one such implementation separate bootstrap gate drive circuitry is required for independent drive of each power MOSFET.
In operation, bootstrap drive involves constant switching where the high-side bootstrap capacitor is alternately charged from the rail voltage and then placed in series with the rail voltage (i.e. with the capacitor's negative terminal connected to Vcc) to provide a combined rail plus capacitor voltage that exceeds the voltage available from the rail alone. Low-side bootstrap operation is similar but having an inverted polarity and phase involving alternatively charging the bootstrap capacitor from the supply rail and then reconnecting the charged capacitor in series with ground (i.e. with the capacitor's positive terminal connected to ground) to provide a voltage that is more negative than ground.
Using complementary bootstrap drive a push-pull output comprising a complementary MOSFET follower can be implemented with low-resistance and rail-to-rail output drive capability. In one embodiment, the dead band where neither high-side nor low-side MOSFET conducts is controlled by the relative turn-on voltages of complementary level shifting circuitry which may include resistor level shift or cross coupled level shift techniques described below.
A second solution is to provide a power supply (switching or otherwise) that produces a first voltage (Vdd) that exceeds the rail voltage and a second voltage that is less than ground (−Vcc) and to utilize these two supply rails to power the complementary gate buffers. Power supplies of this type are described in U.S. Published Patent Application No. 2009/0039711, entitled “Dual-Polarity Multi-Output DC/DC Converters and Voltage Regulators,” which is incorporated in this document by reference.
Once the two voltages (Vdd and −Vcc) are available, it becomes a matter of appropriately generating high and low-side gate drives (VGHS and VGLS) as a function of an audio input signal. One disclosed method for generating the two gate drives, the complementary resistor level shift method, is to provide a first resistive divider for generating the high side gate drive voltage VGHS as a function of the audio input and a second resistive divider for generating the low side gate drive voltage VGLS. The first resistive divider includes a resistor and an NMOS device in series between Vdd and ground. In response to the amplifier's audio input signal a digital signal is applied to the gate of the NMOS device varying its gain and VGHS is obtained between the NMOS device and the resistor, switching between Vdd and near ground voltages. In a similar fashion, the second resistive divider includes a resistor and a PMOS device in series between Vcc and −Vcc. The digital control signal acting in response to the audio input signal is applied to the gate of the PMOS device varying its gain and VGLS is obtained between the PMOS device and the resistor, thereby switching between near −Vcc and near Vcc voltages. The two resistor level shifting circuits are driven out of phase in complementary fashion.
A more efficient method for generating the two gate-drives (VGHS and VGLS), herein referred to as complementary cross coupled level shifting, replaces the resistive dividers with an active level shifting topology. For one such topology, a first NMOS device and a first PMOS device are connected in series between Vdd and ground. A second NMOS device and a second PMOS device are also connected in series between Vdd and ground. The gates of the NMOS devices are cross connected to each other's drains. The audio signal drives the gate of the first PMOS device and its complement drives the gate of the second PMOS device. VGHS is derived between the first PMOS device and the first NMOS device. In effect, the complementarily switched NMOS devices level shift the audio signal and the pair of PMOS devices function as a cross connected as a latch to provide VGHS from Vdd.
VGLS is derived from −Vcc is in a similar fashion except that PMOS devices are used to perform level shifting and NMOS devices are used as the cross-connected latch. The level shifting PMOS devices are connected to Vcc and the NMOS devices are connected to −Vcc.
Both of the topologies just described (i.e., resistive and level-shifting) may be made more robust by adding a second stage. The second stage includes a PMOS device, a first resistor, a second resistor, a third resistor and an NMOS device all connected in series between Vdd and −Vcc. The gate of the PMOS device is controlled by what was described as the VGHS output of the resistive or level-shifting topology. The gate of the NMOS device is controlled by what was described as the VGLS output of the resistive or level-shifting topology. VGHS is derived between the first and second transistor and VGLS is derived between the second and third transistor. Addition of the second stage prevents overdrive of the transistors in the resistive and level-shifting topologies and decreases the likelihood of failure, and by controlling the dead band where neither high-side nor low-side MOSFETs conduct.
Another method that prevents gate overdrive uses shunt regulators instead of the second stage just described. For one such implementation, two gate buffers are added to the resistive divider topology previously described. One gate buffer supplies the high-side device using the voltage provided by the second resistive divider and the second gate buffer supplies the low-side device using the voltage provided by the second resistive divider. Two Zener diodes are also added. One of these diodes is placed between the source and gate of the high-side device. The second Zener diode is placed between the source and gate of the low-side device. In this way, the gate-source voltage of the high and low-side devices is limited to less than the Zener breakdown voltage BVZ. In such an implementation, a first current source is preferably placed between the +Vdd bias supply and the resistive divider and a second current source is placed between the second resistive divider and the +Vdd bias supply. This prevents the Zener diodes from being damaged by sourcing too much current. In a similar topology, the Zener diodes can be placed across the power supplies of the gate buffers.
Another shunt regulator clamped level shift circuit (shown in
Another shunt regulator clamped level shift circuit (shown in
Many of the class D amplifiers described above require a power supply (or supplies) that produces Vdd and −Vcc bias voltages. For one such power supply, a first P-channel device, an inductor and an N-channel device are connected between the input voltage −Vcc and ground. To simplify this description, it is assumed that a node Vy is located between the first P-channel device and the inductor and a node Vx is located between the inductor and the N-channel device. A second P-channel device connects the node Vy to a first output node (the −Vcc output node). The −Vcc output node is connected to ground by a first filter capacitor. A third P-channel device connects the node Vx to a second output node (the +Vdd output node). The +Vdd output node is connected to ground by a second filter capacitor.
Operation of the power supply involves using pulse width modulation or variable frequency techniques to control and regulate two outputs −Vcc and +Vdd. During a first phase of operation, the N-channel device and the first P-channel device are turned on building up current (i.e., magnetizing), the inductor. During this phase the second and third P-channel devices both remain off.
In the second phase of operation the first P-channel device and the N-channel device are both shut off in which case voltage Vx immediately flies up to a positive voltage from the inductor into the +Vdd capacitor. At the same time, Vy simultaneously flies negative to a below ground potential transferring energy from the inductor into the −Vcc capacitor.
The P and N-channel devices remain in this condition until the voltages across the capacitors reach their target value. When the +Vdd capacitor reaches its nominal value, the third P-channel device is turned OFF. After a break-before-make interval, the N-channel device is turned back on driving Vx to a voltage near ground. Meanwhile the inductor continues to transfer energy into the −Vcc capacitor.
When −Vcc finally reaches its nominal value, the second P-channel device is turned OFF and after a break-before-make interval, the first P-channel device is turned back ON driving Vy to a voltage near Vcc. Once the first P-channel device and the N-channel device are both conducting current and inductor begins to build up again, replenishing energy lost to filter capacitors and starting the cycle again.
In the sequence just described Vdd reached its final value before −Vcc. Thus, the flow of current to the Vdd output node was terminated while the flow of current to −Vcc continued. In the alternative (i.e., where −Vcc reaches it target value before Vdd) the opposite operation is performed and the flow of current to the Vdd output node continues while the flow of current to −Vcc is terminated.
In an alternative embodiment, transfer of energy to the filter capacitors can be alternated with magnetizing the inductor, i.e. alternating magnetizing, transferring energy into the +Vdd output capacitor, magnetizing the inductor again, transferring energy into the −Vcc output capacitor and repeating the cycle.
Another power supply that produces Vdd and −Vcc bias voltages uses a switched capacitor network to produce both negative and positive bias voltages. Specifically, as shown in
During a charging phase, a PMOS device and an NMOS device are both turned ON connecting the flying capacitor between an input supply Vcc and ground. The remaining MOSFETS in the network are turned OFF. As a result, the flying capacitor is charged to approximately Vcc.
During a first charge transfer phase, the PMOS and NMOS devices are turned OFF. Two more MOSFETS are turned ON connecting the negative pole of the flying capacitor to the input voltage Vcc and the positive pole of the capacitor to the +Vdd output capacitor. In this way, the voltage combined voltage of the flying capacitor and the input supply Vcc are applied to the +Vdd output capacitor. After the first charge transfer phase is repeated several times, the +Vdd capacitor will charge to a value approximately equal to twice the input voltage Vcc.
The charging phase is then repeated. Once completed, a second charge transfer phase is initiated. In the second charge transfer phase, the positive pole of the flying capacitor is connected to ground and the negative pole of the flying capacitor is connected to the −Vcc output capacitor. In this way, a voltage of approximately −Vcc is applied to the −Vcc output capacitor.
Using either one of these methods or by using separate power supplies the bias supplies +Vdd and −Vcc may be generated to power the gate buffers in class-D audio amplifiers.
As shown in
To generate the negative output −Vcc, the second flying capacitor is second charged to approximately −Vcc and then connected between the −Vcc output capacitor and ground. During charging, the second flying capacitor is connected to the ground using a dedicated MOSFET. At the same time, the second flying capacitor is connected to the power input Vcc through the half-bridge. During discharge, the second flying capacitor is connected to ground through the half-bridge and connected to the −Vcc output capacitor using another dedicated MOSFET.
As shown in
Using the aforementioned methods, integrating the H-bridge complementary-follower with bias generator and speaker drivers for class-D audio applications can be achieved in three silicon die which may be packaged separately or assembled into a single plastic package. For example,
Implementation of class-D audio amplification involves several elements, primarily the class D audio signal processing, the gate drive and level shifting circuitry, the DMOS output stage and in some cases a dedicated bias supply for the gate drivers. The disclosed invention considers all of these elements except for the requisite signal processing.
H-Bridge Assembly of Vertical DMOSUsing vertical DMOS technology, each power MOSFET is manufactured as a discrete device and cannot be integrated with any other devices. The packaging of such a multi-chip solution requires a leadframe to accommodate eight discrete die arranged in a regular and well matched symmetry. For example, the plan view in
N-channel and P-channel vertical DMOS 204A and 205A both include backside metalized drain contacts, typically comprising a deposited tri-metal back-metal sandwich of titanium, nickel, and silver. The dice are typically die-attached to die pad 201A using silver-filled conductive epoxy although soft solder can also be employed. Leads connected to die pad 201A provide electrical connections to pins labeled “A” while providing mechanical support to the surrounding leadframe rails during assembly, i.e. before trim and form operations. Similarly, N-channel 204B and P-channel 205B share die-pad 201B with attached output pins “B”. The die pad connected pins also provide heat sinking of the power devices.
As shown, source bond wires connect the top of N-channel DMOS die 204A and 204B to common GND connected pins 203A. Two wires per die are employed to minimize the resistance contribution of the bond wires. Similarly, source bond wires connect the top of P-channel DMOS die 205A and 205B to common Vcc-connected pins 203C. Two wires per die are employed to minimize the resistance contribution of the bond wires. Gate wires G1 through G4 are connected to separate pins 202.
In similar arrangement, N-channel 204C and P-channel 205C share die pad 201C with “C” connected pins, N-channel 204D and P-channel 205D share die pad 201D with “D” connected pins, and where N-channels 204C and 204D include source bond wires tied to ground connected pins 203B, and P-channels 205C and 205D include bond wires to Vcc-connected pins 203D. The entire assembly is enclosed and encapsulated in plastic mold compound 210.
Using vertical DMOS technology, each low-side common-source-connected power MOSFET is manufactured as a discrete device and cannot be integrated with any other devices. All common-drain connected high-side N-channels 224 can share a single piece of silicon. If the aspect ratio, the ratio of die length to die width, is too extreme for manufacturing the common drain high-side N-channels as one die, they may be split into two as shown in assembly 240.
As such, the packaging of such a multi-chip solution requires a leadframe to accommodate six discrete die arranged in a regular and well matched symmetry. For example, the plan view in
N-channel vertical DMOS 244 and 245 both include backside metalized drain contacts, typically comprising a deposited tri-metal back-metal sandwich of titanium, nickel, and silver. The dice are typically die-attached to die pads 241 or 243 using silver-filled conductive epoxy although soft solder can also be employed. Leads connected to die pads 241 and 243 provide electrical connections to the pins while providing mechanical support to the surrounding leadframe rails during assembly, i.e. before trim and form operations. The die pad connected pins also provide heat sinking of the power devices.
As shown source bond wires connect the top of N-channel DMOS die 244A and 244B to common GND connected pins 246A. Two wires per die are employed to minimize the resistance contribution of the bond wires. Similarly, source bond wires connect the top of N-channel DMOS die 245A and 245B to output-connected pins 247A and 247B. Two wires per die are employed to minimize the resistance contribution of the bond wires. Gate wires 251 G1 through G4 are connected to separate pins 242.
In similar arrangement, N-channel 244C employs dedicated die pad 241C with “C” connected pin, N-channel 244D employs die pad 241D with “D” connected pins, and where N-channels 246C and 246D share Vcc connected die pad 243 and include separate source bond wires tied to output connected pins 247C, and 247D. The entire assembly is enclosed and encapsulated in plastic mold compound 250.
In its application in a class D amplifier, assembly 240 requires low-side N-channel drain pin 241A to be connected on the printed circuit board to high-side source pin 247A to electrically complete the half-bridge as output “A”. Similarly, board level connections are needed to short low-side drain connections 241B, 241C, and 241D to respective high-side follower outputs 247B, 247C and 247D.
In an alternative assembly 260 shown in
Surrounding H-shaped Vcc-connected die pad 263, separate die pads 262A through 262D are employed to mount discrete low-side MOSFETs 265A through 265D respectively. The source connections of high-side N-channels 266 are connected by bond wires 272 to the die-pad connected pins 262A through 262D, electrically connecting high-side source and low-side drains to produce outputs A, B, C and D. The source connections of low-side DMOS 265 are connected by bond wires 273 to grounded pin straps 261A and 261B located at the package's edges. The entire eight-MOSFET assembly 260, containing five distinct pieces of silicon, is molded by plastic 270 to complete the packaged solution.
Even through assembly 260 requires only five die, the assembly and the electrical yield of multi-chip packaging is much higher using only three and ideally only two dice in the assembly process. This is because is manufacturing, the assembly yields Yn for each of N mounted die multiply. i.e. Ytotal=Y1·Y2·Y3·Yn.
But as shown previously, the common source N-channel low-side MOSFET solution forces manufacturers to use four discrete low-side N-channels device. Complementary highs-side P-channel devices require another 4 devices in the same package, compared to one or two additional dice using high-side N-channel devices and totem pole outputs. Even with five separate dice, the manufacturing yield and finished-goods cost is adversely affected.
New Complementary Follower ArchitectureAs another embodiment of this invention, a circuit-architecture is newly disclosed that eliminates the problem of co-packaging too many components and avoids the adverse costs associated with such complex assemblies. Instead of utilizing a half-bridge output comprising the aforementioned complementary or totem-pole push-pull configuration its uses a circuit topology never used for class-D power output stages.
The alternative topology described herein is a complementary follower, comprising an array of common-drain N-channel followers on the high-side and another array of common-drain P-channel followers on the low side. Clearly, ground connected P-channel MOSFETs have a higher specific resistance than N-channels and require special gate drive circuitry too.
So while it may be considered wasteful, even illogical, to employ P-channel DMOS on the low-side, it offers an unexpected benefit toward integration when employing vertical power MOSFET devices and fabrication processes. Properly implemented, the unexpected benefits of vertical device integration can more than offset the detriments of a P-channel's higher resistance (as compared to N-channel MOSFETs) and the complex gate drive required by P-channel followers.
Specifically, a complementary follower for multiple channels can be realized in only two silicon dice as shown in schematic 300 of
The gate and source connections for each of the common drain P-channel MOSFETs are connected through bond wires to separate pins. Transistor 305A for example has its source connected to pin SP1 its gate connected to pin GP1, and its drain tied to common drain pin DP. By grounding the DP pin and biasing the source of DMOS 305A with only positive voltages, the MOSFETs integral drain-body diode 306A remains reversed biased at all times. Similarly diode 306B within P-channel DMOS 305B remains reversed biased, as does intrinsic diode 306C in DMOS 305C and intrinsic diode 306D in DMOS 306D.
The pull-up or high-side devices in multi-channel complementary follower circuit 300 comprise a second silicon die 302A containing an array of common drain N-channel DMOS power MOSFETs 303A, 303B, 303C and 303D sharing a common drain connection DN connected to the positive power supply rail Vcc. Implemented as vertical N-channel DMOS, either trench-gated or planar, the DN connection comprises the backside of the die. The die's backside of silicon 302A as shown is attached to a common conductive die pad 301A, providing electrical and thermal connections to the common drain N-channel DMOS power MOSFET array.
The gate and source connections for each of the common drain N-channel MOSFETs are connected through bond wires to separate pins. Transistor 303A for example has its source connected to pin SN1, its gate connected to pin GN1, and its drain tied to common drain pin DN. By powering the DN pin with the most positive circuit voltage Vcc and biasing the source of DMOS 303A with only voltages more negative than Vcc, the MOSFET's integral drain-body diode 304A remains reversed biased at all times. Similarly diode 304B within N-channel DMOS 303B remains reversed biased, as does intrinsic diode 304C in DMOS 303C and intrinsic diode 304D in DMOS 303D.
In a class D audio amplifier, corresponding source connections SN and SP are electrically shorted together to form multiple complementary follower half-bridge outputs, in this example, four. For example, connecting pins SN1 and SP1 together electrically forms half-bridge “A” comprising N-channel high-side DMOS 303A and P-channel low-side DMOS 305A, both as source followers. For any output voltage between ground and Vcc, both diodes 304A and 306A remain reverse biased. Similarly, pins SN2 and SP2 connect MOSFETs 303B and 305B to produce output B, pins SN3 and SP3 connect MOSFETs 30CB and 305C to produce output C, and pins SN4 and SP4 connect MOSFETs 303D and 305D to produce output D.
Using a complementary source follower implementation,
N-channel high-side array 336 includes four common-drain N-channel MOSFETs 326A, 326B, 326C and 326D with corresponding source outputs SN1, SN2, SN3, and SN4 and respective gate connections GN1, GN2, GN3 and GN4. The backside drain of die 336 is connected to Vcc through a conductive epoxy die attach to copper leadframe 322A. As part of die pad 322A, two Vcc-connected leads provide a low resistance electrical connection to the N-channel MOSFET's common drain, facilitate a heat path from die 336 to the printed circuit board, and provide mechanical support during the assembly process. Tie bars 322B and 322C provide added stability during the die attach process.
P-channel low-side array 337 includes four common-drain P-channel MOSFETs 327A, 327B, 327C and 327D with corresponding source outputs SN1, SN2, SN3, and SN4 and respective gate connections GP1, GP2, GP3 and GP4. The backside drain of die 337 is connected to Vcc through a conductive epoxy die attach to copper leadframe 321A. As part of die pad 321A, two ground-connected leads provide a low resistance electrical connection to the P-channel MOSFET's common drain, facilitate a heat path from die 337 to the printed circuit board, and provide mechanical support during the assembly process. Tie bars 321B and 321C provide added stability during the die attach process.
As shown, gold or aluminum wire bonds 331 are used to connect the source outputs of the vertical MOSFETs to T-shaped copper leads 323. Gate connections use bond wires 332 to connect to straight leads 324. To complete the connection, printed circuit board traces are used to electrically connect pins SN1 and SP1 to form output A; pins SN2 and SP2 to form output B; pins SN3 and SP3 to form output C; pins SN4 and SP4 to form output D. Alternatively, a stitch wire bond may connect the source of N-channel 326A to the source of P-channel 327A and to leads SN1 and SP1 inside the package itself.
Internal to assembly 340, N-channel DMOS array 355 includes MOSFETs 346A, 346B, 346C and 346D with corresponding source connections SN1, SN2, SN3 and SN4 and corresponding gate connections GN1, GN2, GN3 and GN4. The backside of die 355 forms the common drain of the N-channel vertical DMOS array and is connected to Vcc through H-shaped copper lead frame 341. In similar construction, P-channel DMOS array 356 includes MOSFETs 347A, 347B, 347C and 347D with corresponding source connections SP1, SP2, SP3 and SP4 and corresponding gate connections GP1, GP2, GP3 and GP4. The backside of die 356 forms the common drain of the P-channel vertical DMOS array and is connected to ground through H-shaped copper lead frame 351.
Source bond wires 351 connect the surface of the DMOS to T-shaped leads 343. Gate bond wires 352 connect the individual MOSFET gates to leads 344. An area efficient low-resistance package with four half-bridge outputs A, B, C and D is therefore facilitated using only two silicon dice, 355 and 356.
Using half-bridges comprising complementary followers, the power circuit for class-D audio amplification can be realized with circuit 360 of
Similarly, speaker 36BA is driven by two Vcc-connected high-side N-channel MOSFET source followers 362C and 362D with output pins SN3 and SN4 connected to pins SP3 and SP4 of grounded P-channel source follower MOSFETs 361C and 361D. In a preferred embodiment outputs C and D are driven out of phase to maximize the power output of the amplifier for a given supply voltage Vcc.
Operation of half-bridge outputs A and B is completely independent of C and D. Even so grounded P-channel MOSFETs 361A, 361B, 361C and 361D may share a common silicon die using a P-channel vertical DMOS power MOSFET process with low-specific on-resistance. Using principals of symmetry, Vcc-connected N-channel MOSFETs 362A, 362B, 362C and 362D may also share a common silicon die using an N-channel vertical DMOS power MOSFET process with low-specific on-resistance.
The entire stereo class-D amplifier can then be realized in a small area with efficient low on-resistance vertical power MOSFETs. The complementary follower architecture is counter intuitive and is not used in power applications. In fact, conventional CMOS circuit design teaches forming power push-pull buffers using grounded low-side N-channel MOSFETs combined with high-side Vcc-connected P-channel MOSFETs. Such “common-source” configured CMOS buffers connect the transistors' source connections to their respective supply rails and short the drain connections together to form the output. As illustrated in
Since conventional CMOS design methods teach the use of complementary common source configured push-pull outputs, they actually teach away from the use of complementary follower configured outputs in class D power amplifiers. As such, physical realization of a stereo power output requires a large number a components or integration using monolithic integration.
In contrast, using the complementary follower architecture of circuit 360 in
The area and cost advantage of such an approach can be estimated using some conservative “rules-of-thumb” to make some simple comparisons. Assume for example the specific on-resistance RDSA of lateral 30V MOSFET is four times that of comparable vertical DMOS devices and that P-channel MOSFETs have a resistance 2.5 times that of a comparably constructed N-channel MOSFET. Assume furthermore that vertical DMOS require six masking operations to manufacture while most CMOS IC processes require 18 layers, roughly triple the cost of the vertical discrete manufacturing process. A summary table is shown here with RDSA and cost relative to vertical N-channel TrenchDMOS devices fabricated using 0.4 micron design rules and a 287 Mcells/in2 active cell density.
Using the above relative factors we can calculate and compare the area needed to achieve full stereo class D amplification using eight transistors to form four half-bridges using various approaches.
From the above, if four N-channel TrenchDMOS vertical power MOSFETs take an area of 4 units, then four P-channel vertical TrenchDMOS require an area 2.5·4=10. So a totem pole N-channel discrete implementation takes an area of 8 while a complementary version of discrete devices, either common source or source follower takes an area of 14, i.e. 75% more area than the N-channel discrete solution.
At a 30V breakdown rating, the integrated circuit NMOS takes an area of 16, four times the vertical device and the PMOS takes an area 4 times that of the vertical P-channel, or 4·10=40. The total area of 56 in an IC is therefore 4 to 7 times that of discrete implementations. Moreover, the cost of the IC die is three times higher than the comparable area vertical device, at a relative value of 168, at least 12 times higher than using discrete TrenchDMOS vertical power MOSFETs.
When yield loss during assembly is considered, then even if the yield per die is 96% the overall yield is given by (96%)*n where n is the number of die mounted down in assembly. The yield adjusted cost is then given by Cost/Yield where * indicates the actual assembly cost is not included. Even ignoring the assembly manufacturing cost itself, the source follower solution with an effective cost of 15.2 is the second best solution. But when the actual manufacturability and through-put is considered, the effective cost and risk associated with the assembly of 5 or 6 die makes the totem pole N-channel discrete solution of
Driving a complementary follower for high efficiency operation in class-D audio amplification is not trivial. As shown in schematic 380 of
Specifically as shown in graph 390 the output of the follower has a maximum output voltage equal to (Vcc−Vtn) as shown by curve 393. For any output higher than that, N-channel high-side 383 turns off and can no longer source current. Similarly, curve 391 reveals that when VG is zero volts, P-channel MOSFET 382 can only sink currents for output voltages down to its threshold voltage Vtp. Beyond the P-channel devices turns off.
Since circuit 380 cannot swing rail-to-rail is suffers from poor efficiency. What is needed is gate drive circuitry which operates beyond the supply rails, i.e. below ground and above Vcc. Such circuitry will support full rail-to-rail switching in the power complementary follower output stage.
Another characteristics of complementary follower circuit 380 is its dead-band around the input and output voltage of Vcc/2. In this narrow range ΔV neither transistor is on or conducting current, so that the output Vout can neither sink nor source current. The width of the dead-band is equal to the sum of the threshold voltages (Vtn+Vtp). While shoot-through protection is needed, too wide of a dead-band is detrimental to smoothly modulating a wide range of PWM duty factors.
One remedy to the dead-band and maximum-minimum common-mode range limitations of circuit 380 is illustrated in
This relation can be understood by considering when low-side MOSFET 404 is on and Vout=0. During such time bootstrap diode 408 forward biases and charges bootstrap capacitor 409 to a voltage one diode drop Vf less than the supply Vcc. This capacitor in turn powers floating buffer 412 to drive the gate of N-channel follower 403 to a voltage Van above its source and turns on MOSFET 403. The signal input to buffer 412 is illustrated using a resistive level shift technique with N-channel 414 and resistor 413. When Vout=Vcc the gate voltage VGN is biased at approximately Vout+VBH, which is higher than the supply voltage Vcc. For this reason Vout can source current for all output voltages up to Vcc.
Conversely, when N-channel MOSFET 403 is on, low-side MOSFET 404 is off and Vout=Vcc, then diode 407 forward biases and charges capacitor 410 to a voltage VBL where
VGP=Vout−VBL=Vout−(Vcc−Vf)
for a corresponding gate to source voltage of
VGSP=−VBL=−(Vcc−Vf)
Low-side bootstrap capacitor 410 then powers floating gate buffer 401 to drive the gate of MOSFET 404 below ground so that P-channel follower 404 can continue to sink current for output voltages Vout all the way down to ground potential. Buffer 401 is turned on and off by the gate signals Vin driving a negative level shift circuit comprising P-channel 412 and resistor 411. This signal is opposite in polarity to the signal turning on high-side buffer 412 and MOSFET 403.
The transfer characteristic of the complementary follower with complementary bootstrap drive is illustrated in graph 420 of
Notice that by employing two bootstrap capacitors, capacitor 409 on the high side, and capacitor 410 on the low side the output power MOSFETs 403 and 404 can be made to source and sink current on the output pin Vout from rail-to-rail, i.e. from Vcc to ground. The inventive complementary bootstrap drive circuit 400 does however require two bootstrap capacitors, generally connected external to the driver circuit. The extra pins needed to connect these capacitors, however, can result in package pin limitations
Another disadvantage of level shifting and complementary bootstrap driver 400 is that either resistor 413 or 411 burns power while it conducts current, even in its quiescent state. One improvement on this level shift circuit is to replace the resistors with cross coupled latch circuits which only consume power only during transitions, and not under quiescent states. Circuit 450 illustrates an improved complementary bootstrap circuit using NMOS level shift transistors 471 and 472 driven out of phase to set a latch comprising cross coupled PMOS 473 and 474, the output of which powers floating CMOS gate buffer 456 which in turn drives the gate of N-channel follower 451.
Bootstrap capacitor 457 is charged to a voltage VBH whenever Vout is at ground, i.e. when P-channel 452 is on and N-channel 451 is off. The capacitor is charged to a voltage VGSHSS=VBH−Vout=(Vcc−Vf) through diode 459. The diode drop Vf can be eliminated by including P-channel MOSFET 461 which conducts whenever capacitor 457 is being charged, so that VGSHSS=VBH−Vout≈Vcc.
The negative going bootstrap circuit operates in a similar manner to the positive floating gate drive. As shown in 450, PMOS level shift transistors 467 and 468 are driven out of phase to set a latch comprising cross coupled NMOS 469 and 470, the output of which powers floating CMOS gate buffer 455 which in turn drives the gate of P-channel follower 452. Bootstrap capacitor 458 is charged to a voltage −VBL whenever Vout is at Vcc, i.e. when N-channel 451 is on and P-channel 452 is off. The capacitor is charged to a voltage VGSLSS=Vout−VBH=−(Vcc−Vf) through diode 460. The diode drop Vf can be eliminated by including N-channel MOSFET 462 which conducts whenever capacitor 458 is being charged, so that VGSLSS=Vout−VBH≈−Vcc.
Complementary bootstrap drive is self-biasing, meaning that each half-bridge alternatively charges and discharges its bootstrap capacitors during every switching cycle in order to drive its high-side N-channel gate above Vcc and its low-side P-channel gate below ground. The disadvantage of this approach is that every half-bridge requires two bootstrap capacitors. This limitation is shown in schematic 500 of
Similarly BBM buffer 502B with capacitors 503C and 503D powers power MOSFETs 505B and 506B, BBM buffer 502C with capacitors 503E and 503F powers power MOSFETs 505C and 506C, and BBM buffer 502D with capacitors 503G and 503H powers power MOSFETs 505D and 506D, all under the control of class D audio digital controller 501. Logic level PWM signals a, b, c and d are therefore translated into high current capable power outputs A, B, C, and D.
The pin-out limitation becomes evident in
A preferred embodiment of this invention eliminates the majority of these bootstrap capacitors by sharing a dual polarity bias supply for powering the gate driver circuitry.
Dual Polarity Bias Supply for Complementary DriveAn alternative to dedicated floating bootstrap drive for each half-bridge is to share a dual polarity bias supply for powering the gate buffer circuitry. This method is illustrated in schematic 550 of
Gate buffer 536A, powered by +Vdd and −Vee bias supplies, drives N-channel high-side MOSFET 569A and P-channel low-side 567A. Similarly gate buffer 536B powers N-channel 569B and P-channel 567B, gate buffer 536C powers N-channel 569C and P-channel 567C, and gate buffer 536D powers N-channel 569D and P-channel 567D. This approach eliminates the bootstrap capacitors on each half-bridge, and requires only two reservoir capacitors 554 and 553 for the entire class D stereo system. Circuit 550 does, however, require DC/DC converter 552 to generate the dual polarity bias supplies +Vdd and −Vcc needed for powering the gate buffers.
Gate buffers 526A through 536D convert logic signals, a, b, c, and d into power outputs A, B, C and D by facilitating level shifting to drive the gates of source-follower MOSFETs 567 and 569 with gate voltages extending above the Vcc supply range and below ground. One such level shifting circuit 600 illustrated in
At the same time a logic “high” input is inverted by gate 607 and turns on level shift PMOS 604. The current conducting in PMOS 604 produces a voltage drop across resistor 603, pulling up the low-side MOSFET's gate voltage VGP to Vcc and shutting off P-channel follower 601. With N-channel DMOS 602 conducting and P-channel DMOS 601 off, the output voltage of pin A is high, i.e. equal to Vcc.
In the opposite phase, the input is low turning NMOS 606 on and PMOS 604 off, allowing current to flow through resistor 605 which in turn drives high-side gate voltage VGN to ground and turns off N-channel source follower DMOS 602. Meanwhile with no current flowing through level shift PMOS 604, resistor 603 pulls the gate of low-side P-channel DMOS follower 601 down below ground to a voltage −Vcc, allowing P-channel 601 to sink current from the output even when Vout=0.
By switching the gate voltage VGN of high-side N-channel DMOS 602 between +Vdd and ground while the gate voltage VGP of low-side P-channel DMOS 601 switches from Vcc to −Vcc, the output voltage at pin A is able to swing rail-to-rail from +Vcc to ground.
The maximum turn-on rate for N-channel follower 602 is set by the value R2 of resistor 605. The maximum turn-on rate for P-channel follower 601 is determined by the value R1 of resistor 603. The size and current capability of NMOS 606 and PMOS 604 determine the turn off rate of power DMOS transistors 602 and 601.
To eliminate DC quiescent current in level shift resistors 603 and 605, circuit 620 in
One consideration in level-shifting gate drive circuitry for a complementary follower power half-bridge is preventing overdrive of its gates. Rapidly applying a gate bias to a power MOSFET outside of the supply rail could inadvertently exceed the maximum gate voltage VGS(max), even briefly, and damage the power transistors' gate oxide. The value of VGS(max) for a power MOSFET can be estimated knowing a transistor's gate oxide thickness xox as per the relation
VGS(max)=(4 MV/cm)·xox
An intelligent gate driver which limits the instantaneous bias applied to the gates of both high-side N-channel and low-side P-channel followers is mandated. In the prior gate drivers 600 and 620, limiting gate overdrive during turn-on can only be accomplished by slowing down transitions. Voltage overshoot is controlled by limiting the current supplied by the +Vdd and −Vcc bias supplies to the MOSFETs' gates using either resistors 605 and 603, or by under-sizing MOSFETs 634 and 628.
Other methods to prevent over-voltage and voltage over-shoot on the output transistors' gates are illustrated in
In the opposite phase, the speed of pulling the gate of low-side P-channel 652 below ground to −Vcc, is primarily determined by resistance R3 of resistor 655 while R4 of resistor 654 contributes to the turn-off of high side follower 651. Even though turn off of MOSFET 651 is delayed past turn on of 652, no shoot-through occurs because of the built-in dead-band intrinsic to the complementary source follower circuitry.
A similar modification to circuit 620 is shown in level shift circuit 690 of
The impact of the resistors on the break-before-make (BBM) dead-band can be understood by inspecting simplified level shift circuit 720 of
Conversely, turning-on low-side P-channel follower 721 is determined by the current sinking capability of −Vcc-connected NMOS 724 while the turn off of high-side N-channel 722 is determined by resistor 725. As such the negative transition of VGL leads VGH during turn on of low-side MOSFET 721, delaying the turn-off of high-side follower 722 to a later time and voltage a lower voltage and bringing the two output devices 721 and 722 closer to a shoot-though condition.
The net effect of resistor 725 is to narrow the intrinsic dead-band of the complementary follower's transfer characteristic 730 shown in
If R was chosen to be very large, i.e. R→∞, and a high voltage must be imposed on VGH by conducting PMOS 723 before VGL will start to become biased in a positive polarity, essentially making it more difficult to turn off low-side P-channel 721 and narrowing the dead-band to a value less than the sum of the thresholds (Vtn+Vtp). Resistors 654 and 694 in level shift circuitry 650 and 690 exhibit the same effect as resistor 725 in circuit 720, except that additional resistors are added to control the source and sink currents supplied by the bias supplies +Vdd and −Vcc.
In an alternate embodiment of level shifting gate drive circuitry in
In shunt regulated level shift circuit 750 of
Another shunt regulator clamped level shift circuit is illustrated in circuit 790 of
Unlike in circuit 750 where Zener 761 is a power clamp, the current limiting 810 in circuit 790 is not critical since Zener 796 only has to limit the gate bias of follower 793. Similarly Zener diode 804 clamps the voltage across inverters 803 and 802 and drives the gate of −Vcc-connected PMOS follower 801, thereby limiting the maximum VGSP on MOSFET 792 to a voltage of (BVZ−Vtp). Notice the high current path for charging the gates of MOSFETs 791 and 792 flows directly from the +Vdd and −Vcc bias supplies through source followers 793 and 801 without the need for Zener diodes 796 and 804 and current sources 810 and 811 to carry high currents. Aside from its Zener clamping and shunt regulation, level shift 790 operates similar to level shift circuit 620.
In a symmetrical circuit, gate buffer 833 driving the gate of P-channel low-side follower 832 is powered from the output of a floating linear regulator circuit comprising NMOS pass element 847 controlled by amplifier 846. Feedback of the linear regulators output voltage across capacitor 840 is adjusted by resistor divider 841 and 842 and compared to floating voltage reference Vref thereby limiting the maximum voltage applied to CMOS buffer 833 to a potential safe for the gate oxide of N-channel DMOS 832. Since the linear regulator is referenced to the source of MOSFET 832, the entire circuit floats with the output. The voltage differential between −Vcc and the floating voltage Vout−ΔVLS is dropped across the drain-to-source terminals of NMOS 847. PMOS 835 and resistor 834 provide the negative level-shifted gate signal to buffer 833.
Dual Polarity Bias SuppliesReferring again to class D audio amplifier 550 of
Dual-Polarity Switched Inductor Regulator:
Specifically,
The converter outputs two supply voltages, one positive +Vdd and another negative −Vcc, both filtered by output capacitors 879 and 880.
Operation of DC/DC converter involves using pulse width modulation or variable frequency techniques to control and regulate two outputs −Vcc and +Vdd. Operation involves turning on PMOS 872 and NMOS 873 simultaneously for a time ton and building up current, i.e. magnetizing, inductor 874. During that time Vx is biased near ground at a voltage equal to IL·RDSN, the inductor current IL times the on-resistance RDSN of NMOS power transistor 873. At the same time, Vy is biased to a voltage nearly that of the converter's input Vcc, namely (Vcc−IL·RDSP) where RDSP is the on-resistance of PMOS power MOSFET 872. During this cycle both synchronous rectifiers 875 and 877 remain off. Assuming capacitor 879 is charged to a below ground voltage −Vcc and capacitor 880 is charged to a positive voltage +Vdd>Vcc, the intrinsic P-N diodes 876 and 877 remain reverse biased during this interval.
In the second phase of operation PMOS 872 and NMOS 873 are both shut off in which case voltage Vx immediately flies up to a positive voltage above both Vcc and +Vdd and forward biases diode 878. The positive transient is clamped at a voltage Vx equal to (+Vdd+Vf), transferring energy from inductor 874 into capacitor 880. The voltage Vf is the forward bias voltage of P-N diode 878. In tandem with Vx flying high, Vy simultaneously flies negative to a below ground potential. The negative going transient is clamped to a negative voltage Vy=(−Vcc−Vf), transferring energy from inductor 874 into capacitor 879 through forward biased diode 876. In this case, the voltage Vf is the forward bias voltage of P-N diode 876. For simplicity's sake, the forward drop Vf can be approximated to be the same drop across diode 878 and 876 since they are carrying similar currents.
Subsequent to turning MOSFETs 872 and 873 off, and after a minimum break-before-make (BBM) interval tBBM, synchronous rectifier MOSFETs 875 and 878 are turned on and shunt the current flowing in diodes 876 and 878, during which time Vx=Vdd+IL·RDSP and Vy=−Vcc−IL·RDSN
The MOSFETs remain in this condition until the voltages across capacitors 879 and 880 reach their nominal value as determined by PWM controller 871 responding to feedback signals VFB2 and VFB1 monitoring the −Vcc and +Vdd outputs. When +Vdd reaches its nominal value synchronous rectifier MOSFET 877 is turned off and after a break-before-make interval tBBM, NMOS 873 is turned back on driving Vx to a voltage near ground and reverse biasing diode 878. Meanwhile inductor 874 continues to transfer energy into capacitor 879.
When −Vcc finally reaches its nominal value synchronous rectifier MOSFET 875 is turned off and after a break-before-make interval tBBM, PMOS 872 is turned back on driving Vy to a voltage near Vcc and reverse biasing diode 876. Once both PMOS 872 and NMOS 873 are both conducting current in inductor 874 begins to build up again, replenishing energy lost to output capacitors 879 and 880 and starting the cycle again.
In the sequence described Vdd reached its final value before −Vcc. In such case the converter 870 continued to supply power to −Vcc and capacitor 879 for a longer duration than to capacitor 880. In the contrary case if −Vcc reaches its target value sooner than +Vdd, then the sequence can reverse where first synchronous rectifier 875 is turned off and then PMOS 872 is turned on, driving Vy up to a voltage near Vcc and reverse biasing diode 876. During this time current can continue to flow through synchronous rectifier 877 into capacitor 880 and output +Vdd. Later when +Vdd reaches it target value synchronous rectifier 873 is turned off, and a tBBM interval later NMOS 873 is turned on, once again reenergizing inductor 874.
In steady state, duty factor control requires the energy put in to inductor 874 must be equal to the amount removed during the time when NMOS 873, PMOS 872 or both are off. Since either NMOS 873 or PMOS 872 can be switched independently, the control of energy transfer from inductor 874 to capacitor 979 and to capacitor 880 is independently controllable.
In an alternative embodiment the synchronous rectifier timing can be alternated with magnetizing the inductor, i.e. alternating magnetizing, transferring energy into the +Vdd output capacitor, magnetizing the inductor again, transferring energy into the −Vcc output capacitor and repeating the cycle. In detail, operation commences by turning on both PMOS 872 and 873 to magnetize inductor 874, then after a time ton1, turning off NMOS 873. After a delay tBBM, synchronous rectifier 877 is turned on till Vdd reaches its target value. Next synchronous rectifier 877 is shut off and after tBBM NMOS 873 is again turned on, thereby magnetizing inductor 874 for a time ton2.
In the next phase PMOS 872 is turned off, and after tBBM synchronous rectifier 875 is turned on transferring energy to capacitor 879 and to the −Vcc output. After −Vcc reaches its target value synchronous rectifier 875 is turned off and after a time tBBM, PMOS 872 is turned on, once again magnetizing inductor 874. In this way interval ton1 replenishes the energy lost to the −Vcc output and ton2 replenishes the energy lost to the +Vdd output, allowing nearly independent control of two regulated outputs from a single inductor.
In converter 870, the synchronous rectifiers may be switched digitally, between off, i.e. with no current, to “on” with the device's lowest possible on-resistance. Alternatively the synchronous rectifier may be operated in a manner where it never turns off, but always allows some current to flow through it. Operation of a saturated MOSFET where VDS>VGS−Vt is a well known method to produce a constant current source. Synchronous rectification alternating between a low on-resistance state and a constant-current state as described in U.S. Published Patent Application No. 2008/0084197, entitled “Low-Noise DC/DC Converter With Controlled Diode Conduction” by Richard K. Williams has certain benefits in achieving low noise and improved efficiency in switching regulators and is incorporated herein by reference.
Dual-Polarity Switched Capacitor Bias Supply:
Specifically,
Operation of dual polarity output charge pump circuit 900 commences with the charging of flying capacitor 902 by turning on PMOS 901 and NMOS 903, whereby capacitor 902 charges to a voltage Vfly approximately equal to Vcc. This condition is referred to herein as the charging phase.
During a first charge transfer phase, MOSFETs 901 and 903 are turned off and MOSFET 904 and 906 are turned on. By connecting the negative terminal Vy of flying capacitor 902 to Vcc through MOSFET 904, the voltage at Vx immediately jumps to (Vcc+Vfly)≈2·Vcc which is then transferred to capacitor 908 through conducting MOSFET 906. In steady state the output voltage +Vdd will charge to a value approximately equal to twice the input voltage Vcc. After the first charge transfer phase MOSFETs 904 and 906 are turned off and MOSFETs 901 and 903 are turned on, replenishing the charge on flying capacitor 902, once again charging it to a voltage Vcc.
In a second charge transfer phase, MOSFETs 901 and 903 are turned off and MOSFET 905 and 907 are turned on. By connecting the positive terminal Vx of flying capacitor 902 to ground through MOSFET 905, the voltage at Vy immediately jumps to (0−Vfly)≈−Vcc which is then transferred to capacitor 909 through conducting MOSFET 909. In steady state the output voltage −Vcc will charge to a value approximately equal to the negative of the input voltage Vcc.
After the second charge transfer phase MOSFETs 905 and 907 are turned off and MOSFETs 901 and 903 are turned on, replenishing the charge on flying capacitor 902, once again charging it to a voltage Vcc. The entire cycle then repeats itself.
Using either one of these methods or by using separate power supplies the bias supplies +Vdd and −Vcc may be generated to power the gate buffers in class-D audio amplifiers.
Class-D Output Integral Bootstrap SupplyIn an alternative embodiment of this invention the +Vdd and −Vcc bias supplies do not employ a dedicated DC/DC switching converter, but instead is generated from the switching action of the class-D power output stage itself. As shown in schematic 930 of
Half-Bridge Bias Generator:
As shown in circuit 930, a dual polarity power supply is generated from the switching action of one half-bridge, in this case MOSFETs 934 and 936. The common source output VB of this half-bridge is AC coupled using flying capacitors 938 and 939. To generate the positive Output +Vdd, capacitor 938 is connected to the power input Vcc through PMOS 942 and to output capacitor 946 through synchronous rectifier PMOS 942 with intrinsic P-N diode 944. To generate the negative output −Vcc, capacitor 939 is connected to ground through NMOS 941 and to output capacitor 947 through synchronous rectifier NMOS 943 with intrinsic P-N diode 945.
Operation is similar to dual-polarity boot-strap gate drive 400 except that the circuit produces two bias outputs, one negative and one positive, used to power multiple gate buffers. In
During this cycle, PMOS 940 is turned on, conducting current I2 and charging flying capacitor 938 to a voltage Vfly1=Vcc. At the same time, PMOS synchronous rectifier 943 is turned-on connecting pre-charged flying capacitor 939 to the −Vcc output and reservoir capacitor 947. Because capacitor 939 is pre-charged from a previous phase to a voltage Vfly2=Vcc, connecting its negative terminal to the −Vcc output causes current I3 to flow in PMOS 943 and in forward biased P-N diode 945. Accordingly flying capacitor 939 thereby transfers charge to reservoir capacitor 947 forcing the output negative so that (−Vcc)→(−Vcc).
Low-side P-channel follower 936, therefore carries the speaker current I1, charging current I2 for flying capacitor 938, and the charge transfer current I3 from flying capacitor 939, reservoir capacitor 947 and any load attached to the −Vcc bias output. P-channel power MOSFET 936 must be appropriately sized for low on-resistance. The on-resistances of MOSFETs 940 and 943 in the bias generator circuitry do not to be as low because they carry current used only to power gate buffers, not speakers.
In
During this cycle, NMOS 941 is turned on, conducting current I6 and charging flying capacitor 939 to a voltage Vfly2=Vcc. At the same time, synchronous rectifier 942 is turned-on connecting pre-charged flying capacitor 938 to the +Vdd output and reservoir capacitor 946. Because capacitor 938 is pre-charged from the previous phase to a voltage Vfly1=Vcc, connecting its positive terminal to the +Vdd output causes current I5 to flow in MOS 942 and in forward biased P-N diode 944. Accordingly flying capacitor 938 thereby transfers charge to reservoir capacitor 946 forcing the output above Vcc so that (+Vdd)→(+2Vcc).
High-side N-channel follower 934, therefore carries the speaker current I4, charging current I6 for flying capacitor 939, and the charge transfer current I5 from flying capacitor 938, reservoir capacitor 946 and any load attached to the +Vdd bias output. N-channel power MOSFET 934 must be appropriately sized for low on-resistance. The on-resistances of MOSFETs 939 and 942 in the bias generator circuitry do not to be as low because they carry current used only to power gate buffers, not speakers.
Full-Bridge Bias Generator:
Generating the +Vdd and −Vcc bias supplies from the switching action of a class-D audio amplifier can be achieved from any single half-bridge. Alternatively, the same technique can be used to derive power from a full bridge, i.e. from two half-bridges, as shown in
Specifically when VA is ground, PMOS 955A charges flying capacitor 953A, synchronous rectifier 956A is off and diode 957A is reverse biased. Meanwhile, while VB is at Vcc, PMOS 955B is off, diode 957B is forward biased and synchronous rectifier MOSFET 956B is conducting, transferring charge from flying capacitor 953B to reservoir capacitor 964 and driving (+Vdd)→2·Vcc.
Alternatively when VB is ground, PMOS 955B charges flying capacitor 953B, synchronous rectifier 956B is off and diode 957B is reverse biased. Meanwhile, while VA is at Vcc, PMOS 955A is off, diode 957A is forward biased and synchronous rectifier MOSFET 956A is conducting, transferring charge from flying capacitor 953A to reservoir capacitor 964 and also driving (+Vdd)→2·Vcc.
The net effect is that reservoir or “output” capacitor 964 of the +Vdd positive bias supply is being charged in every switching phase similar to that of a full-wave bridge rectifier in an AC-to-DC converter. Circuit 950 operates in a similar fashion to generate a −Vcc negative bias supply output from the switching action of the class-D amplifier where two-phase charging of −Vcc reservoir capacitor 965 is achieved with synchronous rectifiers 959A and 959B, alternatively transferring charge from flying capacitors 954A and 954B to reservoir capacitor 965 every phase.
Specifically when VA is at Vcc, NMOS 958A charges flying capacitor 955A, synchronous rectifier 959A is off and diode 960A is reverse biased. Meanwhile, while VB is at ground, NMOS 958B is off, diode 960B is forward biased and synchronous rectifier MOSFET 959B is conducting, transferring charge from flying capacitor 958B to reservoir capacitor 965 and driving (−Vcc)→−Vcc.
Alternatively when VB is at Vcc, NMOS 958B charges flying capacitor 9548, synchronous rectifier 959B is off and diode 960B is reverse biased. Meanwhile, while VA is at ground, NMOS 958A is off, diode 960A is forward biased and synchronous rectifier MOSFET 959A is conducting, transferring charge from flying capacitor 955A to reservoir capacitor 965 and also driving (−Vcc)→−Vcc.
The positive bias supply +Vdd in turn power gate buffers 962A and 962B while the negative bias supply −Vcc powers buffers 961A and 961B. These buffers in turn drive complementary follower half-bridge “A” comprising N-channel power MOSFET 951A and P-channel 952A and also drive half-bridge “B” comprising N-channel power MOSFET 951B and P-channel 952B.
Multi-Channel Class-D Audio ImplementationUsing the aforementioned methods, integrating the H-bridge complementary-follower with bias generator and speaker drivers for class-D audio applications can be achieved in three silicon die which may be packaged separately or assembled into a single plastic package.
Controller 1007 and power MOSFET dice 1008 share a common grounded die pad 1001A with leads 1001C, 1001D, 1001E, 1001F and optional tie bar 1001B. The H-shaped copper die-pad offers superior thermal and electrical performance. Die attach of P-channel DMOS array 1008 is performed with TiNiAg sandwiched back metal and conductive epoxy. On the top-side, vertical DMOS source regions are contacted using gold bond wires 1009A and connected to leads 1004, while chip-to-chip wire bonds 1012 are used to facilitate gate contact from controller 1007. The controller IC also includes individual bond wires to leads 1005, and down bond 1013 to facilitate top-side ground connection 1007.
A second Vcc-connected H-shaped die pad 1002A with leads 1002C, 1002D, 1002E, 1002F and optional tie bar 1002B is used support and contact N-channel high-side MOSFET array 1006 include source bonding wires 1009B to leads 1003, and die-to-die bonds 1010 for gate contact to controller 1007. Controller 1007 also includes down bond 1011 to Vcc-connected lead 1002F.
The entire triple-die assembly is housed in plastic mold compound 1020 and a 32 pin package. To electrically complete the amplifier, pins NS1 and PS1 must be connected on the printed circuit board to form output A. Similarly pins NS2 and PS2 form output B, NS3 and PS3 for output C, and NS4 and PS4 form output D.
An alternate package solution 1030 shown in
N-channel DMOS array 1034 is mounted using conductive epoxy die attach to lead frame 1032A with leads 1032C and 1032D with tie bar 1032B. Top-side contact to DMOS source regions is facilitated using bond wires 1039 and leads 1037. The entire assembly is housed in plastic mold compound 1045 in a 28-pin package. Like assembly 1000 pins NS1 and PS1 are connected on the printed circuit board to form output A, NS2 and PS2 to form output B, etc. To eliminate the necessity of this printed circuit board connection, a stitch bond as shown in top view 1050 and cross section 1055 of
As shown a first multi-channel vertical DMOS die 1033 mounted on die pad 1031A and a second multi-channel vertical DMOS die 1034 mounted on a second die pad 1032A are connected to leads 1036 and 1037 by a stitch bond comprising segments 1051A, 1051B and 1051C and optionally by a second stitch bond comprising segments 1052A, 1052B and 1052C. The example illustrates the connection of NS2 and PS2 to form output B. A similar approach can be employed for other outputs. Plastic mold compound 1045 secures the entire assembly.
Referring again to plan view 1000 of
The gate metal contacts gate polysilicon 1078B through barrier metal 1080. Gate polysilicon 1078B, insulated from epitaxy 1071 by gate oxide 1077 lining trench 1073B also connects to active area trench polysilicon 1078A in trench 1073A. Provided dielectric 1079 is sufficiently thick, the breakdown of the vertical trench power MOSFET will not be adversely affected.
As a complete multi-channel audio system,
Claims
1. (canceled)
2. A stereo class-D audio amplifier comprising:
- a first conductive die pad having at least one supply contact to connect to a supply voltage;
- a second conductive die pad having at least one ground contact to connect to a ground reference voltage; and
- a plurality of half-bridge circuits, each respective half bridge circuit of the plurality of half-bridge circuits including a high-side vertical N-channel MOSFET formed on a first die and a low-side vertical P-channel MOSFET formed on a second die, an interconnection of the low-side vertical P-channel MOSFET and the high-side vertical N-channel MOSFET forming an output of the respective half-bridge circuit, a drain of the high-side vertical N-channel MOSFET of each of the plurality of half-bridge circuits being electrically connected to the first conductive die pad, and a drain of the low-side vertical P-channel MOSFET of each of the plurality of half-bridge circuits being electrically connected to the second conductive die pad.
3. The stereo class-D audio amplifier of claim 2 wherein the high-side vertical N-channel MOSFET and the low-side vertical P-channel MOSFET of each of the plurality of half-bridge circuits is a DMOS MOSFET.
4. The stereo class-D audio amplifier of claim 3 wherein the plurality of half-bridge circuits includes at least 4 half-bridge circuits.
5. The stereo class-D audio amplifier of claim 4 wherein the stereo class-D audio amplifier is packaged in a single integrated circuit.
6. The stereo class-D audio amplifier of claim 2 wherein each respective high-side vertical N-channel MOSFET and the corresponding low-side vertical P-channel MOSFET forms a complementary follower.
7. The stereo class-D audio amplifier of claim 6 further comprising a plurality of break-before-make buffers corresponding to each of the plurality of high-side vertical N-channel MOSFETs.
8. The stereo class-D amplifier of claim 7 wherein each respective break-before-make buffer is connected to a respective one of the plurality of high-side vertical N-channel MOSFETs and the corresponding low-side vertical P-channel MOSFETs.
9. The stereo class-D audio amplifier of claim 2 wherein the first conductive die pad and the second conductive die pad have an H-shape.
10. A stereo class-D audio amplifier comprising:
- a plurality of high-side vertical power MOSFETs;
- a corresponding plurality of low-side vertical power MOSFETs corresponding to each high-side vertical power MOSFET of the plurality of high-side vertical power MOSFETs; and
- an interconnection between each respective high-side vertical power MOSFET and the corresponding low-side vertical power MOSFET forming a respective half-bridge output of the stereo class-D audio amplifier, each of the plurality of high-side vertical power MOSFETs being formed on a first die and each of the corresponding plurality of low-side vertical power MOSFETs being formed on a second die, a drain of each of the high-side vertical power MOSFETs being electrically connected by a backside of the first die to a first single die pad, and a drain of each of the low-side vertical power MOSFETs being electrically connected by a backside of the second die to a second single die pad.
11. The stereo class-D audio amplifier of claim 10 wherein each respective high-side vertical power MOSFET and the corresponding low-side vertical power MOSFET forms a complementary follower.
12. The stereo class-D audio amplifier of claim 11 wherein each low-side vertical power MOSFET of the corresponding plurality of low-side vertical power MOSFETs is a P-channel MOSFET.
13. The stereo class-D audio amplifier of claim 11 wherein each high-side vertical power MOSFET of the plurality of high-side vertical power MOSFETs is an N-channel MOSFET.
14. The stereo class-D audio amplifier of claim 10 wherein the plurality of high-side vertical power MOSFETs includes at least 4 MOSFETs and the corresponding plurality of low-side vertical power MOSFETs includes at least 4 MOSFETs.
15. The stereo class-D audio amplifier of claim 14 wherein each low-side vertical power MOSFET of the corresponding plurality of low-side vertical power MOSFETs is a P-channel MOSFET and each high-side vertical power MOSFET of the plurality of high-side vertical power MOSFETs is an N-channel MOSFET.
16. The stereo class-D audio amplifier of claim 10 wherein the stereo class-D audio amplifier is packaged in a single integrated circuit.
17. The stereo class-D amplifier of claim 10 wherein the first single die pad is electrically connected to at least one power supply contact.
18. The stereo class-D audio amplifier of claim 17 wherein the second single die pad is electrically connected to at least one ground contact.
19. The stereo class-D audio amplifier of claim 10 wherein the first single die pad and the second single die pad have an H-shape.
20. The stereo class-D audio amplifier of claim 10 wherein each of the plurality of high-side vertical power MOSFETs and each of the corresponding plurality of low-side vertical power MOSFETs is a DMOS MOSFET.
21. The stereo class-D audio amplifier of claim 10 further comprising a plurality of break-before-make buffers corresponding to each of the plurality of high-side vertical power MOSFETs, each respective break-before-make buffer being connected to a respective one of the plurality of high-side vertical power MOSFETs and the corresponding low-side vertical power MOSFET.
Type: Application
Filed: Jan 20, 2016
Publication Date: May 19, 2016
Inventor: Richard K. Williams (Cupertino, CA)
Application Number: 15/001,966
