NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT AND SYSTEM THEREOF
A negative reference voltage generating circuit generating a negative reference voltage is provided, including a differential amplifier, a first diode, second diodes, and a third resistor. The differential amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal, and is driven by a positive and a negative power voltages. The output terminal is connected with the non-inverting input terminal via a first resistor and connected with the inverting input terminal via a second resistor. The first diode includes a cathode connected with the non-inverting input terminal of the differential amplifier and an anode connected with a ground. The second diodes respectively include a cathode connected with a predetermined connection point and an anode connected with the ground, and are connected in parallel. The third resistor is connected between the connection point and the inverting input terminal of the differential amplifier.
This application claims the priority benefit of Japan application serial no. 2015-004352, filed on Jan. 13, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to a negative reference voltage generating circuit that is, for example, used in a NOR type flash memory and generates a negative reference voltage, and a negative reference voltage generating system using the negative reference voltage generating circuit.
2. Description of Related Art
For example, a NOR type flash memory requires high speed performance during random access, and as shown in
In order to generate the positive voltage, generally a bandgap reference (BGR) voltage generating circuit is used, for example, in the peripheral circuit of a NAND type flash memory.
PRIOR ART LITERATUREPatent Literature 1: Specification of US Patent Publication No. 2012/0218032
Patent Literature 2: Japanese Patent Publication No. 2009-016929
Patent Literature 3: Japanese Patent Publication No. 2009-074973
Patent Literature 4: Specification of US Patent Publication No. 2008/0018318
For generating a negative voltage, however, instead of using the BGR voltage generating circuit that generates a negative voltage, generally the BGR voltage generating circuit of the positive voltage, as shown in
Vneg=−R22/R21×Vpp+(1+R22/R21)×PVref (1)
Vneg=−Iref×R32+PVref (2)
Iref=PVref/R31 (3)
However, it is considered that, if the negative reference voltage NVref can be used, the negative voltage Vneg can be generated more accurately and the circuit structure can be simplified. In order to generate the negative voltage Vneg equal to −10V (Vneg=−10V), if the negative reference voltage NVref is equal to −1.0V±0.1V (NVref=−1.0V±0.1V), the negative voltage Vneg is controlled to be −10V±1V by a ten times error. Thus, the negative voltage generating circuit requires the same accuracy as the BGR voltage generating circuit, that is ±0.01V.
Vneg=(R42/R41+1)×NVref (4)
The issue is to realize a circuit that accurately generates the negative reference voltage NVref.
NVref=−Iref×R52 (5)
NVref=−PVref×R62/R61 (6)
In the control circuit of the aforementioned conventional examples, the following problem exists. That is, the negative reference voltage is obtained from the positive reference voltage PVref, and thus in addition to the accuracy of the positive reference voltage PVref, some errors are added. The control circuits of the conventional examples are divided into the following two types.
(Type 1 (
(Type 2 (
(1) a differential amplifier 1, i.e., an operational amplifier;
(2) a feedback resistor Rc connected between an output terminal and a non-inverting input terminal of the differential amplifier 1;
(3) a feedback resistor Rc connected between the output terminal and an inverting input terminal of the differential amplifier 1;
(4) a diode Dc having an anode connected with the non-inverting input terminal of the differential amplifier 1 and a cathode connected with a ground; and
(5) m diodes D1-Dm, each having an anode connected with the inverting input terminal of the differential amplifier 1 via a resistor Rb and a cathode connected with the ground, and the diodes D1-Dm are connected in parallel.
The BGR type positive reference voltage generating circuit of Comparative Example 1 configured in the aforementioned manner generates a positive reference voltage Vbgr from the output terminal of the differential amplifier 1 and outputs the same.
(1) a PNP type transistor Qc connected as a diode is provided in place of the diode Dc.
(2) m PNP type transistors Q1-Qm are provided in place of the parallel circuit of the diodes D1-Dm. The m PNP type transistors Q1-Qm are connected in parallel and diode-connected independently.
In
The same as Comparative Example 1, the BGR type positive reference voltage generating circuit of Comparative Example 2 configured in the aforementioned manner generates the positive reference voltage Vbgr from the output terminal of the differential amplifier 1 and outputs the same.
Nevertheless, the BGR type positive reference voltage generating circuits of Comparative Examples 1 and 2 have the problem of being unable to generating the negative reference voltage.
SUMMARY OF THE INVENTIONIn view of the above, the invention provides a negative reference voltage generating circuit and a negative reference voltage generating system which generate a negative reference voltage with high accuracy and have a simple circuit structure, compared with the conventional technology.
A negative reference voltage generating circuit of the invention generates a negative reference voltage with a bandgap reference, and the negative reference voltage generating circuit includes:
a differential amplifier including a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the differential amplifier is driven by a positive power voltage and a negative power voltage, and the output terminal is connected with the non-inverting input terminal via a first resistor and is connected with the inverting input terminal via a second resistor;
a first diode including a cathode and an anode, wherein the cathode is connected with the non-inverting input terminal of the differential amplifier and the anode is connected with a ground;
a plurality of second diodes each including a cathode and an anode, wherein the cathode is connected with a predetermined connection point and the anode is connected with the ground, and the second diodes are connected in parallel; and
a third resistor connected between the predetermined connection point and the inverting input terminal of the differential amplifier.
Regarding the negative reference voltage generating circuit, the first diode and the second diodes are formed by implanting a P type dopant into a semiconductor substrate to form a P well, forming an N+ doped region in a central portion of the P well to form the cathode, and forming a P+ doped region at a position around the cathode to form the anode.
Here, a substrate tap is formed by forming the P+ doped region in the semiconductor substrate located outside the first diode and the second diodes.
Regarding the negative reference voltage generating circuit, the first diode and the second diodes are formed by implanting an N type dopant into a semiconductor substrate to form an N well, implanting a P type dopant into the N well to form a P well, forming an N+ doped region in a central portion of the P well to form the cathode, and forming a P+ doped region at a position around the cathode to form the anode.
Here, a first substrate tap is formed by forming the N+ doped region in the N well and a second substrate tap is formed by forming the P+ doped region in the semiconductor substrate.
In the negative reference voltage generating circuit, each of the first diode and the second diodes are a diode between a base and an emitter of an NPN type transistor having a triple well structure.
Here, the first diode and the second diodes are formed by implanting the N type dopant into the semiconductor substrate to form the N well, implanting the P type dopant into the N well to form the P well, forming the N+ doped region in the central portion of the P well to form the emitter, and forming the P+ doped region at a position around the emitter to form the base; and further the NPN type transistor is formed by forming the N+ doped region at a position around the base to form the collector.
Moreover, the first substrate tap is formed by forming the N+ doped region in the N well and the second substrate tap is formed by forming the P+ doped region in the semiconductor substrate.
In the negative reference voltage generating circuit, a positive power terminal of the differential amplifier is applied with a predetermined positive power voltage Vdd or a ground voltage. A negative power terminal of the differential amplifier is applied with a predetermined negative power voltage Vnn.
Regarding the negative reference voltage generating circuit, the differential amplifier includes a plurality of NMOS transistors having a triple well structure, and the triple well structure is formed by forming a P well in an N well formed in a P type semiconductor substrate and forming a plurality of electrode doped regions in the P well.
Here, the N well is applied with the predetermined positive power voltage Vdd or the ground voltage.
A negative reference voltage generating system of the invention includes: the negative reference voltage generating circuit; and
a negative voltage generating circuit including a charge pump, generating a predetermined negative power voltage, and supplying the predetermined negative power voltage as a negative power voltage to the negative reference voltage generating circuit.
The negative reference voltage generating system further includes: a control circuit controlling the negative power voltage outputted from the negative voltage generating circuit by using a predetermined reference voltage, so as to reduce a variation of the negative power voltage.
The negative reference voltage generating system further includes: a control circuit controlling the negative power voltage by using a negative reference voltage that is outputted from the negative reference voltage generating circuit, as a reference voltage, to reduce a variation of the negative power voltage based on the negative power voltage outputted from the negative voltage generating circuit.
Thus, the negative reference voltage generating circuit and the negative reference voltage generating system of the invention are capable of generating a negative reference voltage with high accuracy and have a simple circuit structure, compared with the conventional technology.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Embodiments of the invention are described hereinafter with reference to the figures. In the following embodiments, identical components/elements are assigned with the same reference numerals.
(1) a differential amplifier 1, i.e. an operational amplifier, to which a positive power voltage Vdd and a negative power voltage Vnn are respectively supplied via a positive power terminal and a negative power terminal;
(2) a feedback resistor Rc connected between an output terminal and a non-inverting input terminal of the differential amplifier 1;
(3) a feedback resistor Rc connected between the output terminal and an inverting input terminal of the differential amplifier 1;
(4) a diode Dc having a cathode connected with the non-inverting input terminal of the differential amplifier 1 and an anode connected with a ground; and
(5) in diodes D1-Dm each having a cathode connected with the inverting input terminal of the differential amplifier 1 via a resistor Rb and an anode connected with the ground, wherein the diodes D1-Dm are connected in parallel.
Here, the resistors Rc, Rc, and Rb are composed of polysilicon resistors, for example.
The BGR type negative reference voltage generating circuit of Embodiment 1 configured in the aforementioned manner generates a negative reference voltage NVbgr from the output terminal of the differential amplifier 1 and outputs the same. The BGR type negative reference voltage generating circuit is formed based on the general BGR type positive reference voltage generating circuit of
In addition, an N+ dopant is implanted into a P well 12 of
In the BGR type negative reference voltage generating circuit of
NVbgr=If×(Rc+Rb)+Vd (7)
Here, the diode current If and the cathode voltage Vd are represented by the following equations.
If=kT/q×(1/Rb)×Ln(m)
Vd=kT/q×Ln(If/Is/m)
Here, k represents a Boltzmann constant, T represents an absolute temperature, q represents an elementary charge, and Is represents a reverse saturation current of the diode.
Temperature dependence can be removed if the following equation is satisfied.
As described above, according to Embodiment 1, the negative reference voltage generating circuit is provided, which generates the negative reference voltage with high accuracy and has simple circuit structure as compared with the conventional technology.
Embodiment 2(1) a NPN type transistor Qc with diode connection is provided in place of the diode Dc.
(2) m NPN type transistors Q1-Qm respectively with diode connection are provided in place of the diodes D1-Dm.
In the BGR type negative reference voltage generating circuit configured in the aforementioned manner, as clearly shown in
As described above, according to Embodiment 2, the negative reference voltage generating circuit is provided, which operates the same as Embodiment 1, and generates the negative reference voltage with high accuracy and has a simple circuit structure as compared with the conventional technology.
Embodiment 3The differential amplifier 1 used in Embodiment 1 and Embodiment 2 needs to be operated by the negative power voltage Vnn. The initial negative power voltage Vnn and the BGR output voltage are at a ground level (Vss level). At the moment, the negative power voltage Vim is supplied by the charge pump, for example. Thus, it is important to prevent phenomena, such as latch-up effect, resulting from noise that occurs when the operation starts.
(1) Vdf=the positive power voltage Vdd, or
the positive reference voltage PVref generated by the positive reference voltage generating circuit of
(2) Vref=the positive reference voltage PVref generated by the positive reference voltage generating circuit of
Moreover, the power voltage of the differential amplifier 74 uses the positive power voltage Vdd and the ground voltage Vss.
In
(1) The negative reference voltage Vbgr outputted from the BGR type negative reference voltage generating circuit 72 is used in place of the reference voltage Vref applied to the inverting input terminal of the differential amplifier 74.
(2) The voltage Vdd/Vss, the voltage Vss/Vnn or the voltage Vdd/Vnn can be used as the power voltage Vp/Vn of the differential amplifier 74.
With the aforementioned configuration, the negative reference voltage Vbgr is used as the reference voltage of the differential amplifier 74, and the differential amplifier 74 performs feedback control on the negative voltage generating circuit 71, thereby suppressing variation of the negative power voltage Vnn.
As described above, the negative reference voltage generating circuit according to the embodiment and the negative reference voltage generating system using the negative reference voltage generating circuit achieve the following specific effects: being capable of generating the negative reference voltage with extremely high accuracy and high precision relative to the temperature change and having a simple circuit structure, compared with the conventional technology.
As specified above, the negative reference voltage generating circuits and the negative reference voltage generating systems of the invention are capable of generating the negative reference voltage with high accuracy and have a simple circuit structure, compared with the conventional technology. The negative reference voltage generating circuits and the negative reference voltage generating systems of the invention are applicable to a non-volatile memory device such as a NOR type flash memory, or a dynamic random access memory (DRAM), etc.
Claims
1. A negative reference voltage generating circuit generating a negative reference voltage with a bandgap reference, the negative reference voltage generating circuit comprising:
- a differential amplifier comprising a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the differential amplifier is driven by a positive power voltage and a negative power voltage, and the output terminal is connected with the non-inverting input terminal via a first resistor and is connected with the inverting input terminal via a second resistor;
- a first diode comprising a cathode and an anode, wherein the cathode is connected with the non-inverting input terminal of the differential amplifier and the anode is connected with a ground;
- a plurality of second diodes each comprising a cathode and an anode, wherein the cathode is connected with a predetermined connection point and the anode is connected with the ground, and the second diodes are connected in parallel; and
- a third resistor connected between the predetermined connection point and the inverting input terminal of the differential amplifier.
2. The negative reference voltage generating circuit according to claim 1, wherein:
- the first diode and the second diodes are formed by implanting a P type dopant into a semiconductor substrate to form a P well, forming an N+ doped region in a central portion of the P well to form the cathode, and forming a P+ doped region at a position around the cathode to form the anode.
3. The negative reference voltage generating circuit according to claim 2, wherein:
- a substrate tap is formed by forming the P+ doped region in the semiconductor substrate located outside the first diode and the second diodes.
4. The negative reference voltage generating circuit according to claim 1, wherein:
- the first diode and the second diodes are formed by implanting an N type dopant into a semiconductor substrate to form an N well, implanting a P type dopant into the N well to form a P well, forming an N+ doped region in a central portion of the P well to form the cathode, and forming a P+ doped region at a position around the cathode to form the anode.
5. The negative reference voltage generating circuit according to claim 4, wherein:
- a first substrate tap is formed by forming the N+ doped region in the N well and a second substrate tap is formed by forming the P+ doped region in the semiconductor substrate.
6. The negative reference voltage generating circuit according to claim 1, wherein:
- each the first diode and the second diodes is a diode between a base and an emitter of an NPN type transistor having a triple well structure.
7. The negative reference voltage generating circuit according to claim 6, wherein:
- the first diode and the second diodes are formed by implanting an N type dopant into the semiconductor substrate to form an N well, implanting a P type dopant into the N well to form a P well, forming an N+ doped region in the central portion of the P well to form the emitter, and forming a P+ doped region at a position around the emitter to form the base; and further the NPN type transistor is formed by forming the N+ doped region at a position around the base to form the collector.
8. The negative reference voltage generating circuit according to claim 7, wherein:
- a first substrate tap is formed by forming the N+ doped region in the N well and a second substrate tap is formed by forming the P+ doped region in the semiconductor substrate.
9. The negative reference voltage generating circuit according to claim 1, wherein:
- a positive power terminal of the differential amplifier is applied with a predetermined positive power voltage or a ground voltage; and
- a negative power terminal of the differential amplifier is applied with a predetermined negative power voltage.
10. The negative reference voltage generating circuit according to claim 1, wherein:
- the differential amplifier comprises a plurality of NMOS transistors having a triple well structure, and the triple well structure is formed by forming a P well in an N well formed in a P type semiconductor substrate and forming a plurality of electrode doped regions in the P well.
11. The negative reference voltage generating circuit according to claim 10, wherein:
- the N well is applied with the predetermined positive power voltage or the ground voltage.
12. A negative reference voltage generating system, comprising:
- the negative reference voltage generating circuit of claim 1; and
- a negative voltage generating circuit comprising a charge pump, generating a predetermined negative power voltage, and supplying the predetermined negative power voltage as a negative power voltage to the negative reference voltage generating circuit.
13. The negative reference voltage generating system according to claim 12, further comprising:
- a control circuit controlling the negative power voltage outputted from the negative voltage generating circuit by using a predetermined reference voltage, so as to reduce a variation of the negative power voltage.
14. The negative reference voltage generating system according to claim 12, further comprising:
- a control circuit controlling the negative power voltage by using a negative reference voltage that is outputted from the negative reference voltage generating circuit, as a reference voltage, based on the negative power voltage outputted from the negative voltage generating circuit, so as to reduce a variation of the negative power voltage.
Type: Application
Filed: May 21, 2015
Publication Date: Jul 14, 2016
Inventors: Hideki Arakawa (Tokyo), Nobuhiko Ito (Tokyo), Teruaki Maeda (Tokyo)
Application Number: 14/718,100