MEMORY DEVICE AND OPERATING METHOD OF SAME
A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
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1. Field of the Disclosure
The present disclosure relates to a memory device and operation method of the same and, more particularly, to a memory device having extra arrays of reconfigurable size.
2. Background
Memory devices are used in a variety of electronic applications. A memory device may include a plurality of pages for storing user data, and the size of the pages is fixed and unchangeable. However, in some applications, it is desirable to store extra data in the memory device.
SUMMARYAccording to an embodiment of the disclosure, a memory device includes a memory array including a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The memory device also includes a logic unit communicatively coupled to the memory array and configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
According to another embodiment of the disclosure, a memory device includes a memory array including a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The memory device also includes a logic unit communicatively coupled to the memory array, and configured to receive a program instruction including an address of a selected page and data to be programmed, and perform a program operation in a first access mode or in a second access mode. In the first access mode, the logic unit programs the received data in the selected page. In the second access mode, the logic unit programs the received data in the selected page and the extra array corresponding to the selected page.
According to a further embodiment of the disclosure, a method of operating a memory device is provided. The memory device includes a plurality of array blocks for storing array data and a plurality of extra array blocks respectively corresponding to the plurality of array blocks for storing extra data. The method includes receiving a read instruction including a read command code, and determining whether the read command code is a first read command code or a second read command code. If the read command code is determined to be the first read command code, the method includes sequentially reading out the array data stored in the plurality of pages. If the read command code is determined to be the second read command code, the method includes sequentially reading out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate disclosed embodiments and, together with the description, serve to explain the disclosed embodiments.
Reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
In some embodiments, internal register 124 of logic unit 120 stores a plurality of command codes and their corresponding operations. When logic unit 120 receives an instruction from the external circuit via I/O interface 110, processing circuitry 122 of logic unit 120 parses the instruction to identify a command code, compares the identified command code with the plurality of command codes stored in internal register 124 to look for an operation corresponding to the identified command code, and then performs the operation.
The array structure illustrated in
In order to implement a read operation in the first access mode or the second access mode in memory device 100, several interface protocol methods can be used, according to different embodiments of the present disclosure. In some embodiments, logic unit 120 of memory device 100 can receive a read instruction that includes access information related to whether to perform a memory access operation in the first access mode or the second access mode. When logic unit 120 performs a read operation in the first access mode, logic unit 120 sequentially reads out the array data stored in pages 220 in the order of page 0, page 1, page 2, . . . , page n. The extra data stored in extra arrays 230 are excluded from the read out sequence. That is, the extra data stored in extra arrays 230 are not read out. When logic unit 120 performs a read operation in the second access mode, logic unit 120 sequentially reads out both the array data stored in pages 220 and the extra data stored in extra arrays in the order of page 0, extra array 0, page 1, extra array 1, page 2, extra array 2, . . . , page n, extra array n.
In some embodiments, logic unit 120 can store, in non-volatile memory 140, access information related to whether to perform a memory access operation in the first access mode or in the second access mode, and the size of each extra array 230.
Referring to
In some embodiments, in order to implement a program operation in the first access mode or the second access mode, logic unit 120 of memory device 100 can receive a program instruction that include access information related to whether to perform a program operation in the first access mode or the second access mode.
In some embodiments, logic unit 120 can perform a program operation according to the access information stored in non-volatile memory 140 and loaded in internal register 124.
Referring to
In some embodiments, in order to implement an erase operation in memory device 100 including array blocks 200 and extra array blocks 210, logic unit 120 of memory device 100 can receive an erase instruction that includes information related to whether to erase a selected array block 200, or to erase a selected extra array block 210, or to erase both a selected array block 200 and a corresponding extra array block 210.
As illustrated in
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims
1. A memory device, comprising:
- a memory array including a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data;
- a non-volatile memory storing access information that specifies whether to perform a memory access operation in a first access mode or a second access mode; and
- a logic unit coupled to the memory array and the non-volatile memory,
- wherein in the first access mode, the logic unit accesses the array data stored in the plurality of pages, and
- in the second access mode, the logic unit accesses the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
2. The memory device of claim 1, wherein the logic unit is configured to:
- receive a read instruction, and
- perform a read operation in the first access mode or in the second access mode; and
- wherein the read instruction specifies whether to perform the read operation in the first access mode or the second access mode.
3. The memory device of claim 2, wherein the read instruction includes a read command code and a starting address for the read operation, and
- the read command code is one of a first read command code that specifies the first access mode, and a second read command code that specifies the second access mode and a size of each one of the plurality of extra arrays.
4. The memory device of claim 3, wherein the logic unit is configured to:
- determine whether the read command code included in the read instruction is the first read command code or the second read command code;
- if the read command code is determined to be the first read command code, perform the read operation in the first access mode; and
- if the read command code is determined to be the second read command code, perform the read operation in the second access mode.
5. The memory device of claim 1, wherein the logic unit includes an internal register, and
- the logic unit is configured to: load the access information from the non-volatile memory to the internal register; and set a default access mode according to the access information in the internal register.
6. The memory device of claim 5, wherein the logic unit is configured to:
- perform a read operation in the default access mode.
7. The memory device of claim 5, wherein the logic unit is configured to:
- receive an instruction to modify the access information in the internal register;
- modify the access information in the internal register according to the received instruction; and
- set the default access mode according to the modified access information.
8. The memory device of claim 5, wherein the logic unit is configured to:
- receive a program instruction including an address of a selected page and data to be programmed; and
- perform a program operation in the default access mode.
9. The memory device of claim 1, where in the logic unit is configured to:
- receive a program instruction including an address of a selected page and data to be programmed;
- perform a program operation in the first access mode or in the second access mode,
- wherein in the first access mode, the logic unit programs the received data in the selected page, and
- in the second access mode, the logic unit programs the received data in the selected page and the extra array corresponding to the selected page.
10. The memory device of claim 9, wherein the program instruction includes a program command code, and
- the program command code is one of a first program command code that specifies the first access mode, and a second program command code that specifies the second access mode and the size of each one of the plurality of extra arrays.
11. The memory device of claim 10, wherein the logic unit is configured to:
- determine whether the program command code included in the program instruction is the first program command code or the second program command code;
- if the program command code is determined to be the first program command code, perform the program operation in the first access mode; and
- if the program command code is determined to be the second program command code, perform the program operation in the second access mode.
12. The memory device of claim 1, wherein the logic unit is configured to:
- receive an erase instruction including an address;
- determine whether the erase instruction specifies erasing an array block having the address, or erasing an extra array block having the address, or erasing an array block and a corresponding extra array having the address; and
- perform an erase operation based on the determination.
13. A memory device, comprising:
- a memory array including a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data;
- a non-volatile memory storing access information that specifies whether to perform a memory access operation in a first access mode or a second access mode; and
- a logic unit coupled to the memory array and the non-volatile memory,
- wherein in the first access mode, the logic unit accesses a selected page, and
- in the second access mode, the logic unit accesses the selected page and one of the extra arrays corresponding to the selected page.
14. The memory device of claim 13, wherein the logic unit is configured to:
- receive a program instruction, and
- perform a program operation in the first access mode or in the second access mode; and
- wherein the program instruction specifies whether to perform the program operation in the first access mode or the second access mode.
15. The memory device of claim 14, wherein the program instruction includes a program command code, and
- the program command code is one of a first program command code that specifies the first access mode, and a second program command code that specifies the second access mode and the size of each one of the plurality of extra arrays.
16. The memory device of claim 15, wherein the logic unit is configured to:
- determine whether the program command code included in the program instruction is the first program command code or the second program command code;
- if the program command code is determined to be the first program command code, perform the program operation in the first access mode; and
- if the program command code is determined to be the second program command code, perform the program operation in the second access mode.
17. (canceled)
18. The memory device of claim 13, wherein the logic unit includes an internal register, and
- the logic unit is configured to: load the access information from the non-volatile memory to the internal register; set a default access mode according to the access information in the internal register; and perform the program operation according to the default access mode.
19. The memory device of claim 18, wherein the logic unit is configured to:
- receive an instruction to modify the access information in the internal register;
- modify the access information in the internal register according to the received instruction; and
- set the default access mode according to the modified access information.
20. A method of operating a memory device,
- the memory device including: a memory array including a plurality of array blocks for storing array data and a plurality of extra array blocks respectively corresponding to the plurality of array blocks for storing extra data a non-volatile memory storing access information that specifies whether to perform a memory access operation in a first access mode or a second access mode; and a logic unit coupled to the memory array and the non-volatile memory,
- the method comprising: determining, by the logic unit, whether to access the memory array in the first access mode or the second access mode based on the access information stored in the non-volatile memory; if the access information stored in the non-volatile memo specifies the first access mode, accessing, by the logic unit, the array data stored in the plurality of pages; and
- if the access info a ion stored in he non-volatile memory specifies the second access mode, accessing, by the logic unit, the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
Type: Application
Filed: Feb 11, 2015
Publication Date: Aug 11, 2016
Applicant:
Inventors: Kuen-Long CHANG (Taipei City), Ken-Hui CHEN (Hsinchu City), Ming-Chih HSIEH (Taipei City)
Application Number: 14/619,810