Patents by Inventor Kuen-Long Chang

Kuen-Long Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210051020
    Abstract: A memory device can comprise a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received a command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung CHEN, Chin-Hung CHANG, Kuen-Long CHANG
  • Patent number: 10891184
    Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 12, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui Chen, Kuen-Long Chang, Yi-Fan Chang
  • Patent number: 10884956
    Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 5, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Patent number: 10855477
    Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 1, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Shih-Chang Huang
  • Publication number: 20200371861
    Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui CHEN, Kuen-Long CHANG, Yi-Fan CHANG
  • Patent number: 10809925
    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui Chen, Kuen-Long Chang, Chin-Hung Chang, Yu-Chen Wang
  • Patent number: 10770119
    Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 8, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang, Ming-Chih Hsieh
  • Patent number: 10749695
    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: August 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Shih-Chang Huang
  • Publication number: 20200242273
    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 30, 2020
    Inventors: Kuen-Long CHANG, Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20200241768
    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui CHEN, Kuen-Long CHANG, Chin-Hung CHANG, Yu-Chen WANG
  • Patent number: 10715340
    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 14, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Shih-Chang Huang
  • Publication number: 20200186339
    Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung HUNG, Kuen-Long CHANG, Ken-Hui CHEN, Shih-Chang HUANG, Chin-Hung CHANG, Chen-Chia FAN
  • Publication number: 20200185010
    Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.
    Type: Application
    Filed: August 7, 2019
    Publication date: June 11, 2020
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang, Ming-Chih Hsieh
  • Patent number: 10680809
    Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 9, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Patent number: 10658046
    Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 19, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Su-Chueh Lo, Chun-Yu Liao
  • Patent number: 10620879
    Abstract: A memory device includes a memory including first and second pages in first and second banks, respectively, an address decoder mapping command addresses to physical addresses. The memory device further includes circuitry configured to maintain a status indicating a most recently written page, decode received command sequences including command addresses and implementing an operation including (i) responsive to receiving a command sequence including a read command address that is pre-configured for reading data, causing the address decoder to map the read command address to one of the first and second pages selected according to the status, and (ii) responsive to receiving a second command sequence including a write command address that is pre-configured for writing data, causing the address decoder to map the write command address to one of the first and second pages selected according to the status.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 14, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Su-Chueh Lo, Shang-Chi Yang
  • Patent number: 10566062
    Abstract: A memory device is disclosed in the present invention, comprising a memory array, a logic circuit, a sense amplifier circuit and a read buffer. The logic circuit is configured to perform a read operation in response to a read command and a start address. During the read operation, the logic circuit finds a target data in the memory array. The sense amplifier circuit is configured to read the target data from the memory array during the read operation. The read buffer is configured to temporarily stores and outputs the target data during the read operation. When an interruption event occurs during the read operation, the read buffer preserves a buffer content of the read buffer, and the logic circuit records a read status.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Shang-Chi Yang
  • Publication number: 20200036539
    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung HUNG, Kuen-Long CHANG, Ken-Hui CHEN, Shih-Chang HUANG
  • Publication number: 20190347159
    Abstract: A memory device includes an error code generator, one or more first pins coupled to an external data bus, and one or more second pins coupled to an external system interface. The one or more first pins output data chunks to the data bus during a period of memory operation; and the error code generator is configured to transmit a status code via the one or more second pins during the period of memory operation. The status code indicates at least one of an error was detected, an error was detected and corrected, or an error was detected and not corrected.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Inventors: Kuen Long CHANG, Ken Hui CHEN, Su Chueh LO, Chia-Feng CHENG
  • Patent number: RE47803
    Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 7, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Chia-He Liu