SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including In. The upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
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This application is a divisional of application Ser. No. 14/445,135, filed Jul. 29, 2014, which is based upon and claims the benefit of priority of the prior Japanese Priority Application No. 2013-167851 filed on Aug. 12, 2013, the entire contents of which are hereby incorporated by reference.
FIELDThe disclosures herein generally relate to a semiconductor device and a manufacturing method thereof.
BACKGROUNDNitride semiconductors such as GaN, AlN, and InN, or mixed crystals of these materials have wide band gaps, and are used as high-output electronic devices, short-wavelength light-emitting devices, and the like. To be used as high-output devices, technologies relating to field-effect transistors (FET), especially, high electron mobility transistors (HEMT) have been developed. A HEMT that uses such a nitride semiconductor is used for a high-output, high-efficiency amplifier, a high-power switching device or the like because it can operate with great current, high voltage, and low on-resistance.
Among such nitride semiconductors, a HEMT having an InAlN/GaN structure that uses InAlN as an electron supply layer has great spontaneous polarization of InAlN, and can generate greater 2DEG than a HEMT having an AlGaN/GaN structure. Therefore, the HEMT having an InAlN/GaN structure can have the on-resistance lower than the HEMT having an AlGaN/GaN structure, with which characteristics of the semiconductor device can be improved.
RELATED-ART DOCUMENTS Patent Documents
- [Patent Document 1] Japanese Laid-open Patent Publication No. 2002-359256
- [Patent Document 2] Japanese Patent No. 3740744
However, when InAlN is used in a semiconductor device, In (Indium) tends to be eliminated if a process such as heating is performed at a high temperature during a manufacturing process. If such elimination of In occurs in a semiconductor device using InAlN, it lowers characteristics of the semiconductor device, and it is not preferable.
Therefore, a semiconductor device and its manufacturing method have been desired for the semiconductor device using InAlN that can be manufactured without lowering the characteristics.
SUMMARYAccording to at least an embodiment of the present invention, a semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including In. The upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.
In the following, embodiments of the present invention will be described with reference to the drawings. Note that the same numerical codes are assigned to the same members, and repetition of their description may be omitted.
First EmbodimentFirst, a HEMT will be described that has a structure using InAlN in its electron supply layer.
In the HEMT having this structure, InAlN has a wide band gap, which makes the contact resistance become great if the source electrode 942 and the drain electrode 943 are directly formed on InAlN, and it is not preferable. Therefore, there is a method to form n-type regions 920a by ion implantation of an impurity element such as Si in the electron supply layer 922 and the electron transit layer 921 in regions where the source electrode 942 and the drain electrode 943 are formed. This makes it possible to lower the contact resistance between the electron supply layer 922 made of InAlN, and the source electrode 942 and the drain electrode 943, in regions where the n-type regions 920a are formed.
Next, a manufacturing method will be described for the HEMT that has the structure illustrated in
First, as illustrated in
Next, as illustrated in
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In a HEMT manufactured by such a manufacturing method, In is eliminated that has been included in the electron supply layer 922 during the Si-activation annealing illustrated in
(Semiconductor Device)
Next, a semiconductor device will be described according to an embodiment of the present invention based on
The substrate 10 may be formed of a material other than SiC such as Si. Also, the electron transit layer 21 is formed to have the thickness of about 2 μm, the electron supply layer 22 is formed of In0.17Al0.83N having the thickness of about 10 nm, and the upper surface layer 23 is formed of Al0.2Ga0.8N having the thickness of about 10 nm.
A gate electrode 41, a source electrode 42, and a drain electrode 43 are formed on the upper surface layer 23. Also, n-type regions 20a are formed by applying ion implantation with an impurity element such as Si to the upper surface layer 23, the electron supply layer 22, and the electron transit layer 21 in regions where the source electrode 42 and the drain electrode 43 are formed. This makes it possible to lower the contact resistance between the upper surface layer 23, and the source electrode 42 and the drain electrode 43 in the regions where the n-type regions 20a are formed.
In the present embodiment, the electron transit layer 21 is formed of a nitride semiconductor including In, which is InAlN, or may be formed of InGaN or InAlGaN. Also, the structure may be modified to have an intermediate layer made of AlN formed between the electron transit layer 21 and the electron supply layer 22. The electron supply layer 22 may be formed of InAlGaN. In InAlN or the like, elimination of In is confirmed at a substrate temperature over 800° C. Therefore, it is preferable to set the substrate temperature greater than or equal to 500° C. and less than or equal to 800° C. when forming the electron supply layer 22 of InAlN or the like.
Also, the upper surface layer 23 may be formed as a layer not including In in a nitride semiconductor. For example, it may be formed of a nitride of one or more elements selected among B, Al, Ga, which includes GaN, AlN, and BGaN. Also, in the present embodiment, the upper surface layer 23 is formed as a film at substantially the same substrate temperature as that for forming the electron supply layer 22.
(Manufacturing Method of Semiconductor Device)
Next, a manufacturing method of the semiconductor device in the present embodiment will be described based on
First, as illustrated in
Next, as illustrated in
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In the present embodiment, the upper surface layer 23 is formed as a crystal film of AlGaN formed by epitaxial growth on the electron supply layer 22 formed of InAlN. A finding is obtained that elimination of In in the electron supply layer 22 is suppressed by forming such a crystal film of AlGaN on InAlN even if it is heated at a high temperature such as 1100° C. Therefore, in the present embodiment, the Si-doped regions 20b can become the n-type regions 20a without causing defect of In in the electron supply layer 22. Therefore, in the present embodiment, the on-resistance does not become great because the 2DEG 21a is not reduced, and the contact resistance can be lowered at the source electrode 42 and the drain electrode 43.
Second EmbodimentNext, a second embodiment will be described.
(Semiconductor Device)
Next, a semiconductor device will be described according to the present invention based on
The substrate 10 may be formed of a material other than SiC such as Si. Also, the electron transit layer 21 is formed to have the thickness of about 2 μm, the electron supply layer 22 is formed of In0.17Al0.83N having the thickness of about nm, and the upper surface layer 23 is formed of Al0.2Ga0.8N having the thickness of about 10 nm.
A source electrode 42 and a drain electrode are formed on the upper surface layer 23. An opening 23a is formed in a region where a gate electrode 41 is formed, by removing a part of the upper surface layer 23, and the gate electrode 41 is formed on the electron supply layer 22 at the opening 23a in the upper surface layer 23. This shortens the distance between the gate electrode 41 and the 2DEG 21a, with which a high-frequency characteristic can be improved. Also, n-type regions 20a are formed by applying ion implantation with an impurity element such as Si to the upper surface layer 23, the electron supply layer 22, and the electron transit layer 21 in regions where the source electrode 42 and the drain electrode 43 are formed. This makes it possible to lower the contact resistance between the upper surface layer 23, and the source electrode 42 and the drain electrode 43 in the regions where the n-type regions 20a are formed.
(Manufacturing Method of Semiconductor Device)
Next, a manufacturing method of the semiconductor device in the present embodiment will be described based on
First, as illustrated in
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Note that the content other than described above is substantially the same as in the first embodiment.
Third EmbodimentNext, a third embodiment will be described.
(Semiconductor Device)
A semiconductor device will be described according to the present invention based on
The substrate 10 may be formed of a material other than SiC such as Si. Also, the electron transit layer 21 is formed to have the thickness of about 2 μm, the electron supply layer 22 is formed of In0.17Al0.83N having the thickness of about 10 nm, and the upper surface layer 23 is formed of Al0.2Ga0.8N having the thickness of about 10 nm.
A gate electrode 41 is formed on the upper surface layer 23. Also, a part of the upper surface layer 23, the electron supply layer 22, and the electron transit layer 21 are removed in regions where a source electrode 42 and a drain electrode 43 are formed. Thus, in the present embodiment, the source electrode 42 and the drain electrode 43 are formed contacting the electron transit layer 21. Also, n-type regions 20a are formed by applying ion implantation with an impurity element such as Si to the upper surface layer 23, the electron supply layer 22, and the electron transit layer 21 in neighboring regions where the source electrode 42 and the drain electrode 43 are formed. This makes it possible to further lower the contact resistance because the electron transit layer 21 directly contacts the source electrode 42 and the drain electrode 43.
(Manufacturing Method of Semiconductor Device)
Next, a manufacturing method of the semiconductor device in the present embodiment will be described based on
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Note that the content other than described above is substantially the same as in the first embodiment.
Fourth EmbodimentNext, a fourth embodiment will be described.
(Semiconductor Device)
Next, a semiconductor device will be described according to the present invention based on
The substrate 10 may be formed of a material other than SiC such as Si. Also, the electron transit layer 21 is formed to have the thickness of about 2 μm, and the electron supply layer 22 is formed of In0.17Al0.83N having the thickness of about 10 nm.
A gate electrode 41, a source electrode 42, and a drain electrode 43 are formed on the electron supply layer 22. Also, n-type regions 20a are formed by applying ion implantation with an impurity element such as Si to the electron supply layer 22 and the electron transit layer 21 at regions where the source electrode 42 and the drain electrode 43 are formed. This makes it possible to lower the contact resistance with the source electrode 42 and the drain electrode 43.
(Manufacturing Method of Semiconductor Device)
Next, a manufacturing method of the semiconductor device in the present embodiment will be described based on
First, as illustrated in
Next, as illustrated in
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Note that although a case is described where the heat-protective film 31 is formed in the present embodiment, substantially the same semiconductor device can be manufactured without forming a heat-protective film 31. This is because the upper surface layer 23 formed on the electron supply layer 22 is a crystal film, with which the surface of the electron supply layer 22 does not become rough even if a heat-protective film 31 is not formed. Note that the content other than described above is substantially the same as in the first embodiment.
Fifth EmbodimentNext, a fifth embodiment will be described.
(Semiconductor Device)
Next, a semiconductor device will be described according to the present invention based on
The substrate 10 may be formed of a material other than SiC such as Si. Also, the electron transit layer 21 is formed to have the thickness of about 2 μm, and the electron supply layer 22 is formed of In0.17Al0.83N having the thickness of about 10 nm. Also, the intermediate layer 25 has the thickness of about 1 nm.
A gate electrode 41, a source electrode 42, and a drain electrode 43 are formed on the electron supply layer 22. Also, n-type regions 20a are formed by applying ion implantation with an impurity element such as Si to the electron supply layer 22 and the electron transit layer 21 at regions where the source electrode 42 and the drain electrode 43 are formed. This makes it possible to lower the contact resistance with the source electrode 42 and the drain electrode 43.
(Manufacturing Method of Semiconductor Device)
Next, a manufacturing method of the semiconductor device in the present embodiment will be described based on
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
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Note that the content other than described above is substantially the same as in the fourth embodiment. Also, the structure having an intermediate layer 25 as in the present embodiment may be applied to the semiconductor devices in the first to third embodiments.
Sixth EmbodimentNext, a sixth embodiment will be described.
(Semiconductor Device)
Next, a semiconductor device will be described according to the present invention based on
Specifically, the semiconductor device in the present embodiment has layers formed on a substrate 10 made of SiC or the like where the layers include a buffer layer 11 formed of AlN and the like, an electron transit layer 21 formed of i-GaN, and an electron supply layer 22 formed of InAlN, and an upper surface layer 23 formed of AlGaN which are stacked in this order. With this structure, 2DEG 21a is generated in the neighborhood of the interface between the electron transit layer 21 and the electron supply layer 22 in the electron transit layer 21.
The substrate 10 may be formed of a material other than SiC such as Si. Also, the electron transit layer 21 is formed to have the thickness of about 2 μm, the electron supply layer 22 is formed of In0.17Al0.83N having the thickness of about nm, and the upper surface layer 23 is formed of Al0.2Ga0.8N having the thickness of about 10 nm.
The source electrode 42 and the drain electrode 43 are formed on the upper surface layer 23. Also, the insulation film 60 is formed in a region on the upper surface layer 23 where the source electrode 42 and the drain electrode 43 are not formed, and the gate electrode 41 is formed in a predetermined region on the insulation film 60. In the present embodiment, the insulation film 60 is formed of aluminum oxide (Al2O3) to have the thickness of about 40 nm.
(Manufacturing Method of Semiconductor Device)
Next, a manufacturing method of the semiconductor device in the present embodiment will be described based on
First, as illustrated in
Next, as illustrated in
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In the semiconductor device in the present embodiment, a smaller number of trap levels are formed in the insulation film 60 or the like, with which stable operation can be realized.
Seventh EmbodimentNext, a seventh embodiment will be described. The present embodiment relates to a semiconductor device, a power source device, and a high-frequency amplifier.
The semiconductor device in the present embodiment includes a semiconductor device according to any of the first to sixth embodiments, which is contained in a discrete package, which will be described based on
First, a semiconductor device manufactured according to any of the first to sixth embodiments is cut off by dicing or the like to form a semiconductor chip 410, which is a HEMT made of GaN semiconductor materials. The semiconductor chip 410 is fixed on a lead frame 420 by a die attachment agent 430 such as solder.
Next, a gate electrode 441 is connected with a gate lead 421 by a bonding wire 431, a source electrode 442 is connected with a source lead 422 by a bonding wire 432, and a drain electrode 443 is connected with a drain lead 423 by a bonding wire 433. Note that the bonding wires 431, 432, and 433 are formed of a metal material such as Al. Also, the gate electrode 441 is a gate electrode pad in the present embodiment, which is connected with the gate electrode 41 of the semiconductor device according to any of the first to sixth embodiments. Also, the source electrode 442 is a source electrode pad, which is connected with the source electrode 42, and the drain electrode 443 is a drain electrode pad, which is connected with the drain electrode 43.
Next, resin sealing is performed by a transfer molding method using a mold resin 440. Thus, the HEMT made of GaN semiconductor materials can be manufactured as the discretely packaged semiconductor device.
Also, the power source device and the high-frequency amplifier in the present embodiment use one or more of the semiconductor devices in the first to sixth embodiments, respectively.
Based on
Also, based on
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Claims
1. A semiconductor device comprising:
- an electron transit layer configured to be formed on a substrate;
- an electron supply layer configured to be formed on the electron transit layer;
- an upper surface layer configured to be formed on the electron supply layer;
- a gate electrode configured to be formed on the electron supply layer or the upper surface layer;
- a source electrode and a drain electrode configured to be formed on the upper surface layer; and
- first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed,
- wherein the electron supply layer is formed of a nitride semiconductor including In,
- wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
2. A semiconductor device comprising:
- an electron transit layer configured to be formed on a substrate;
- an electron supply layer configured to be formed on the electron transit layer;
- an upper surface layer configured to be formed on the electron supply layer;
- a gate electrode configured to be formed on the electron supply layer or the upper surface layer;
- a source electrode and a drain electrode configured to be formed on the electron supply layer; and
- first conductivity-type regions configured to be formed in the electron supply layer immediately below regions where the source electrode and the drain electrode are formed,
- wherein the electron supply layer is formed of a nitride semiconductor including In,
- wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
3. The semiconductor device as claimed in claim 1, wherein the first conductivity-type region is also formed in a part of the electron transit layer immediately below the regions where the source electrode and the drain electrode are formed.
4. A semiconductor device comprising:
- an electron transit layer configured to be formed on a substrate;
- an electron supply layer configured to be formed on the electron transit layer;
- an upper surface layer configured to be formed on the electron supply layer;
- a gate electrode configured to be formed on the electron supply layer or the upper surface layer;
- a source electrode and a drain electrode configured to be formed on the electron transit layer; and
- first conductivity-type regions configured to be formed in the electron transit layer contacting the source electrode and the drain electrode,
- wherein the electron supply layer is formed of a nitride semiconductor including In,
- wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
5. The semiconductor device as claimed in claim 1, wherein the first conductivity-type is n-type.
6. The semiconductor device as claimed in claim 1, wherein the first conductivity-type regions have ion implantation applied with Si.
7. A semiconductor device comprising:
- an electron transit layer configured to be formed on a substrate;
- an electron supply layer configured to be formed on the electron transit layer;
- an upper surface layer configured to be formed on the electron supply layer;
- an insulation film configured to be formed on the upper surface layer;
- a gate electrode configured to be formed on the insulation film; and
- a source electrode and a drain electrode configured to be formed on the upper surface layer or the electron supply layer,
- wherein the electron supply layer is formed of a nitride semiconductor including In,
- wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
8. The semiconductor device as claimed in claim 7, wherein the insulation film is formed of a material including an aluminum oxide.
9. The semiconductor device as claimed in claim 1, further comprising:
- an intermediate layer configured to be formed between the electron transit layer and the electron supply layer,
- wherein the intermediate layer is formed of a material including AlN.
10. The semiconductor device as claimed in claim 1, wherein the upper surface layer is formed of a material including one of AlGaN, GaN, AlN, and BGaN.
11. The semiconductor device as claimed in claim 1, wherein the electron supply layer is formed of a material including InAlN.
12. The semiconductor device as claimed in claim 1, wherein the electron transit layer is formed of a material including GaN.
13. A manufacturing method of a semiconductor device, the method comprising:
- forming an electron transit layer, an electron supply layer, and an upper surface layer in order on a substrate by epitaxial growth;
- implanting ions of an impurity element of a first conductivity-type in regions immediately below where a source electrode and a drain electrode are formed in the electron supply layer and the upper surface layer;
- applying heat to activate the ions so that the regions with the implanted ions become first conductivity-type regions;
- forming the source electrode and the drain electrode on the upper surface layer;
- forming a gate electrode on the upper surface layer,
- wherein the electron supply layer is formed of a nitride semiconductor including In,
- wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
14. A manufacturing method of a semiconductor device, the method comprising:
- forming an electron transit layer, an electron supply layer, and an upper surface layer in order on a substrate by epitaxial growth;
- forming an insulation film on the upper surface layer;
- applying heat after the forming the insulation film;
- forming a source electrode and a drain electrode on the upper surface layer; and
- forming a gate electrode on the insulation film,
- wherein the electron supply layer is formed of a nitride semiconductor including In,
- wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
15. The manufacturing method of the semiconductor device as claimed in claim 14, wherein the insulation film is formed of a material including an aluminum oxide.
16. A power source device comprising:
- a semiconductor device including an electron transit layer configured to be formed on a substrate, an electron supply layer configured to be formed on the electron transit layer, an upper surface layer configured to be formed on the electron supply layer, a gate electrode configured to be formed on the electron supply layer or the upper surface layer, a source electrode and a drain electrode configured to be formed on the upper surface layer, and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed, wherein the electron supply layer is formed of a nitride semiconductor including In, wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
17. An amplifier comprising:
- a semiconductor device including an electron transit layer configured to be formed on a substrate, an electron supply layer configured to be formed on the electron transit layer, an upper surface layer configured to be formed on the electron supply layer, a gate electrode configured to be formed on the electron supply layer or the upper surface layer, a source electrode and a drain electrode configured to be formed on the upper surface layer, and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed, wherein the electron supply layer is formed of a nitride semiconductor including In, wherein the upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
Type: Application
Filed: Aug 4, 2016
Publication Date: Nov 24, 2016
Applicant: FUJITSU LIMITED (Kawasaki-shi)
Inventors: Masato Nishimori (Atsugi), Toshihide Kikkawa (Machida)
Application Number: 15/228,700