METAL RESISTOR FORMING METHOD USING ION IMPLANTATION
Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.
Technical Field
The present disclosure relates to metal resistors, and more specifically, to methods of forming a metal resistor with lower temperature coefficient of resistance (TCR) and low sheet resistance using ion implantation.
Related Art
Metal resistors are widely used in integrated circuit fabrication processes. For example, precision metal resistors are employed as resistors and electronic fuses (e-fuses) within integrated circuits to enable advanced functionalities that improve performance, provide memory on passive devices, provide chip identification, etc. Current metal resistor processing includes depositing a conductor on a substrate, e.g., silicon dioxide (SiO2), and annealing to stabilize the material. Current processing typically uses a tungsten silicide, WSi2.7, as the conductor. The conventional processing is disadvantageous because it creates a high temperature coefficient of resistance (TCR) and a relatively high resistivity. Temperature coefficient of resistance (TCR) describes the relative change of resistance that is associated with a given change in temperature. One approach to solve these issues is to employ other materials with lower TCR, but these materials are typically not compatible with semiconductor integration flow. For example, use of silicide WSi2.2 has been attempted, but it exhibits high non-uniformity and thus is difficult to employ.
SUMMARYA first aspect of the disclosure is directed to a method of forming a metal resistor, the method including: depositing a metal layer on a substrate; and forming the metal resistor by implanting a semiconductor species into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer.
A second aspect of the disclosure includes a method of forming a metal resistor, the method including: atomic layer depositing an adhesion layer on a dielectric upper layer of a substrate; chemical vapor depositing a tungsten (W) layer over the adhesion layer; and forming the metal resistor by implanting a silicon into the tungsten layer to form a tungsten silicide layer from at least a portion of the tungsten layer, the tungsten silicide layer including WSi2.7.
A third aspect of the disclosure related to a method of forming a metal resistor, the method including: atomic layer depositing an adhesion layer on a dielectric upper layer of a substrate, the adhesion layer including titanium nitride (TiN); chemical vapor depositing a tungsten (W) layer over the adhesion layer, the metal layer having a thickness of approximately 140-180 Angstroms (Å); forming the metal resistor by implanting a silicon species into the tungsten layer to form a tungsten silicide layer from at least a portion of the tungsten layer, wherein the tungsten silicide layer includes WSi2.7 and the implanting has a dose in a range of approximately 1012 to 1015 atoms/square centimeter (atoms/cm2) and an energy in a range of approximately 2 to 3 kilo-electronVolts (keV); and annealing the metal resistor, wherein the metal resistor has a sheet resistance of approximately 300-350 ohms/square (Ω/sq) prior to and after the annealing.
The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.
The embodiments of this disclosure will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
Embodiments of a method of forming a metal resistor are described herein. The methods include ion implanting a semiconductor species into a metal layer to form a metal resistor. Embodiments of the method according to the disclosure may reduce the thermal coefficient of resistance (TCR) from a typical range of, e.g., 500-800 parts per million per degree Celsius (ppm/° C.), by approximately 20% with high tune-ability and decreased sheet resistance by approximately 20% with tungsten silicide, WSi2.7. The embodiments of the disclosure can provide these features with broad adjustability and no change in the integration scheme, and without additional tooling. Ion implantation of semiconductor species can be used to promote a controlled alloying of a tungsten (W) layer, e.g., chemical vapor deposited W. By using different doses and energies of ion implantation the composition of the tungsten film can be tuned to adjust the resistivity and TCR. Consequently, the teachings of this disclosure can preserve the deposition uniformity across wafers, while lowering both TCR and sheet resistance.
Referring to the drawings,
Substrate 100 may further include an interlayer dielectric (ILD) layer 116 over SOI layer 114. ILD layer 116 may include but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK (a polyarylene ether available from Dow Chemical Corporation), a spin-on silicon-carbon containing polymer material available from JSR Corporation, other low dielectric constant (<3.9) material, or layers thereof. In one embodiment, a dielectric upper layer 118 of substrate 100 (i.e., of ILD layer 116) upon which metal resistor 102 (
Substrate 100 may be formed using any now known or later developed techniques, e.g., deposition, photolithography (patterning, etching, etc.), etc. As used herein, unless otherwise stated, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
In an alternative embodiment, also shown in
Subsequently conventional back-end-of-line (BEOL) processes can also be carried out. As understood in the art, BEOL processes may include any operations performed on the semiconductor wafer in the course of device manufacturing following first metallization, e.g., to provide interconnects, fuses, resistors, size up the IC, etc. In one embodiment, as shown in
Metal resistors 102 formed according to embodiments of the disclosure provide higher TCR and relatively higher resistivity compared to conventional metal resistors such as chemical vapor deposition (CVD) TiN, CVD WSi and physical vapor deposition (PVD) WSi. Embodiments of the disclosure may also include a metal resistor 102 having a tungsten silicide layer and a sheet resistance of greater than 300 Ω/sq.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A method of forming a metal resistor, the method comprising:
- depositing a metal layer on a substrate; and
- forming the metal resistor by implanting a semiconductor species into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer.
2. The method of claim 1, wherein the semiconductor species includes at least one of silicon and germanium.
3. The method of claim 2, further comprising ion implanting nitrogen into the semiconductor-metal alloy layer after implanting the semiconductor species.
4. The method of claim 1, wherein the metal layer includes tungsten (W), the semiconductor species includes silicon and the semiconductor-metal alloy includes tungsten silicide (WSix).
5. The method of claim 4, wherein the tungsten silicide includes WSi2.7.
6. The method of claim 1, further comprising depositing an adhesion layer over the substrate prior to depositing the metal layer.
7. The method of claim 6, wherein the adhesion layer includes one of titanium nitride and organometallic tungsten, and the metal layer includes tungsten (W).
8. The method of claim 6, wherein the metal layer depositing includes chemical vapor deposition (CVD) and the adhesion layer depositing includes atomic layer deposition (ALD).
9. The method of claim 1, wherein the metal layer depositing includes chemical vapor depositing (CVD).
10. The method of claim 1, wherein the metal layer has a thickness of approximately 140-180 Angstroms (Å).
11. The method of claim 1, wherein the implanting has a dose in a range of approximately 1012 to 1015 atoms/square centimeter (atoms/cm2).
12. The method of claim 1, wherein the implanting uses an energy in a range of approximately 2 to 3 kilo-electronVolts (keV).
13. The method of claim 1, wherein the metal resistor has a sheet resistance of approximately 300-350 ohms/square (Ω/sq).
14. The method of claim 1, wherein forming the metal resistor further includes annealing, and wherein a sheet resistance of the metal resistor remains substantially unchanged prior to and after the annealing.
15. A method of forming a metal resistor, the method comprising:
- atomic layer depositing an adhesion layer on a dielectric upper layer of a substrate;
- chemical vapor depositing a tungsten (W) layer over the adhesion layer; and
- forming the metal resistor by implanting a silicon into the tungsten layer to form a tungsten silicide layer from at least a portion of the tungsten layer, the tungsten silicide layer including WSi2.7.
16. The method of claim 15, wherein the tungsten layer has a thickness of approximately 140-180 Angstroms (Å).
17. The method of claim 15, wherein the implanting has a dose in a range of approximately 1012 to 1015 atoms/square centimeter (atoms/cm2).
18. The method of claim 15, wherein the implanting uses an energy in a range of approximately 2 to 3 kilo-electronVolts (keV).
19. The method of claim 15, wherein the metal resistor has a sheet resistance of approximately 300-350 ohms/square (Ω/sq).
20. A method of forming a metal resistor, the method comprising:
- atomic layer depositing an adhesion layer on a dielectric upper layer of a substrate, the adhesion layer including titanium nitride (TiN);
- chemical vapor depositing a tungsten (W) layer over the adhesion layer, the metal layer having a thickness of approximately 140-180 Angstroms (Å);
- forming the metal resistor by implanting a silicon species into the tungsten layer to form a tungsten silicide layer from at least a portion of the tungsten layer, wherein the tungsten silicide layer includes WSi2.7 and the implanting has a dose in a range of approximately 1012 to 1015 atoms/square centimeter (atoms/cm2) and an energy in a range of approximately 2 to 3 kiloelectronVolts (keV); and
- annealing the metal resistor, wherein the metal resistor has a sheet resistance of approximately 300-350 ohms/square (Ω/sq) prior to and after the annealing.
Type: Application
Filed: Nov 4, 2015
Publication Date: May 4, 2017
Patent Grant number: 10263065
Inventors: Domingo A. Ferrer Luppi (Fishkill, NY), Aritra Dasgupta (Clifton Park, NY), Benjamin G. Moser (Malta, NY)
Application Number: 14/932,441