METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method includes: a first step of designing the semiconductor device by using CAD and outputting design CAD data; a second step of correcting the design CAD data to correspond to a matching trial object of the semiconductor device and outputting corrected CAD data; a third step of manufacturing the semiconductor device based on the design CAD data; a fourth step of capturing a tomographic image of the manufactured semiconductor device; a fifth step of comparing a shape and a dimension of a unit included in the semiconductor device between the tomographic image and the corrected CAD data; and a sixth step of determining that the matching trial object is failed when a difference therebetween as a result of the comparison in the fifth step is equal to or larger than a predetermined amount.
The present application claims priority from Japanese Patent Application No. 2016-029652 filed on Feb. 19, 2016, the content of which is hereby incorporated by reference into this application.
TECHNICAL FIELD OF THE INVENTIONThe present invention relates to a technique of manufacturing a semiconductor device. More particularly, the present invention relates to a technique effectively applied to a method of manufacturing a semiconductor device for inspecting a matching trial object of a manufactured semiconductor device.
BACKGROUND OF THE INVENTIONWhen it is necessary to observe a cross-sectional shape for an internal structure and electrical connection of a semiconductor device in inspection and analysis of a matching trial object of the manufactured semiconductor device, it is general to employ such a method of polishing the semiconductor device as exposing the cross section. However, in the method using the polishing, for example, when the shape analysis is performed over a plurality of cross sections in a depth direction, it is necessary to perform the analysis while polishing the device little by little, and therefore, it takes time and cost for the analysis. In addition, since the method is destructive inspection, the method has such a problem that a polished unit cannot be observed again.
As a method for solving the problem, for example, a non-destructive three-dimensional inspection method that employs an X-ray computed tomography (CT) and others is used. A tomographic image captured by the X-ray CT can be handled as image data by using a computer, and thus, the matching trial object can be analyzed by, for example, comparing the tomographic image and computer-aided design (CAD) data based on a calculation on the computer.
As a technique relating to the above-described method, for example, Japanese Patent No. 4082718 (Patent Document 1) and Japanese Patent No. 5220316 (Patent Document 2) describe a technique of inspecting a defect of a target object by comparing the CAD data and the image data obtained by the tomography apparatus such as the X-ray CT.
SUMMARY OF THE INVENTIONVarious heat treatments and heat processes are performed during a process of manufacturing a semiconductor device, and, as a result, a practical matching trial object is different from the design CAD data at a certain degree in some cases such that deformation such as warpage or distortion occurs or such that a solder alloy portion that is not on the design occurs. In such a case, the appropriate determination of the matching trial object is impossible in some cases in employing the shape analysis method of comparing the design CAD data and the tomographic image obtained by the X-ray CT as a conventional technique.
This is because the design CAD data is data created at the time of design before the manufacture, and because a determination criteria for the matching trial object after the manufacture is not reflected on the design CAD data. Particularly in inspection for a three-dimensional shape dimension, a contour shape of the matching trial object can be variously changed from the design CAD data, and therefore, the appropriate shape analysis is impossible even by the comparison with the design CAD data different from the matching trial object.
Other object and novel characteristics will be apparent from the description of the present specification and the accompanying drawings.
A method of manufacturing a semiconductor device according to an embodiment includes: a first step of designing the semiconductor device by using CAD to output design CAD data; a second step of correcting the design CAD data so as to correspond to a matching trial object of the semiconductor device and outputting corrected CAD data; a third step of manufacturing the semiconductor device based on the design CAD data; a fourth step of capturing a tomographic image of the manufactured semiconductor device; a fifth step of comparing the tomographic image and the corrected CAD data in a shape and a dimension of a unit included in the semiconductor device; and a sixth step of determining that the matching trial object is failed when a difference therebetween as a result of the comparison in the fifth step is equal to or larger than a predetermined amount.
According to the embodiment, an accuracy of in the shape analysis can be improved by comparing the tomographic image of the semiconductor device obtained using X-ray CT and the CAD data of the semiconductor device.
Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings. Note that the same components are denoted by the same reference symbols throughout all the drawings for describing the embodiments in principle, and the repetitive description thereof will be omitted. On the other hand, while the part described with the reference character in a certain diagram is not illustrated again in the description for other drawings, the part is described with the same reference character in some cases.
To a method of manufacturing a semiconductor device according to an embodiment of the present invention, a non-destructive three-dimensional inspection method which compares CAD data and a tomographic image captured using X-ray CT is applied in a matching trial object analysis of the manufactured semiconductor device. Accordingly, a plurality of optional cross sections of the semiconductor device can be repeatedly inspected for a short period of time. Further, the accuracy of the shape analysis is improved by using not the design CAD data different from the matching trial object but the corrected CAD data which has been subjected to such correction as corresponding to the matching trial object as the CAD data. Further, the cause of the failure can be estimated based on an inspection result, and a result of the estimation can be fed back for correction of a manufacturing condition.
Note that the semiconductor manufacturing method according to the present embodiment can be applied to a semiconductor manufacturing apparatus or a semiconductor inspection apparatus such as an X-ray CT apparatus as a system by, for example, executing a program using a central processing unit (CPU) or using control and calculation through hardware such as a microcomputer.
Alternatively, the method can be configured as a system which associates a computer system executing the program and performing control and calculation as described above with the semiconductor manufacturing apparatus, the X-ray CT apparatus, or others.
<Semiconductor Device>
In the top view in
The side view in
<Conventional Method of Manufacturing Semiconductor Device and Conventional Technique of Matching Trial Object Analysis>
Returning to
Then, the matching trial object analysis is performed for the semiconductor device 1 manufactured in Step S02. First, a cross-sectional shape of the manufactured semiconductor device 1 at a desired position is acquired (S03). As described above, a destructive inspection technique of obtaining a cross-sectional shape by polishing the semiconductor device 1 has been conventionally applied. Meanwhile, as described in Patent Documents land 2 or others, non-destructive inspection using X-ray CT is performed in some cases.
Returning to
On the other hand, when the dimension is not within the standard, while the cause of the failure is estimated by human's decision based on a status of the determination and others (S06), and various parameters such as a material parameter of the manufacturing condition are appropriately changed based on the content of estimation (S07), and then, the process returns to Step S02 to manufacture the semiconductor device 1 again. That is, for the matching trial object of the semiconductor device 1, a series of processes are repeated until the dimension of the cross-sectional shape of the inspection target unit enters within the standard.
In the above-described conventional manufacturing method and inspection method, while one of the target and the reference to be compared is the cross-sectional shape of the practical matching trial object having a shape distortion or others, the other is the ideal design CAD data 100 having no shape distortion. Accordingly, it is difficult to appropriately perform contrast and comparison between them, and it is difficult to improve the accuracy of the matching trial object analysis.
<Method of Manufacturing Semiconductor Device and Matching Trial Object Analysis Technique>
Next, in the present embodiment, the design CAD data 100 is corrected so that a status of the matching trial object is reflected to the data (S12). As the specific correction content, for example, correction of a contour shape and a dimension value of a unit or others and addition of a unit may be cited. Hereinafter, such content of correction will be described.
(1) Correction of Contour Shape and Dimension Value
This step corrects a certain difference in the shape dimension between the design CAD data 100 and the matching trial object caused by the change in dimension due to thermal history such as reflow and baking during the process of manufacturing the semiconductor device 1 and due to the warpage and the distortion because of mismatch of material characteristics among the respective units. To be specific, the corrected CAD data 200 is obtained by acquiring the shape dimension of the matching trial object to be obtained by the manufacturing process and correcting the design CAD data 100 based on the acquired shape dimension.
In order to acquire the shape dimension of the matching trial object, for example, a result of finite element method (FEM) analysis can be used, or dimensions of the respective units of the practically-manufactured semiconductor device 1 can be practically measured. The process of obtaining the corrected CAD data 200 by reflecting the shape dimension of the matching trial object acquired here to the design CAD data 100 and obtaining may be manually performed by a human. Alternatively, the process may be automatically performed through computer processing or others if possible.
In the correction using the FEM analysis as described above, it is desirable to analyze each material parameter of the units forming the semiconductor device 1 for each condition of combinations in appropriate value change and to store a result of the analysis so that the result can be referred. As the material parameter that can influence the shape dimension of the matching trial object, it is possible to appropriately use, for example, a parameter relating to assembly accuracy (such as accuracy of alignment between the semiconductor chip 30 and the organic substrate 10), a parameter relating to a dimension of a material (such as a thickness of a core material of the organic substrate 10 (substrate core material)), a parameter relating to a property of the material (such as a linear expansion coefficient of the substrate core material or an underfill resin 41), and others.
A shape dimension value, which is obtained as a result of FEM analysis with a combination in a case of usage of a design value (reference value) for each material parameter, corresponds to that of the matching trial object of the semiconductor device 1 manufactured using the design value (reference value) for the each material parameter. In addition, a range or a region is referred to as a standard adaptation range, the range or the region including a result of FEM analysis with combination of values set within a range between standard upper and lower limits of each material parameter.
Note that the respective FEM analysis results obtained while changing the respective material parameter values in order to obtain the corrected CAD data 200 can be used as comparison data in the determination of the quality of the matching trial object of the practically-manufactured semiconductor device 1. Accordingly, it is desirable to record and accumulate the respective FEM analysis results in linkage with information of combinations of the respective material parameter values at the time of performing the analysis.
As described above, the shape dimension of the matching trial object may be acquired by measuring a practical dimension of the practically-manufactured semiconductor device 1. For example, each dimension of the matching trial object of the solder bump 42 as illustrated in
Further, for example, a mean value ±3σ or others may be defined as the standard upper and lower limit values by measuring practical dimensions of a plurality of samples of the semiconductor device 1 and using statistic calculation. By using these values, it is possible to create the corrected CAD data 200 with the upper limit of the standard adaptation range (the corrected CAD data 201b illustrated in
The design CAD data 100 is corrected based on the shape dimension of the matching trial object by using the technique as described above, so that the corrected CAD data 200 can be obtained. Meanwhile, the correction based on the FEM analysis result causes a difference between the FEM analysis result and the practical matching trial object in some cases. This is because the FEM is only an approximate calculation based on mesh division of a continuum by finite elements, and besides, because a model is simplified in some cases in order to shorten the analysis time. Thus, the matching trial object and the FEM analysis result may be matched with each other by further measuring the practical dimension of the matching trial object of the sample of the manufactured semiconductor device 1 and equalizing the practical dimension and the FEM analysis result to each other.
To be specific, for example, a primary correction is performed to the design CAD data 100 by performing the FEM analysis to the design CAD data 100 first, and then, a secondary correction (equalization) is performed based on the result obtained by measuring the practical dimension. Note that equalization with the FEM analysis results under combination conditions of a plurality of material parameter values is required in order to correctly equalize a change amount of each material parameter value and a change amount of a shape of the inspection target (a shape of the solder bump 42 in the present embodiment) to each other.
As described above, the correction of the design CAD data 100 may be performed by adding a new unit not embedded in the original design CAD data 100 in addition to the above-described correction of the contour shape or the dimension value. For example, in the manufacturing process, a solder alloy layer is formed between an electrode and a solder in some cases when the solder bump 42 is connected by the reflow to the electrode which is formed on a surface of the organic substrate 10 and which is made of copper or nickel. The solder alloy layer formed here is handled as the new unit, and added to the corrected CAD data 200. In this case, a user manually corrects the design CAD data 100 based on, for example, a result obtained by practically observing and measuring the matching trial object such as the cross section.
Returning to
After the semiconductor device 1 is manufactured, the matching trial object analysis of the semiconductor device is performed. First, a tomographic image of the manufactured semiconductor device 1 is captured through the non-destructive inspection by using the X-ray CT (S14). In the X-ray CT, a plurality of sliced tomographic images of the semiconductor device 1 can be obtained. By performing image processing and reconstruction to the obtained respective tomographic image, three-dimensional internal information (voxel data) of the semiconductor device 1 can be obtained. Then, a success-or-failure determination process is performed (S15) by comparing the corrected CAD data 200 (the corrected CAD data 201 in relation to the solder bump 42 in the present embodiment) obtained in Step S12 with the three-dimensional tomographic image information of the inspection target object (the solder bump 42 in the present embodiment) obtained in Step S14.
For extracting the contour of the target object from such image data, a publicly-known technique such as a histogram method can be appropriately used. In the histogram method, a threshold of gradation for separating different units is acquired by obtaining a gradation histogram of the image data (each three-dimensional voxel data). The middle of
Returning to
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In this state, first, a predetermined range of the tomographic image 300 is searched while taking the center of gravity of the corrected CAD data 201 as the center so that the unit whose center of gravity is close thereto is searched. As illustrated in the central drawing, the example of
Next, each correlation in the contour shape between the corrected CAD data 201 and each of the searched candidate units of the tomographic image 301 is calculated, and a unit having the largest correlation, that is, having the most similar contour shape is specified. The example of
The linking process among the unit elements between the tomographic image 300 and the corrected CAD data 200 as described above may be automatically performed through computer processing or may be manually performed while a user checks a monitor. The unit elements may be liked to one another for each of all units included in the semiconductor device 1 or appropriately for only some of the units.
Returning to
As a content for the comparison in the alignment, for example, a positional shift amount is calculated by acquiring a difference (movement amount in the alignment of the center of gravity) at the center of gravity between the tomographic image 301 and the corrected CAD data 201, acquiring a rotation angle of the contour shape, or acquiring others. At this time, for example, the correlation calculation result of the contour shape of the target unit that has been described in
In addition, the number of voxels in a region where the contour of the tomographic image 301 is out of the corrected CAD data 201a (with the upper limit of the standard adaptation range) (a region where the shape dimension of the target unit is larger than the standard adaptation range) is calculated, and then, it may be determined that the dimension is within the standard adaptation range when the number of voxels is zero. In addition or alternatively, the number of voxels in a region where the contour of the corrected CAD data 201b (with the lower limit of the standard adaptation range) is out of the tomographic image 301 (a region where the shape dimension of the target unit is smaller than the standard adaptation range) is calculated, and then, it may be determined that the dimension is within the standard adaptation range when the number of voxels is zero.
In addition, a histogram illustrated in
Returning to
On the other hand, if it is without the standard, that is, if it is found that there is the difference between the matching trial object of the inspection target unit and the design value, the cause of the failure is estimated based on the content of the difference and others (S18), and then, a mismatch amount of the material parameter is calculated (S19).
To be specific, the analysis result having the similar contour shape is searched and specified by comparing the tomographic image 300 and a plurality of FEM analysis results obtained while changing the condition of the material parameter value at the time of correcting the design CAD data 100 in Step S12. Further, the content of the condition of the material parameter value corresponding to the specified FEM analysis result is compared with that of the material parameter value (that is, the design value) of the manufacturing condition at the time of practically manufacturing the semiconductor device 1 including the inspection target unit in Step S13. Accordingly, the material parameter which becomes the cause making the difference between the matching trial object and the design value (more correctly, the corrected CAD data 200 obtained by correcting the design CAD data 100) is estimated, and the mismatch amount therebetween is calculated.
Further, the the example of
In this case, it can be estimated that the matching trial object of the linear expansion coefficient of the substrate core material used in the semiconductor device 1 which becomes the target for acquisition of the tomographic image 301 is 30 ppm/deg higher than 20 ppm/deg which is the design value. That is, it can be estimated that the material parameter which is the cause of the difference between the design value and the matching trial object in the solder bump 42 is the linear expansion coefficient of the substrate core material of the organic substrate 10, and that the mismatch amount from the design value is “30-20=10 ppm/deg”.
The example of
Further, in the example of
Returning to
Then, the material parameter value in the manufacturing condition is changed and corrected (S21) so as to reflect the material parameter which is the cause of the difference and the mismatch amount output in Step S20 thereon, and the semiconductor device 1 is manufactured again returning to Step S13. For example, as illustrated in the example of
Further, a series of processes of Step S13 and the subsequent steps are repeated until the shape dimension of the matching trial object of the semiconductor device 1 enters within the standard adaptation range.
As described above, in the method of manufacturing the semiconductor device according to the embodiment of the present invention, the tomographic image 300 captured using the X-ray CT and the corrected CAD data 200 corrected based on the result of the matching trial object are compared with each other in the matching trial object analysis of the manufactured semiconductor device 1. Accordingly, the accuracy of the shape analysis can be improved, the mismatch amount from the material parameter which is the cause of the failure can be estimated based on the inspection result, and the result can be fed back to the correction of the manufacturing condition. In addition, by employing the non-destructive technique of using the tomographic image 300 captured using the X-ray CT, a plurality of arbitrary cross sections of the semiconductor device 1 can be repeatedly inspected for a short period of time. In the foregoing, the invention made by the present inventors has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention. For example, the above-described embodiments have been explained for easily understanding the present invention, but are not always limited to the one including all structures explained above. Further, the other structure can be added to/eliminated from/replaced with a part of the structure of the above-described embodiments.
For example, in the present embodiment, the X-ray CT is used in order to obtain the tomographic image of the semiconductor device 1. However, other non-destructive tomographic imaging technique can be also appropriately used. In addition, the FEM is used as the technique of acquiring the matching trial object through numerical calculation. However, other numerical calculation or simulation technique can be also appropriately used.
The present invention can be employed for a method of manufacturing a semiconductor device for inspecting a matching trial object of the manufactured semiconductor device.
Claims
1. A method of manufacturing a semiconductor device which includes inspection of a matching trial object of the semiconductor device, the method comprising:
- a first step of designing the semiconductor device by using CAD and outputting design CAD data;
- a second step of correcting the design CAD data so as to correspond to the matching trial object of the semiconductor device and outputting corrected CAD data;
- a third step of manufacturing the semiconductor device based on the design CAD data;
- a fourth step of capturing a tomographic image of the manufactured semiconductor device;
- a fifth step of comparing the tomographic image and the corrected CAD data in a shape and a dimension of a unit included in the semiconductor device; and
- a sixth step of determining that the matching trial object is failed when a difference therebetween as a result of the comparison in the fifth step is equal to or larger than a predetermined amount.
2. The method of manufacturing the semiconductor device according to claim 1,
- wherein the correction of the design CAD data in the second step includes correction of the dimension of the unit included in the semiconductor device.
3. The method of manufacturing the semiconductor device according to claim 1,
- wherein the correction of the design CAD data in the second step includes addition of a unit which is newly formed in manufacturing the semiconductor device.
4. The method of manufacturing the semiconductor device according to claim 2,
- wherein a dimension of the unit of the design CAD data is corrected based on an output which is acquired by numerical calculation of the matching trial object of the semiconductor device.
5. The method of manufacturing the semiconductor device according to claim 2,
- wherein a dimension of the unit of the design CAD data is corrected based on a dimension which is practically measured in the semiconductor device which is practically manufactured.
6. The method of manufacturing the semiconductor device according to claim 2,
- wherein a dimension of the unit of the design CAD data is corrected based on an output which is acquired by numerical calculation of the matching trial object of the semiconductor device and based on a dimension which is practically measured in the semiconductor device which is practically manufactured.
7. The method of manufacturing the semiconductor device according to claim 1,
- wherein, in the second step, an upper limit and a lower limit of an adaptation range of a shape and a dimension of the unit of the corrected CAD data are further determined based on an output which is acquired by numerical calculation of the matching trial object of the semiconductor device for each condition of combination of a design value, an upper limit value, and a lower limit value of one or more material parameters in a manufacturing condition of the semiconductor device.
8. The method of manufacturing the semiconductor device according to claim 7,
- wherein, in the fifth step, the tomographic image is compared with the upper limit and the lower limit of the adaptation range of the corrected CAD data for the unit, and,
- in the sixth step, it is determined that the matching trial object is failed when the tomographic image exceeds the upper limit or the lower limit of the adaptation range.
9. The method of manufacturing the semiconductor device according to claim 1,
- wherein the correction of the design CAD data in the second step includes correction of a shape and a dimension of the unit included in the semiconductor device for each condition of combination of one or more material parameter values in a manufacturing condition of the semiconductor device,
- the method further includes:
- a seventh step of specifying the corrected CAD data having the most similar shape and dimension of the unit to those of the tomographic image when the matching trial object is failed in the fifth step; and
- an eighth step of acquiring each difference between a design value of each of the material parameters at time of manufacturing the semiconductor device which is an inspection target and a value of each of the material parameters corresponding to the corrected CAD data specified in the seventh step, and specifying the material parameter which is a cause of the failure and an amount of the corresponding difference.
10. The method of manufacturing the semiconductor device according to claim 9, further comprising
- a ninth step of changing the manufacturing condition of the semiconductor device based on the amount of the difference corresponding to the material parameter specified in the eighth step.
11. The method of manufacturing the semiconductor device according to claim 10,
- wherein the third and subsequent steps are repeated based on the manufacturing condition changed in the ninth step until it is not determined that the matching trial object is failed in the sixth step.
Type: Application
Filed: Jan 11, 2017
Publication Date: Aug 24, 2017
Inventors: Yoshihiro ONO (Tokyo), Kenji SAKATA (Tokyo)
Application Number: 15/403,203