LAYOUT STRUCTURE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
In a circuit block, a plurality of cell rows, each being comprised of a plurality of standard cells arranged in a first direction, are arranged in a second direction perpendicular to the first direction, thereby forming a circuit of SOI transistors. The circuit block includes a plurality of antenna cells, each including an antenna diode provided between a power supply line and a substrate or a well. In at least a part of the circuit block, the antenna cells are arranged at constant intervals in at least one of the first and second directions.
This is a continuation of International Application No. PCT/JP2015/005003 filed on Oct. 1, 2015, which claims priority to Japanese Patent Application No. 2014-229804 filed on Nov. 12, 2014. The entire disclosures of these applications are hereby incorporated by reference.
BACKGROUNDThe present disclosure relates to a layout structure for a semiconductor integrated circuit including transistors with a silicon-on-insulator (SOI) structure (hereinafter referred to as “SOI transistors”).
Meanwhile, a semiconductor device manufacturing process may sometimes cause a so-called “antenna error.” The antenna error refers to a phenomenon that a transistor's gate dielectric under its gate electrode suffers either breakdown or damage due to the influx, into the gate electrode, of electric charges generated by plasma in the ambient during the manufacturing process of the transistor and collected in the metal wires of the transistor that are electrically connected to the gate electrode. In the case of an SOI transistor, the possibility of such antenna errors' occurring in not only the gate dielectric but also the buried insulator under the source or drain needs to be taken into account. The reason is that those electric charges collected in the metal wires of the transistor being manufactured also flow into the source or drain electrically connected to the metal wires to cause breakdown or damage to the buried insulator under a doped layer serving as the source or drain.
Thus, in order to avoid causing such antenna errors in an SOI transistor, Japanese Unexamined Patent Publication No. 2003-133559 discloses a technique for inserting an antenna diode for dissipating those electric charges into the substrate.
Japanese Unexamined Patent Publication No. 2003-133559, however, fails to disclose how to actually insert such an antenna diode into a semiconductor integrated circuit including SOI transistors.
Thus, the present disclosure provides a layout structure for a semiconductor integrated circuit including SOI transistors with such antenna errors that could occur in the buried insulator under the source or drain taken into account.
SUMMARYAn aspect of the present disclosure provides a layout structure for a semiconductor integrated circuit including silicon-on-insulator (SOI) transistors. The structure includes a circuit block in which a plurality of cell rows, each being comprised of a plurality of standard cells arranged in a first direction, are arranged in a second direction that is perpendicular to the first direction, thereby forming a circuit of the SOI transistors. The circuit block comprises a plurality of antenna cells, each including an antenna diode formed between a power supply line for supplying power to the circuit block and a substrate or a well. In at least a part of the circuit block, the antenna cells are arranged at constant intervals in at least one of the first and second directions.
According to this aspect, a circuit block as an arrangement of a plurality of cell rows includes antenna cells, each including an antenna diode provided between a power supply line and a substrate or a well. The antenna cells are arranged at constant intervals in at least one of a first direction in which standard cells are arranged in each cell row or a second direction in which those cell rows are arranged. This layout structure is implemented by regular placement of antenna cells during a physical design process of the circuit block. This provides a technique for avoiding causing antenna errors without prolonging the design turnaround time (TAT) irrespective of the circuit area or shape of the circuit block.
The present disclosure provides a technique for avoiding causing antenna errors without prolonging the design TAT for a semiconductor integrated circuit including SOI transistors.
Embodiments of the present disclosure will now be described with reference to the accompanying drawings.
In the circuit block 51 shown in
An antenna cell 20 is inserted into the cell row 10F. As shown in
In the configuration shown in
Now, it will be described what significance such a regular arrangement of the antenna cells 20 has according to the present disclosure.
In a semiconductor integrated circuit comprised of transistors with a so-called “bulk structure,” only the possibility of antenna errors' occurring in their gate dielectric needs to be taken into account. That is why checking the circuit for any antenna errors, named “antenna inspection,” is usually performed on a circuit block, of which the operating timings have already converged after a placement of standard cells and routing have been done. Specifically, the antenna inspection is executed by detecting, based on a given antenna ratio, any spots that would possibly cause antenna errors, inserting antenna cells into the vicinity of those spots, and then routing and connecting the antenna diodes.
Meanwhile, a semiconductor integrated circuit comprised of SOI transistors should be free from antenna errors in not only its gate dielectric but also the buried insulator under its doped layer as well. For example, when a power supply line is provided for an M1 layer (that is the lowest-level metal interconnect layer) within the circuit block, electric charges collected in this power supply line will flow into a portion of the doped layer to function as the source. At this point in time, antenna errors could occur in the buried insulator under that portion of the doped layer to function as the source.
In this case, attempting to fix the errors by inserting antenna cells into those spots that would possibly cause antenna errors as in the known art mentioned above would pose the following problems. First of all, the number of antenna cells to be inserted increases proportionally to the total area of the M1 power supply lines to be charged, which increases with the area of the circuit block. That is why the larger the area of the circuit block, the greater the number of antenna cells to be inserted. This more and more frequently creates the need for relocating standard cells that have already been placed at the destinations of the antenna cells, thus causing operating timing errors of the circuit or prolonging the design turnaround time (TAT). In a worst case, inability of inserting any antenna cells could hamper the physical design of the circuit block utterly.
Furthermore, power supply lines include not only the power supply lines to be placed within the circuit block but also chip-level power supply lines to be routed at a higher level. The chip-level power supply lines are a high-order power supply structure for connecting together the power supplies of multiple circuit blocks. The chip-level power supply lines should have resistance low enough to curb a voltage drop, and therefore, have a broad line width, a high wiring density, and an extremely wide wiring area. That is why the chip-level power supply lines would have a huge quantity of electric charges collected. However, it is not until the chip-level design is completed that antenna errors caused by the huge quantity of electric charges collected in those lines are detected in the buried insulator. Therefore, the conventional technique of attempting to fix the antenna errors after having spotted them would require the designer to go back from the chip-level design to the block design, thus leading to a significantly prolonged design TAT.
Thus, to overcome these problems, the present disclosure adopts the following technique. In general, an antenna error is determined by the antenna ratio, i.e., the ratio of the area of a metal wire to the area of the doped layer of an antenna diode connected to the metal wire. That is why at the stage of physical circuit block design, the placement density of antenna cells with antenna diodes is determined in accordance with an antenna rule, and the antenna cells are placed regularly to meet the maximum allowable placement density. This allows only a power supply line with a predetermined area or less to be connected to each antenna cell, thus limiting the antenna ratio to a predetermined value or less with reliability. This technique dramatically decreases the likelihood of causing antenna errors irrespective of the circuit area or block shape, thus substantially preventing the circuit's operating timings or design TAT from being affected negatively. In addition, this can also eliminate the need for inserting an excessive number of antenna cells and therefore can cut down the chip area effectively as well.
Furthermore, this technique is applicable to not just the power supply lines within the circuit block but also the chip-level power supply lines as well. A specific exemplary application of this technique is as follows.
Suppose a power supply mesh having a regular grid pattern in which power supply lines are arranged at predetermined intervals is laid out on a circuit block. The power supply mesh is connected to the doped layer over the buried oxide in the SOI structure via the power supply lines in the circuit block. The wiring area S0 of the power supply mesh per unit area is constant on the circuit block, since the power supply mesh is regularly laid out on the circuit block. That is why if the doped layer area of an antenna diode per unit area is S1 and the circuit block area is A, the antenna ratio R is given by the following equation:
R=S0×A/S1×A=S0/S1
The upper limit of the antenna ratio R is defined by the antenna rule. Thus, the lower limit of the doped layer area S1 of an antenna diode per unit area is automatically determined by the area S0 of the power supply mesh per unit area. Then, antenna cells with antenna diodes just need to be placed in the circuit block such that the doped layer area S1 becomes equal to or greater than the lower limit defined by the antenna rule and the wiring area S0. For example, the antenna cells 20 may be placed every predetermined number of cell rows at constant intervals P in the arrangement direction of the standard cells 10 as shown in
The regular arrangement of the antenna cells 20 does not have to be the layout shown in
Furthermore, the antenna cells 20 do not have to be regularly placed in the same pattern over the entire circuit block, but may also be placed regularly in one pattern in one part of the circuit block and placed in a different pattern in another part of the circuit block. For example, the arrangement interval of the antenna cells 20 in the arrangement direction of the standard cells 10 may be changed from one area in the circuit block to another. Alternatively, the interval between the cell rows to have the antenna cells 20 may be changed from one area in the circuit block to another as well.
In other words, if at least three antenna cells are arranged at constant intervals within a cell row, it can be said that the antenna cells are arranged regularly according to the technique of the present disclosure. Naturally, all antenna cells may be arranged at constant intervals in that cell row. Also, if antenna cells are arranged at regular cell row intervals (e.g., every other row) in at least three cell rows, then it can also be said that the antenna cells are arranged regularly according to the technique of the present disclosure. Naturally, antenna cells may also be arranged at regular cell row intervals in all of the cell rows of the entire circuit block.
(First Alternative Layout Structure)
In the circuit block 52 shown in
In the circuit block 52 shown in
To implement the arrangement of the antenna cells 20 and the TAP cells 25 shown in
The interval T between the TAP cells 25 is determined mainly by a latch-up rule.
If the interval T is approximately equal to the interval P to be determined mainly by the antenna rule, using the antenna cells 30 such as the one shown in
Optionally, the physical design process may also be carried out by placing the antenna cell 20 and the TAP cell 25 adjacent to each other at each predetermined location, instead of using the antenna cells 30 with the TAP function as shown in
(Second Alternative Layout Structure)
In the circuit block 53 shown in
The structure shown in
In the exemplary configuration shown in
The various exemplary layout structures described above may be adopted in any arbitrary combination. For example, the layout structure shown in
Also, in the exemplary layout structures described above, each antenna cell is supposed to be a VDD/VSS-compatible antenna cell including both a VDD antenna diode and a VSS antenna diode. However, this is only a non-limiting exemplary embodiment of the present disclosure. Alternatively, VDD antenna cells each including a VDD antenna diode may be arranged separately from VSS antenna cells each including a VSS antenna diode. Furthermore, it does not matter whether any of the VDD and VSS antenna diodes is formed in a P-type region or an N-type region or provided on a well or a substrate.
The present disclosure contributes to eliminating antenna errors from a semiconductor integrated circuit with SOI transistors, and therefore, enhancing the yield of very-large-scale integrated circuits (VLSIs) effectively, for example.
Claims
1. A layout structure for a semiconductor integrated circuit including silicon-on-insulator (SOI) transistors, the structure comprising:
- a circuit block in which a plurality of cell rows, each being comprised of a plurality of standard cells arranged in a first direction, are arranged in a second direction that is perpendicular to the first direction, thereby forming a circuit of the SOI transistors, wherein
- the circuit block comprises a plurality of antenna cells, each including an antenna diode formed between a power supply line for supplying power to the circuit block and a substrate or a well, and
- in at least a part of the circuit block, the antenna cells are arranged at constant intervals in at least one of the first and second directions.
2. The layout structure of claim 1, wherein
- in a first cell row which is one of the plurality of cell rows, at least three antenna cells are arranged at constant intervals.
3. The layout structure of claim 2, wherein
- in the first cell row, the antenna cells are all arranged at constant intervals.
4. The layout structure of claim 1, wherein
- the plurality of cell rows includes at least three cell rows with the antenna cells, and
- the at least three cell rows with the antenna cells are arranged every predetermined number of cell rows.
5. The layout structure of claim 4, wherein
- the at least three cell rows with the antenna cells are arranged every other cell row.
6. The layout structure of claim 4, wherein
- in the plurality of cell rows, the cell rows with the antenna cells are entirely arranged every predetermined number of cell rows.
7. The layout structure of claim 1, wherein
- at least one of the antenna cells arranged in the circuit block is adjacent to a TAP cell having a TAP function of supplying a substrate potential.
8. The layout structure of claim 1, wherein
- the plurality of cell rows includes at least three cell rows, each of which includes an antenna cell arranged at one end thereof, and
- the at least three cell rows are arranged either consecutively or every predetermined number of cell rows.
9. The layout structure of claim 8, wherein
- each of the at least three cell rows includes antenna cells arranged at both ends thereof.
Type: Application
Filed: May 10, 2017
Publication Date: Aug 24, 2017
Inventor: Hiroyuki SHIMBO (Kyoto)
Application Number: 15/591,923