Wafer Scale Monolithic CMOS-Integration of Free- and Non-Free-Standing Metal- and Metal Alloy-Based MEMS Structures in a Sealed Cavity
An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.
Latest InSense Inc. Patents:
This application is a continuation of U.S. patent application Ser. No. 14/306,139 filed Jun. 16, 2014, the contents of which are incorporated herein by reference.
TECHNICAL FIELDEmbodiments of the invention are in the field of microelectromechanical systems (MEMS) (also called microsystems) and methods for sensing and actuation, and, in particular, inertial and magnetic field sensing without excluding resonators, chemical, environmental, biological, pressure, and temperature sensors, or multisensing platforms post-processed, i.e., directly microfabricated, on their application-specific integrated circuit (ASIC).
BACKGROUNDMEMS devices are currently pervasively used in the automotive industry and consumer electronics. However, the market for standalone MEMS devices is starting to slow down due to the demand for integrated multi-usage elements, wherein multiple MEMS devices are integrated in a single platform. An example of such integration is multi-degree-of-freedom sensors where micromachined structures, such as accelerometers, gyroscopes and magnetometersare all integrated on the same package. This is to enable smaller form factors, lower cost and lower power consumption, thereby requiring single-die integration.
However, such single-die integration is typically achieved in a hybrid fashion, wherein the die containing the MEMS devices and the application-specific integrated circuit (ASIC), which drives the devices and outputs the signals, are individually fabricated and assembled to form the desired product. The cost associated with such an approach is usually high given that the integration has to be performed at the device level rather than at the wafer level. Moreover, the size tends to be large with a lot of wiring involved.
While there have been platforms, e.g., U.S. Pat. No. 7,104,129 B2, that enable wafer scale integration between the ASIC and the MEMS devices via multiple wafer bonding, the size (especially in the Z direction) still remains large. Moreover, the noise floor from the parasitic effects, which affects the device sensitivity, can still be high. As an example, in the case of capacitive-based sensors, such as commercial accelerometers and gyroscopes, the noise floor can be important due to the parasitic capacitances related to the metallic routings that can span through a whole wafer thickness. This requires additional design considerations at the device level to take this issue into account, which causes more power consumption and bulkier devices.
Such a bottleneck can be resolved by directly fabricating the MEMS elements on the CMOS ASIC substrate. However, silicon is the main material used for the MEMS elements, whose deposition is not compatible with the required thermal budget of the CMOS ASIC substrate, which cannot withstand any process temperatures higher than 450° C. The present invention provides wafer-scale integration in a monolithic fashion through the usage of MEMS structures whose structural material can be deposited directly on the ASIC interconnect layers at temperature lower than 450° C. The subsequent microfabrication steps define the MEMS elements which are anchored to the metal interconnects, thereby providing direct electrical contact. This single chip solution enables: (1) much easier routing to implement optimized mechanical structures, (2) an extremely low cost as no wafer bonding is required, (3) smaller form factors, (4) multiple MEMS elements on a single die, (5) much smaller parasitics providing low noise and higher performance.
SUMMARYAn assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate. Moreover, the present invention provides wafer-scale processing steps for multi-device assemblies monolithically integrated with the CMOS at a much reduced cost.
An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), is described. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. In the following description, numerous specific details are set forth, such as processing steps, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
One or more embodiments are targeted towards monolithically CMOS-integrated sensors and actuators, and in particular inertial and magnetic field sensing without excluding environmental- and bio-sensing, and resonators using MEMS device elements. Embodiments may address approaches for providing compact multi-sensing and actuation platforms suitable to perform highly sensitive signal detection or actuation in a parallel fashion. Furthermore, one or more embodiments provide a cost effective and accurate system to enable wide applications of miniaturized sensors and actuators, as well as multi-sensing/actuation platforms for many industries, including consumer electronics, automotive and oil/gas industries. To provide context, conventional MEMS-based sensing technology, such as accelerometers and gyroscopes, is routinely used for motion sensing in smart phones, air-bag deployment systems, and more recently in wearable electronics and Internet of Things (IoT) applications. Such technology is usually based on standalone MEMS devices, which is starting to slow down due to the demand for integrated multi-usage elements, wherein multiple MEMS devices are integrated in a single platform. However, the total cost of such integration remains bulky, costly and power hungry, thereby restricting the use of such integrated technology. For a vulgarized usage, multi-sensing and actuation platforms need to be compact, sensitive and low power such that the overall cost is affordable.
One or more embodiments described herein are directed to the design and manufacturing of an assembly of MEMS structures post-processed, i.e., directly fabricated, on planarized CMOS substrates, containing the ASIC, by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers. Such embodiments may be implemented to significantly improve the signal to noise ratio in sensing schemes, as parasitic effects are reduced greatly, enabling higher performances. This is while achieving easier routing to: (1) implement optimized mechanical structures, (2) enable an extremely low cost as low temperature wafer bonding is required only for capping, (3) enable smaller form factors, (4) multiple MEMS elements on a single die.
To provide further context, it is to be appreciated that a number of problems may be associated with existing integration platforms. First, these platforms require multi-substrate bonding at the die level with excessive wiring, engendering bulky and costly systems. Second, the excessive wiring engenders parasitics that affect the device performances (i.e., providing high noise) and increase power consumption. Past approaches (e.g., U.S. Pat. No. 7,104,129 B2) that enable wafer scale integration between the ASIC and the MEMS devices still use multiple wafer bonding, i.e., the size (especially in the Z direction) still remains large. Moreover, the noise floor from the parasitic effects can still be high due the metallic routings used. This requires additional design considerations at the device level to take this issue into account, which causes more power consumption and bulkier devices. In addition, the required recess on the CMOS ASIC wafer constrains further chip scaling.
In a first aspect, in accordance with an embodiment of the present invention,
A cap 116 is wafer-bonded to the CMOS ASIC 100 via bond-pads 108 directly fabricated on the CMOS ASIC on the last interconnect layer. The lateral and vertical dimensions of the cap 116 are defined by the range of motion of the MEMS structures 112 and 114 and should be large enough to allow them to move in-plane (i.e., laterally) or out-of-plane (i.e., vertically) with enough motion to perform their desired function. These dimensions are defined by lithography and subsequent microfabrication processes. In the case of out-of-plane motion, driving electrodes can also be fabricated and incorporated on the last interconnect layer. The MEMS structures 112 and 114 which define the device elements can be as many as possible, and can embody a single device, such as a sensor or an actuator, or as many devices as possible that embody a multi-sensing platform, a multi-actuation platform or a combination of both. As an example, MEMS structures 112 and 114 can be an accelerometer and a gyroscope directly fabricated on the CMOS ASIC substrate 100. Moreover, the MEMS structures 112 and 114 can have a thickness ranging from O to 300 micrometers.
Depending on the function of the MEMS elements, different pressure levels, within the cavity formed by the cap 116, are required to attain optimal operational conditions. While some require a high vacuum, e.g., capacitive-based gyroscopes with high quality factor and low noise, others require near atmospheric pressure, e.g., capacitive-based accelerometers in order to increase the squeeze-film damping effect that can prevent device overshoot and long settling times. Therefore, the cavity can be hermetically sealed at low pressures or maintained at elevated pressures using inert gases such as nitrogen, helium or argon, or dry air.
In the case where different device elements post-processed on the same CMOS ASIC substrate, require a different operational pressure, and in accordance with an embodiment of the present invention, numerous cavities with different pressures can be achieved.
In the case where some of the MEMS device elements post-processed on the same CMOS ASIC substrate, require ambient exposure, i.e., without a cap, but with a gap between two structures which is maintained at a certain pressure (ambient or otherwise), and in accordance with yet another embodiment of the present invention, the cap is lithographically defined to cover only the MEMS device elements that require it.
In the case where some of device elements post-processed on the same CMOS ASIC substrate, require a back access in the CMOS ASIC substrate for their operation, and in accordance with yet another embodiment of the present invention, part of the CMOS ASIC substrate can be etched through the whole thickness to provide such access.
In accordance with an embodiment of the present invention, a new fabrication process is described for post-processing the MEMS structures on the CMOS ASIC substrate. The resulting fabricated structures, with or without movable parts, may be utilized for sensing and actuation. More generally, one or more embodiments described herein provide a unique combination of using MEMS device elements monolithically integrated on their respective CMOS ASIC for sensing and actuation.
Referring to
Referring to
Referring to
The process steps of
In the case the MEMS elements require a back access within the CMOS ASIC substrate 1200 as in
It is to be appreciated that other process fabrication schemes can also be pursued as shown in
In this case, a sacrificial layer 1402 is deposited and then patterned to open up the access to the interconnects 1404, as shown in
It is to be appreciated that the cap can be further processed to form through-thickness holes that would be filled with TSVs to form a structure similar to
It is to be also appreciated that other process fabrication schemes for the cap can also be pursued, especially when the main capping material is deposited using PVD, CVD, electro- or electroless-plating, as shown in
Referring to
The cap can also be monolithically integrated by processing it simultaneously with, and thus using the same structural material as, the MEMS elements.
A similar process to that described in
It is to be appreciated that in the case the structural material can corrode, such as, but not limited to, Cu, W, Ti, a protective layer can be deposited. This layer can also act as a diffusion barrier to these structural materials. An example of such a layer could consist, but is not limited to, TiN, TaN, AlN, Pt, Ru, Ta, In203, Sn02, or ITO. This can be accomplished using ALD, CVD, or PVD as in the case of sputtering. The thickness of this layer can range from 0 to 1000 nanometers. It is also to be appreciated that a seed layer might be needed in the case of a plating process, which can be deposited using PVD or CVD processes.
For all aspects described above, in an embodiment, the resulting structures can be utilized to provide compact multi-sensing and actuation platforms suitable to perform highly sensitive signal detection or actuation in a parallel fashion. In one such embodiment, a sensor COMBO in which each sensor is used to detect different motions, with high signal to noise ratio, associated with a larger device in which the sensing platform is compactly housed. In general, embodiments described herein may be suitable for a variety of implementations involving high sensitivity electromechanical sensors with or without movable parts, as well as actuators.
While inertial sensors are the preferred application, the embodiments of the present invention can be applied to other MEMS devices such as resonators, switches, optical devices, etc.
As used herein, a “sensor” refers to a substance or device that detects or senses an electrical signal created by movement of electrons, including but not limited to electrical resistance, current, voltage and capacitance. That is, the sensor can detect signals in the form of current, or detect voltage, or detect charge, or impedance or magnetic field, or a combination thereof. A multi-sensor array has one or more sensors integrated on a single chip.
Thus, embodiments of the present invention include the post-processing of MEMS device elements directly on the CMOS ASIC substrate with capping.
In an embodiment, the MEMS device elements, can be sensors or an actuators, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The non-movable parts can be embedded within the interconnect layers.
In one embodiment, the MEMS device elements require two closely spaced structures, one movable and another non movable, with a gap maintained at a certain pressure, ambient or otherwise.
In one embodiment, the MEMS device elements require a back etch of the CMOS ASIC substrate for their operation.
In one embodiment, the main structural material of the MEMS device elements is selected from the group consisting of metals and metal alloys, conductive metal oxides and amorphous semiconductors including, but not limited to, Cu, Al, Ag, Ti, W, Au, Pt, Pd, Ru, Ni, Co, Cd, Pb, Zn, amorphous silicon, Cadium Zinc Telluride (CZT), HfB2, In03, Sn02, Indium Tin Oxide (ITO), or a combination of a few.
In one embodiment, the structural material can be deposited directly on the ASIC interconnects at or below 450 C using deposition techniques including, but not limited to, electroplating, electroless-plating, physical vapor deposition (such as sputtering, thermal and e-beam evaporation), chemical vapor deposition, atomic layer deposition, physical layer deposition.
In one embodiment, the material density is very high, e.g., Cu density of 8900 kg/m3 or W density of 19800 kg/m3 compared to Si density of 2329 kg/m3, enabling much more compact and thinner structures.
In one embodiment, the main structural material has a thickness approximately in the range of 0-100 micrometers.
In one embodiment, the movable parts of the MEMS device elements can move in-plane or out-of-plane, i.e., vertical motion, with driving electrodes fabricated and incorporated on the last interconnect layer of the ASIC for the latter case.
In one embodiment, methods of fabricating a monolithically CMOS integrated MEMS device elements with capping, are defined.
In one embodiment, the methods of fabrication can be vertically repeated multiple times to build multiple layers of MEMS structures, whereby each MEMS layer has a different geometrical shape to enable 3D assembly of MEMS structures on ASIC in a monolithic fashion.
In one embodiment, a thin protective material, selected from the group consisting of, but not limited to, TaN, TiN, AlN, Pt, Ru, Ta, Ta205, In203, Sn02, ITO, Ti02, Si02, Y203, Ah03, Hf02, Zr02, ZrSi04, BaTi03, BaZr03, Teflon, or other organic materials, is selectively deposited around all exposed surfaces of the main structural material to protect it from oxidizing or corroding during its operational use, and thus improving the stability of the device elements and preventing any drift.
In one embodiment, the bonding pads are defined in the post-processing on the CMOS ASIC substrate, which could be routed to the ground interconnects of the device assembly, to enable the bonding of a cap, thereby creating a hermetically, or non-hermetically, sealed cavity.
In one embodiment, the cap can be lithographically defined to form separate cavities, equal to or larger than 2, once bonded to the CMOS ASIC substrate through different bond-pads, where different pressures can be achieved.
In one embodiment, the cap can be post-processed simultaneously with the MEMS structures using the same structural material.
Claims
1. A method, comprising:
- forming a CMOS ASIC with an ASIC interconnect layer including first metallic interconnects to receive MEMS device input signals, contact pads for ASIC processed output signals, and a cap bonding pad;
- depositing a first mold layer on the ASIC interconnect layer;
- forming a first lithographic pattern on the first mold layer;
- etching the first lithographic pattern to form a first etched surface with MEMS anchor windows exposing the first metallic interconnects;
- electroplating copper on the first etched surface to form a first electroplated copper surface;
- planarizing the first electroplated copper surface to the first mold layer to render electroplated copper anchor structures in the MEMS anchor windows;
- depositing a second mold layer on the first mold layer;
- forming a second lithographic pattern on the second mold layer;
- etching the second lithographic pattern to form a second etched surface with first MEMS feature windows;
- electroplating copper on the second etched surface to form a second electroplated copper surface;
- planarizing the second electroplated copper surface to the second mold layer;
- etching the second mold layer to expose electroplated copper MEMS features;
- forming a copper substrate;
- forming a film on a first surface of the copper substrate;
- forming a third lithographic pattern on the film;
- etching the third lithographic pattern to expose a cap outline;
- etching the copper substrate to form a cap with a cap recess within the cap outline; and
- attaching the cap to the cap bonding pad such that the electroplated copper MEMS features reside within the cap recess.
2. The method of claim 1 wherein the cap is formed from a material selected from semiconductors, metals, metal alloys, metal oxides and dielectrics, including, Si, Cu, Ti, W, Al, Ag, Pt, Pd, Ru, HfB2, Indium Tin Oxide (ITO), SiO2, quartz, sapphire, or a combination of a thereof.
3. The method of claim 1 wherein the cap is defined through at least one of lithography, etching and grinding.
4. The method of claim 1 wherein the cap is further processed to form through-thickness holes to host through silicon vias (TSVs).
5. The method of claim 4 wherein the TSVs are in contact with the contact pads of the CMOS ASIC substrate after the final bonding.
6. The method of claim 1 further comprising forming an adhesion layer between the cap and the substrate.
7. The method of claim 1 wherein pressure in the cap recess is determined by the pressure at attaching the cap is performed.
8. The method of claim 1 wherein the electroplating is performed after depositing and patterning the second mold layer on the first mold layer to simultaneously form the MEMS anchor and main features.
9. A method, comprising:
- forming a CMOS ASIC with an ASIC interconnect layer including first metallic interconnects to receive MEMS device input signals, contact pads for ASIC processed output signals, and a cap bonding pad;
- depositing a first mold layer on the ASIC interconnect layer;
- forming a first lithographic pattern on the first mold layer;
- etching the first lithographic pattern to form a first etched surface with MEMS bottom electrode windows and MEMS top electrode anchor windows exposing the first metallic interconnects;
- electroplating copper on the first etched surface to form a first electroplated copper surface;
- planarizing the first electroplated copper surface to the first mold layer to render electroplated copper bottom electrode anchor structures and electroplated copper top electrode anchor structures in the MEMS bottom electrode windows and MEMS top electrode anchor windows;
- depositing a second mold layer on the first mold layer;
- forming a second lithographic pattern on the second mold layer;
- etching the second lithographic pattern to form a second etched surface with first MEMS top electrode feature windows;
- electroplating copper on the second etched surface to form a second electroplated copper surface;
- planarizing the second electroplated copper surface to the second mold layer;
- etching the second mold layer to expose electroplated copper MEMS top electrode features.
10. The method of claim 9 wherein the second electroplated copper surface includes MEMS anchor features and MEMS main features.
11. The method of claim 9 wherein the electroplated copper MEMS top electrode features include at least one hole to facilitate processing of features beneath a cap ceiling.
12. The method of claim 11 further comprising sealing the at least one hole to form a sealed cavity.
13. The method of claim 12 wherein sealing is performed using at least one of PVD, CVD electro deposition and electro-less deposition.
14. The method of claim 12 wherein sealing is performed using a material selected from semiconductors, metals, metal alloys, metal oxides and dielectrics, including, but not limited to Cu, Al, Ag, W, Pt, Pd, Ru, Co, Cd, Pb, Zn, Cadium Zinc Telluride (CZT), HfB2, In2O3, SnO2, Indium Tin Oxide (ITO) or a combination thereof.
15. The method of claim 12 wherein pressure in the sealed cavity is determined by the pressure at which sealing is performed.
Type: Application
Filed: Apr 6, 2017
Publication Date: Sep 28, 2017
Applicant: InSense Inc. (Palo Alto, CA)
Inventors: Noureddine Tayebi (Palo Alto, CA), Hao Luo (Milpitas, CA)
Application Number: 15/481,315