SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.
1. Field of the Invention
The present invention relates to a semiconductor device and method of forming the same, and more particularly, relates to FinFET semiconductor device with fine lattice structure and method of forming the same.
2. Description of the Prior Art
In recent years, as various kinds of consumer electronic products are being constantly modified towards increased miniaturization, the size of semiconductor components are modified to be reduced accordingly, in order to meet high integration, high performance, low power consumption, and the demands of products.
However, with the increasing miniaturization of electronic products, current planar FETs no longer meet the requirements of the products. Thus, non-planar FETs such as Fin-shaped FETs (Fin-FET) have been developed, which includes a three-dimensional channel structure. The manufacturing processes of Fin-FET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the Fin-FET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased. In current years, the development of the Fin-FETS is still aiming to devices with smaller scales.
SUMMARY OF THE INVENTIONThe present invention therefore provides a FinFET semiconductor device with fine lattice structure and method of forming the same.
According to one embodiment, the present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed between two STIs. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.
According to another embodiment, the present invention provides a method of forming a semiconductor device. First, a substrate including a first region is provided, wherein the first region is disposed between two shallow trench isolations (STI). A first semiconductor layer is formed in the first region. Next, a patterned mask layer is formed on the first semiconductor layer, following by using the patterned mask layer as a mask to pattern the first semiconductor layer, thereby forming a plurality of first sub recesses. Then, a plurality of first fin structures are formed in the first sub recesses, and the patterned mask layer is removed to a predetermined height so the patterned mask layer becomes a plurality of insulation structures, wherein the insulation structures are arranged alternatively with the first fin structures.
Based on the semiconductor device and the method set forth in the present invention, which is characterized by using the semiconductor layer as a buffer layer, the formed fin structures can have good lattice structure and no fin cut process is required.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
To provide a better understanding of the presented invention, preferred embodiments will be made in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
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Since the present invention uses epitaxial growth process to form the first semiconductor layer 404, the second semiconductor layer 504, the first top semiconductor layer 408 (later becomes the first fin structure 408′) and the second top semiconductor layer 508 (later becomes the second fin structure 508′), the first semiconductor layer 404 and the second semiconductor layer 504 can serve as a buffer layer for lattice growth, which may have a small number of dislocations, but making the first fin structures 408′ and the second fin structures 508′ exhibit good lattice property without dislocations. In one embodiment, the first semiconductor layer 404 and the first fin structures 408′ formed from the first top semiconductor layer 408 have different lattice coefficients (lattice mismatch). In another embodiment, the first semiconductor layer 404, the first fin structures 408′ and the substrate 300 have different lattice coefficients (lattice mismatch). In one embodiment, if the first region 400 is an N type region, the first semiconductor layer 404, the second semiconductor layer 504, the first fin structures 408′ and the second fin structures 508′ may include silicon, silicon germanium, germanium, arsenic, or other IV elements. Preferably, in order to increase the channel stress of the fin structures, the first semiconductor layer 404 or the second semiconductor layer 504 may be doped with IV elements with different atomic sizes, such as carbon (C) or tin (Sn), and its concentration may have gradient depending on the designs of the products.
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The semiconductor device with the first fin structures 408′ and the second fin structures 508′ formed by the method of the present invention can be subjected to other semiconductor processes, for instance, forming a gate dielectric layer (not shown) and a gate layer (not) on the fin structures and then forming a source/drain region, thereby forming a transistor. Alternatively, the method can be in conjugation with other transistor formation process, such as a metal replacement gate process. Please refer to
In summary, according to the semiconductor device and the method set forth in the present invention, which is characterized by using the semiconductor layer as a buffer layer, the formed fin structures can have fin lattice structure and no fin cut process is required.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A semiconductor device, comprising:
- a substrate, having a first region, wherein the first region is disposed between two shallow trench isolations (STI);
- a first semiconductor layer, disposed in the first region, wherein a depth of the first semiconductor layer is less than depths of the STIs;
- a plurality of first sub recesses, disposed in the first semiconductor layer;
- a plurality of insulation structures, disposed on the first semiconductor layer; and
- a first top semiconductor layer, comprising a plurality of first fin structures, which are embedded in the first sub recesses and arranged alternatively with the insulation structures, wherein the first fin structures protrude from the insulation structures.
2. The semiconductor device according to claim 1, wherein a depth of the first semiconductor layer is greater than a depth of the first sub recess.
3. The semiconductor device according to claim 1, wherein a top surface of the first semiconductor layer is leveled with a top surface of the STI.
4. The semiconductor device according to claim 1, further comprising at least one dielectric dummy fin structure disposed on the STI.
5. (canceled)
6. The semiconductor device according to claim 4, further comprising a metal gate disposed on the first fin structures and partially overlapping with the dielectric dummy fin structure.
7. The semiconductor device according to claim 1, further comprising a first middle semiconductor layer disposed between the first semiconductor layer and the insulation structures.
8. The semiconductor device according to claim 7, wherein a top surface of the first middle semiconductor layer is leveled with a top surface of the STI.
9. The semiconductor device according to claim 7, wherein a boundary between the first middle semiconductor layer and the first semiconductor layer is higher than a top surface of the first fin structure.
10. The semiconductor device according to claim 1, wherein the substrate further comprises a second region, which is surrounded by the STI and separated from the first region.
11. The semiconductor device according to claim 10, further comprising:
- a second semiconductor layer, disposed in the second region;
- a plurality of second sub recesses, disposed in the second semiconductor layer;
- the insulation structures, disposed on the second semiconductor layer; and
- a second top semiconductor layer, forming a plurality of second fin structures, which are embedded in the second sub recesses and arranged alternatively with the insulation structures, wherein the second fin structures protrude from the insulation structures.
12. The semiconductor device according to claim 11, wherein a depth of the second sub recess is different from a depth of the first sub recess.
13. The semiconductor device according to claim 11, wherein a width of the second sub recess is different from a width of the first sub recess.
14. The semiconductor device according to claim 11, wherein the first semiconductor layer has dislocation.
15. The semiconductor device according to claim 1, wherein there are lattice mismatch between the first semiconductor layer and the first top semiconductor layer.
16. The semiconductor device according to claim 1, wherein there are lattice mismatch between the first semiconductor layer, the first top semiconductor layer and the substrate.
17. A method of forming a semiconductor structure, comprising:
- providing a substrate including a first region, wherein the first region is disposed between two shallow trench isolations (STI);
- forming a first semiconductor layer in the first region, wherein a depth of the first semiconductor layer is less than depths of the STIs;
- forming a patterned mask layer on the first semiconductor layer;
- patterning the first semiconductor layer by using the patterned mask layer as a mask, thereby forming a plurality of first sub recesses in the first semiconductor layer;
- forming a plurality of first fin structures in the first sub recesses; and
- removing the patterned mask layer to a predetermined height so the patterned mask layer becomes a plurality of insulation structures, wherein the insulation structures are arranged alternatively with the first fin structures.
18. The method of forming a semiconductor structure according to claim 17, wherein the patterned mask layer covers at least one boundary between the first region and the STI.
19. The method of forming a semiconductor structure according to claim 17, wherein the step of forming the first semiconductor layer comprises a selective epitaxial growth (SEG) process.
20. The method of forming a semiconductor structure according to claim 17, wherein the step of forming the first fin structures comprises a selective epitaxial growth (SEG) process.
21. A semiconductor device, comprising:
- a substrate, having a first region, wherein the first region is disposed between two shallow trench isolations (STI);
- a first semiconductor layer, disposed in the first region, wherein the first semiconductor layer is an epitaxial layer;
- a plurality of first sub recesses, disposed in the first semiconductor layer;
- a plurality of insulation structures, disposed on the first semiconductor layer; and
- a first top semiconductor layer, comprising a plurality of first fin structures, which are embedded in the first sub recesses and arranged alternatively with the insulation structures, wherein the first fin structures protrude from the insulation structures.
Type: Application
Filed: May 12, 2016
Publication Date: Sep 28, 2017
Inventor: Yu-Cheng Tung (Kaohsiung City)
Application Number: 15/152,570