Patents by Inventor Yu-Cheng Tung

Yu-Cheng Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031389
    Abstract: A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.
    Type: Application
    Filed: November 13, 2023
    Publication date: January 23, 2025
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Bingxing Wu, Jung-Hua Chen, Wei-Ming Hsiao, Yu-Cheng Tung, Qiangwei Xu
  • Patent number: 12200923
    Abstract: The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: January 14, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Publication number: 20250016982
    Abstract: A semiconductor structure includes a substrate, a first bottom electrode and a second bottom electrode disposed on the substrate, an upper supporting layer extending laterally between the first bottom electrode and the second bottom electrode and directly contacting the first bottom electrode and the second bottom electrode, a cavity between the upper sacrificial layer and the substrate, a capacitor dielectric layer covering along the first bottom electrode and the second bottom electrode, and a conductive material disposed on the capacitor dielectric layer. A portion of the first bottom electrode has a slope profile having a lower end not lower than a lower surface of the upper supporting layer.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Publication number: 20240421184
    Abstract: In a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, conductive layer structures, plug structures, spacers and stop layers. The plug structures are disposed between two of the conductive layer structures in a second direction perpendicular to the first direction. The spacers are disposed between the conductive layer structures and the plug structures. The stop layers are disposed on the spacers between the conductive layer structures and the plug structures and has a bottommost surface disposed between a bottom surface of the conductive layer structures and a bottom surface of the spacers. The plug structures comprise at least one protrusion member extending from the bottommost surface toward the conductive layer structure and disposed between the stop layer and the substrate. Accordingly, contact area between the plug structures and the substrate can be increased.
    Type: Application
    Filed: November 22, 2023
    Publication date: December 19, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Yu-Cheng Tung, Hsi-Chih Li, Tsung-Yi Wu
  • Publication number: 20240421222
    Abstract: A semiconductor device includes a substrate. A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially disposed on the substrate. A source structure is formed in the first dielectric layer. A drain structure is formed in the third dielectric layer. A channel structure extends through the second dielectric layer and directly contacts the source structure and the drain structure. A gate structure is disposed at two sides of the channel structure. The gate structure includes a conductive layer and a gate dielectric layer. The gate dielectric layer is along sidewalls and a bottom surface of the conductive layer, and is interposed between the conductive layer and the channel structure and the second dielectric layer.
    Type: Application
    Filed: October 3, 2023
    Publication date: December 19, 2024
    Inventors: Chia-Wei Wu, Yu- Cheng Tung
  • Publication number: 20240395605
    Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Patent number: 12156399
    Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: November 26, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Huixian Lai, Yi-Wang Jhan
  • Patent number: 12150291
    Abstract: A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: November 19, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Yu-Cheng Tung
  • Publication number: 20240381629
    Abstract: A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrally-formed contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng TUNG, Shaoyi Wu, Xiaoyan Chen
  • Publication number: 20240381617
    Abstract: A semiconductor device includes a substrate, a connecting layer on the substrate, and a capacitor structure arranged on the connecting layer. The connecting layer includes an array of connecting pads, a peripheral structure adjacent to the array of connecting pads, and a plurality of first extending pads arranged between the peripheral structure and the array of connecting pads. The connecting pads respectively have one of the bottom electrodes of the capacitor structure disposed thereon. The first extending pads respectively have two of the bottom electrodes of the capacitor structure disposed thereon to reinforce the peripheral portions of the capacitor structure.
    Type: Application
    Filed: September 18, 2023
    Publication date: November 14, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Patent number: 12133373
    Abstract: A method for forming a semiconductor structure includes providing a substrate, forming an upper sacrificial layer, an upper supporting layer and a hard mask layer on the substrate, forming bottom electrodes through the upper sacrificial layer, the upper supporting layer and the hard mask layer, forming at least an opening between the bottom electrodes and through the hard mask layer and the upper supporting layer to partially expose the upper sacrificial layer. A portion of at least one of the bottom electrodes exposed from the opening has a slope profile, and a lower end of the slope profile is not lower than a lower surface of the upper supporting layer. The method further includes removing the upper sacrificial layer from the opening to form a cavity, and forming a capacitor dielectric layer along the bottom electrodes and a conductive material filling the cavity.
    Type: Grant
    Filed: October 3, 2023
    Date of Patent: October 29, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Patent number: 12114487
    Abstract: The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: October 8, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Patent number: 12100617
    Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: September 24, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Publication number: 20240298436
    Abstract: A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a semiconductor substrate, bit line structures, isolation structures, a storage node contact structure, and first voids. The bit line structures, the isolation structures, and the storage node contact structure are disposed on the semiconductor substrate. Each bit line structure extends in a first direction, and the bit line structures are arranged in a second direction. The isolation structures are located between the bit line structures adjacent to one another. The storage node contact structure is located between two adjacent bit line structures and located between two adjacent isolation structures in the first direction. The storage node contact structure includes four corner portions. The first voids are disposed in the storage node contact structure, and the first voids are located in at least two of the four corner portions.
    Type: Application
    Filed: March 31, 2023
    Publication date: September 5, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Patent number: 12075609
    Abstract: A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrated contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 27, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Yi-Wang Jhan, Yung-Tai Huang, Xiaopei Fang, Shaoyi Wu, Yi-Lei Tseng
  • Patent number: 12068316
    Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: August 20, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wang Jhan, Fu-Che Lee, Huixian Lai, Yu-Cheng Tung, An-Chi Liu, Gang-Yi Lin
  • Patent number: 12062689
    Abstract: A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: August 13, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Wei Wu, Yu-Cheng Tung
  • Publication number: 20240244824
    Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.
    Type: Application
    Filed: January 31, 2024
    Publication date: July 18, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ken-Li Chen, Yifei Yan, Yu-Cheng Tung
  • Publication number: 20240244818
    Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, which includes a substrate, a plurality of bit lines, a plurality of first plugs, a first spacer, a second spacer, a plurality of second plugs and a metal silicide layer. The bit lines are disposed on the substrate. The first plugs are disposed on the substrate and separated from the bit lines. The first spacer and the second spacer are disposed between each of the bit lines and the first plugs, and include a first height and a second height respectively. The second plugs are disposed on the first plugs respectively, and the metal silicide layer is disposed between the first plugs and the second plugs, wherein an end portion of the metal silicide layer is clamped between the second spacer and the first spacer.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Publication number: 20240237329
    Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and the semiconductor device includes a substrate, a capacitor structure, a supporting structure and a supplementary layer. The capacitor structure is disposed on the substrate, and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The supporting structure is disposed between adjacent ones of the columnar bottom electrodes, and the supporting structure includes a first supporting layer and a second supporting layer stacked from bottom to top. The supplementary layer is disposed between each of the columnar bottom electrodes and the supporting structure, to directly in contact with the first supporting layer, the second supporting layer, and sidewalls of the columnar bottom electrodes.
    Type: Application
    Filed: June 20, 2023
    Publication date: July 11, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang