Patents by Inventor Yu-Cheng Tung

Yu-Cheng Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020742
    Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.
    Type: Application
    Filed: December 11, 2019
    Publication date: January 21, 2021
    Inventors: Yu-Cheng TUNG, Yun-Fan CHOU, Te-Hao HUANG, Hsien-Shih CHU, Feng-Ming HUANG
  • Patent number: 10879378
    Abstract: Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10861673
    Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ying Sun, En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10840182
    Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate is provided and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: November 17, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10825817
    Abstract: A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 3, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • Patent number: 10818660
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 10790202
    Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10777556
    Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10763264
    Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
  • Patent number: 10763175
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20200257192
    Abstract: A method for correcting a mask pattern includes: providing an original mask pattern including at least one dense pattern area and at least one isolated pattern area, and the original mask pattern being divided into a first pattern and a second pattern, wherein the first pattern is formed in the isolated pattern area and extends to the dense pattern area, and the second pattern is formed in the dense pattern area; forming at least one slot on at least one section of the first pattern, and the at least one section of the first pattern is located on at least one transition area between the at least one isolated pattern area and the at least one dense pattern area; and performing an optical proximity correction operation on the first pattern formed with at least one slot and the second pattern. Using the corrected mask pattern may avoid the occurrence of necking or breaking on portion of the post-transfer pattern.
    Type: Application
    Filed: February 11, 2019
    Publication date: August 13, 2020
    Inventors: Chia-Chen SUN, Yu-Cheng TUNG, Sheng-Yuan HSUEH, Fan Wei LIN
  • Publication number: 20200194252
    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and a surface portion formed on the blocking layer.
    Type: Application
    Filed: January 8, 2019
    Publication date: June 18, 2020
    Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
  • Publication number: 20200185511
    Abstract: Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Applicant: United Microelectronics Corp.
    Inventors: EN-CHIUAN LIOU, Yu-Cheng Tung
  • Publication number: 20200185391
    Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A contact hole is formed on a memory cell region of a semiconductor substrate and exposes a part of the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on a memory cell region of the semiconductor substrate. A second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. A contact structure is formed in the contact hole, and the contact structure is located between the bit line metal structure and the semiconductor substrate.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Li-Wei Feng, Yu-Cheng Tung
  • Patent number: 10670958
    Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n?1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Yu-Cheng Tung, Li-Wei Feng, Chien-Ting Ho
  • Patent number: 10663853
    Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20200126965
    Abstract: A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventor: Yu-Cheng Tung
  • Patent number: 10629748
    Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pengfei Guo, Shao-Hui Wu, Hai Biao Yao, Yu-Cheng Tung, Yuanli Ding, Zhibiao Zhou
  • Publication number: 20200118812
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 16, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yu-Cheng Tung
  • Patent number: 10600790
    Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: March 24, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Yu-Cheng Tung