PIPELINED CASCADED DIGITAL SIGNAL PROCESSING STRUCTURES AND METHODS
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
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This invention relates to circuitry that can be used to implement pipelined cascaded digital signal processing (DSP) structure to reduce propagation latency between DSP structures.
BACKGROUND OF THE INVENTIONIn a large scale digital circuit such as, but not limited to, a Field-Programmable Gate Array (FPGA) or an application-specific integrated circuit (ASIC), a number of DSP structures often work together to implement complex tasks. To achieve improved performance, these DSP structures are often operated at high speeds. While FPGA speed, or alternatively the ASIC processing speed, has been improved, one constraint is the propagation delay of signals between two DSP structures, especially when a random routing distance between the two DSP structures is encountered, which can be introduced by row based redundancy. For example, when a number of DSP structures or blocks are connected in a systolic mode to improve system throughput, one of the challenges in operating 1 GHz FPGA is the efficiency of interconnection between DSP blocks. Once the 1 GHz DSP block has been designed, multiple DSP blocks are connected together to create a single structure, and operated at a high speed, for example, 1 GHz in a single structure, and thus efficient interconnection between the blocks is desired to improve multi-block performance.
One method for improving performance in this case would be to add pipeline stages between the DSP structures. Pipelining techniques can be used to enhance processing speed at a critical path of the DSP structure by allowing different functional units to operate concurrently. Pipelined systolic structures, however, may not operate correctly, as the enable flow can be disturbed at times. Thus, summing of values across DSP structures can yield an inaccurate result, as the pipeline depths are no longer balanced. Additional balancing registers can be added to balance the delays, which can incur additional hardware and logic cost.
SUMMARY OF THE INVENTIONIn accordance with embodiments of the present invention, several architectures for interblock registering to improve multi-block performance are presented.
Therefore, in accordance with embodiments of the present invention there is provided circuitry accepting a data input and generating a data output based on said data input. The circuitry includes a first circuit block, which further includes a first multiplier circuit, a first plurality of pipeline registers disposed to pipeline an operation of the first multiplier circuit, a first adder circuit accepting a first adder input from within the first circuit block, and a second adder input from a first interblock connection. The circuitry further includes a second circuit block cascaded to the first circuit block via the first interblock connection, which includes a second multiplier circuit, and a second plurality of pipeline registers disposed to pipeline an operation of the second multiplier circuit. One or more of the second plurality of pipeline registers are selectively bypassed to balance the first adder input and the second adder input.
In accordance with other embodiments of the present invention, there is provided circuitry accepting a data input and generating an output sum based on said data input. The circuitry includes a first systolic FIR structure that has a first adder circuit and a first ripple enable register placed before the first adder circuit. The first FIR structure is retimed by the first ripple enable register to allow additional pipelines to be added throughout the first systolic FIR structure. The circuitry further includes a second systolic FIR structure, connected to the first systolic FIR structure via an interblock connection. A first cascading pipeline register connects the first systolic FIR structure and the second systolic FIR structure.
In accordance with another embodiment of the present invention, there is provided circuitry operating under a floating-point mode or a fixed-point mode. The circuitry includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode. For example, the connection configuration for the cascade register can be a selectable connection that allows the cascade register to be selectively bypassed.
In accordance with another embodiment of the present invention there is provided a method of operating cascaded circuitry. The method includes receiving, via a plurality of input registers within a first circuit, a data input signal. The first circuit includes a first arithmetic element that supports floating-point operation, a plurality of pipeline registers that pipeline an operation of the first arithmetic element, and a cascade register that is connected to a second circuit. The method further includes receiving, from a processor, a first command signal to use the cascade register. In response to the first command signal, the circuitry selectively bypasses an input register from the plurality of input registers, or a pipeline register from the plurality of pipeline registers to compensate for a delay from the cascade register. The circuitry then transmits, via the cascade register, an interblock data signal from the first circuit to the second circuit.
Further features of the invention, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
Unless otherwise indicated, the discussion that follows will be based on an example of a programmable integrated circuit device such as an FPGA. However, it should be noted that the subject matter disclosed herein may be used in any kind of fixed or programmable device, including, but not limited to, an application-specific integrated circuit (ASIC).
In some embodiments of the present invention, when multiple DSP blocks are cascaded to perform a series of tasks in a large system, pipelines can be reused in the cascaded set of DSP structures in an FPGA to provide interblock registering and thus improve system performance. Signals can be rerouted within the DSP structures to use existing pipeline registers in the structure, without introducing additional registers to save hardware. For example, systolic finite impulse response (FIR) filters can use configurable pipeline registers between DSP structures, as illustrated in
As shown in
Continuing on with the pipelined DSP block 300, while multiple such blocks are cascaded, the path lengths of the connections between the DSP blocks can become the critical path to add pipelines when implementing a high performance system.
For example, when a large number of pipeline register(s) 322 are added, the throughput of the DSP blocks 300a-b increase, but with the additional register delay incurred by the pipelines, the latency may increase. In some implementations, when a device or system that employs the DSP blocks 300a-b determines the system throughput and or speed has reached a desirable level, the device or system can selectively bypass one or more pipeline registers 322 to reduce latency.
The multiplier pipeline has an input register stage 605, two internal register stages 606, and a register stage 607 between it and the following floating-point adder. One of the supported modes, the recursive-vector mode, takes the floating-point multiplier 601 output and routes it to the next DSP block through a bus directly into the adjacent DSP block (e.g., to the right of block 600, not shown in
The overall pipeline depth of both the fixed and floating-point modes can be preserved by providing a cascade register 701 on the output of the DSP block 700 before routing to the next DSP block. Adding register 701 can be more efficient than adding another register into the multiplier pipeline 606 because it only has to be used for the floating-point chaining, and the higher speed fixed-point data may not need to pass through it. Since under the fixed-point mode, data is usually transmitted in a 64-bit format, and the floating-point mode has 32 bits, processing efficiency is improved while the fixed-point data can skip one or more registers in the pipeline. When the register 701 is chosen to be used, the recursive-vector mode case by another input register 703 on the floating-point adder path may need to be balanced for such that the two input paths of the adder in block 700 have equal or substantially equal register delays. In this example, register 702 is added, and is used by the slower floating-point path, but the faster fixed-point data may not need to use it.
In each of the blocks 150a-b, adder input registers 104a-105a and 104b-105b connect to the adder 106a-b, respectively. The register 104a accepts the multiplication result from the multiplier in the same DSP block and the other register 105a accepts the multiplication result from the multiplier in the adjacent DSP block. For example, the register 104a in DSP block 150a is connected to multiplier pipeline 101a of block 150a, and register 105a in DSP block 140a is connected to multiplier pipeline 101b of block 150b. Output of the adder 106a is passed through an output register 107a that produces the DSP block output signal 117a.
The interblock connection 110 can be used to implement one stage of a recursive-vector mode. In DSP block 150b, even when the last register 123 of pipelines 101 has no logic between itself and register 105 of the adjacent block 150a, the long routing path may still be the critical path in the vector mode, especially considering the impact of redundancy (as further discussed in connection with
As shown in
In the respective example, the shadow register 201 may only be used when the floating-point mode is invoked; and in the fixed-point interblock modes, data can be directly routed without passing through the shadow register 201. As previously discussed in connection with
In DSP block 180a, adder input balancing path 103a can have the same number of pipeline stages as the floating-point multiplier pipeline 101a, e.g., 4 pipelines in this respective example. In DSP block 180b, the adder 106b is fed by input 210b of DSP block 180b and input 210c of DSP block 180c, in this example 4 stages. By bypassing one of the balancing registers 103c (e.g., see bypassed register 156) in DSP block 180c, cascade register 201c can be used in DSP block 180c along the input path for input 210c to cause the delays from input paths 210B and 210c to be substantially equal. In this way, when a device that employs the DSP blocks 180a-c selectively bypasses one or more register, power consumption efficiency can be improved. For example, the connection configuration for the balancing registers can be a selectable connection that allows one or more balancing registers to be selectively bypassed.
As shown in
For example, if the DSP block is operated under a fixed-point mode 506a, the processor instructions 503a control the DSP block to bypass a cascade register (step 507) and then transmit interblock data directly from the respective DSP block to a cascaded block (step 509).
In an alternative example, if the DSP block is operated under a floating-point mode 506b, the processor instructions 503a control the DSP block to use the cascade register to transmit interblock data to a cascaded block (step 508), and selectively bypass a pipeline register or an input register within the DSP block to balance the cascade register (step 510). Further example structures on bypassing pipeline registers or input registers without introducing additional balancing registers are previously discussed in connection with
In some instances, the processor can optionally determines which register from the pipelines or input balancing registers to bypass so as to induce minimum performance impact to the DSP block, and to the system (step 520), e.g., the first and the last registers are usually kept. The processor may send processor instruction 503b to the DSP block to indicate which registers to bypass for step 510. The DSP block may then continue the operation (step 515), e.g., by receiving a new input (back to step 501).
In an alternative implementation, the DSP blocks can have a static configuration for fixed-point or floating-point operation. For example, the pipeline registers, and/or the balancing registers that are used or bypassed, can be pre-configured before an operation of the DSP block.
System 600 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, Remote Radio Head (RRH), or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 60 can be used to perform a variety of different logic functions. For example, PLD 60 can be configured as a processor or controller that works in cooperation with processor 601. PLD 60 may also be used as an arbiter for arbitrating access to shared resources in system 600. In yet another example, PLD 60 can be configured as an interface between processor 1801 and one of the other components in system 600. It should be noted that system 600 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.
Various technologies can be used to implement PLDs 60 as described above and incorporating this invention.
It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.
Claims
1-25. (canceled)
26. Cascaded circuitry operable in floating-point mode or in fixed-point mode, comprising:
- a first circuit, comprising: a first output port, a first input port, a first arithmetic circuit coupled to the first input port, and a plurality of pipeline registers disposed in connection with the first arithmetic circuit;
- a second circuit, comprising: a second output port, and a second input port; and
- a cascade register coupled between the first output port and the second input port, wherein the cascade register is selectively bypassed when the first circuit is operated in the fixed-point mode.
27. The cascaded circuitry of claim 26, wherein the first arithmetic circuit further comprises:
- a multiplier circuit coupled between the first input port and the first output port, wherein the multiplier circuit supports a floating-point multiplication operation.
28. The cascaded circuitry of claim 26, wherein the second circuit further comprises:
- a second arithmetic circuit coupled between the second input port and the second output port, wherein the second arithmetic circuit supports a floating-point operation.
29. The cascaded circuitry of claim 26, wherein the first circuit further comprises:
- a balancing register, wherein the balancing register and the cascade register are used when the first circuit and the second circuit are operated in the floating-point mode.
30. The cascaded circuitry of claim 26, wherein a pipeline register from the plurality of pipeline registers is selectively bypassed when the cascade register is used.
31. The cascaded circuitry of claim 26, wherein the second circuit further comprises:
- a second arithmetic circuit coupled between the second input port and the second output port; and
- a second plurality of pipeline registers disposed with the second arithmetic circuit.
32. The cascaded circuitry of claim 31, wherein the second circuit further comprises:
- a plurality of input balancing registers, wherein a last register of the second plurality of pipeline registers is connected to an input balancing register from the plurality of input balancing registers.
33. The cascaded circuitry of claim 26, further comprising:
- a third circuit having a third input port and a third output port, wherein the third input port is coupled to a fourth output port of the second circuit.
34. A method of operating cascaded circuitry that is operable in floating-point mode or in fixed-point mode, wherein the cascaded circuitry comprises first and second circuits that are coupled via a cascade register, wherein the first circuit comprises: the method comprising:
- a first output port,
- a first input port,
- a first arithmetic circuit coupled to the first input port, and
- a plurality of pipeline registers disposed in connection with the first arithmetic circuit,
- and wherein the second circuit comprises:
- a second output port, and
- a second input port,
- receiving a data input signal at the first input port;
- transmitting the data input signal via the first arithmetic circuit and the plurality of pipeline registers to the first output port;
- receiving, from a processor, a first command signal to operate the first circuit in floating-point mode and to use the cascade register; and
- in response to the first command signal: transmitting, via the cascade register, an interblock data signal from the first output port to the second input port.
35. The method of claim 34, further comprising:
- in response to the first command signal: selectively bypassing a pipeline register of the plurality of pipeline registers to compensate for a delay from the cascade register.
36. The method of claim 34, wherein the first circuit further comprises a plurality of input registers, the method further comprising:
- in response to the first command signal: selectively bypassing an input register of the plurality of input registers to compensate for a delay from the cascade register.
37. The method of claim 34, further comprising:
- receiving, from the processor, a second command signal to operate the first circuit in fixed-point mode and to bypass the cascade register; and
- in response to the second command signal: transmitting the interblock data signal from the first output port to the second input port without passing through the cascade register.
38. The method of claim 37, wherein:
- the processor sends the first command signal when the data input signal has a floating-point format; and
- the processor sends the second command signal when the data input signal has a fixed-point format.
39. An integrated circuit with a plurality of DSP blocks that are arranged in a cascade chain and that are each operable in fixed-point mode or in floating-point mode, comprising:
- a first DSP block of the plurality of DSP blocks, comprising: a first output, a first input, a first arithmetic operator circuit coupled to the first input, and pipeline registers disposed in connection with the first arithmetic operator circuit;
- a second DSP block of the plurality of DSP blocks, comprising: a second output, and a second input; and
- a cascade connection between the first output and the second input, comprising: a cascade register that is selectively bypassed when the first DSP block is operated in the fixed-point mode.
40. The integrated circuit of claim 39, wherein the first arithmetic operator circuit further comprises:
- a multiplier circuit that performs a floating-point multiplication operation when the first DSP block operates in the floating-point mode.
41. The integrated circuit of claim 39, wherein the first DSP block further comprises:
- a balancing register, wherein the balancing register and the cascade register are used when the first circuit and the second circuit are operated in the floating-point mode.
42. The integrated circuit of claim 39, wherein a pipeline register from the pipeline registers is selectively bypassed when the cascade register is used.
43. The integrated circuit of claim 39, wherein the second DSP block further comprises:
- a second arithmetic operator circuit that performs a floating-point operation when the second DSP block operates in the floating-point mode.
44. The integrated circuit of claim 43, wherein the second DSP block further comprises:
- second pipeline registers disposed with the second arithmetic operator circuit.
45. The integrated circuit of claim 44, wherein the second DSP block further comprises:
- input balancing registers, wherein a last register of the pipeline registers is connected to an input balancing register from the input balancing registers.
Type: Application
Filed: Jul 28, 2017
Publication Date: Nov 9, 2017
Applicant: Altera Corporation (San Jose, CA)
Inventor: Martin Langhammer (Salisbury)
Application Number: 15/662,304