Power Semiconductor Device with Charge Balance Design
A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode and a gate dielectric are formed in the gate trench. The gate dielectric electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.
The instant application relates to power semiconductor devices, and more particularly relates to drift region structures that enhance electrical performance of power semiconductor devices.
BACKGROUNDPower semiconductor devices, in particular field-effect controlled switching devices such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), have been used for various applications including but not limited to use as switches in power supplies and power converters, electric cars, air-conditioners, and even stereo systems. Particularly with regard to power devices capable of switching large currents and/or operating at higher voltages, low on-state resistance Ron, high breakdown voltages Ubd, and/or high robustness are often desired. A power MOSFET typically includes a drain region, a drift region adjoining the drain region, and a source region, each having a first conductivity type, and a body region arranged between the drift region and source region of a second conductivity type. A power IGBT has a similar construction as a power MOSFET, except that the first conductivity type drain region is replaced with a second conductivity type collector region, thus forming a bipolar junction transistor with a voltage controlled switch supplying the base current of the BJT.
One issue of particular concern in power switching applications is cosmic ray radiation. Cosmic ray radiation refers to unwanted particle bombardment from the exterior environment into the operational regions of the device. Although it is more prevalent in space environments, cosmic ray radiation can occur in terrestrial environments. The particle bombardments caused by cosmic ray radiation can set off a chain reaction of impact ionization, which causes unwanted current filamentation and can lead to irreversible device failure. Devices that operate with high electric field gradients, such as power switching devices, are most vulnerable to failure from cosmic ray radiation. For this reason, many power semiconductor switching applications require the device to be ruggedized against cosmic ray radiation. Mitigating high electric fields at critical locations within the power device enables robust device performance against harsh operation conditions such as cosmic ray radiation.
Techniques used to tailor the electric field profile and peak intensity of power switching devices to improve cosmic ray robustness include (i) increasing the wafer/drift region thickness; (ii) introducing a thicker graded/diffused base material profile; (iii) reducing the n-type drift region/intrinsic layer doping concentration; (iv) optimizing the field-stop (buffer) layer profile to reduce the peak electric field in the back side of the device; (V) using deeper p-type junctions at the surfaces to move the high electric field away from the electrodes; and (VI) thickening the gate trench oxide to alleviate the electric field strength at the trench bottom and the top side of the drift region. However, these approaches often lead to worse electrical performance trade-offs, e.g., poorer diode reverse recovery softness and higher on-state losses and hence worse Vce,sat (collector-emitter saturation voltage) and Eoff (turn-off loss).
SUMMARYA method of forming a vertical trenched gate transistor is disclosed. According to an embodiment, a semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode that is disposed in the gate trench is formed and a gate dielectric that is disposed in the gate trench is formed. The gate dialectic electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.
A method of forming a vertical trenched gate transistor in a semiconductor body having first and second vertically spaced apart surfaces, the vertical trenched gate transistor having an n-type source region extending form the first surface into the semiconductor body, a p-type body region disposed beneath and adjoining the source region, an n-type drift region disposed beneath and adjoining the body region, an n-type field stop region that is more highly doped than the drift region disposed beneath and adjoining the doped n-type drift region, a gate trench extending from the first surface through the source and body regions, and a gate electrode disposed in the gate trench and being configured to control a vertical current flowing between the first and second surfaces is disclosed. According to an embodiment of the method, a doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.
A vertical trenched gate transistor that is formed in a semiconductor body having first and second vertically spaced apart surfaces is disclosed. According to an embodiment, the vertical trenched gate transistor includes an n-type source region extending form the first surface into the semiconductor body, a p-type body region disposed beneath and adjoining the source region, an n-type drift region disposed beneath and adjoining the body region, and an n-type field stop region that is more highly doped than the drift region disposed beneath and adjoining the drift region. The vertical trenched gate transistor further includes a gate trench extending from the first surface through the source and body regions, and a gate electrode and a gate dielectric in the gate trench, the gate dielectric electrically insulating the gate electrode from adjacent semiconductor material. The gate electrode is configured to control a vertical current flowing between the first and second surfaces. The vertical trenched gate transistor further includes a doped superjunction region directly adjoining and disposed beneath the gate trench. The doped superjunction region includes first, second, and third doped pillars vertically extending from a bottom of the gate trench. The second pillar is laterally centered between the first and third pillars and forms a p-n junction with the first and third pillars. A distance between a bottom of the doped superjunction region and the field stop region is greater than 50% of a vertical thickness of the drift region. The vertical thickness of the drift region is measured between the body region and the field stop region.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Embodiments disclosed herein include a power semiconductor device. According to an embodiment, the power semiconductor device is an IGBT with a vertical trenched-gate electrode structure. The power semiconductor device includes a doped superjunction region that is disposed at the bottom of the gate trench and vertically extends into the drift region of the device. The doped superjunction region includes three doped pillars or stripes of alternating conductivity type (i.e., p-n-p or n-p-n). The doped superjunction region vertically extends no more than halfway into the drift region.
Various methods for forming the power semiconductor device are disclosed. Embodiments of these methods include providing a lightly doped first conductivity type first semiconductor layer. The doped superjunction region is formed in the first semiconductor layer. A variety of different techniques are disclosed for forming the doped superjunction region in the first semiconductor layer. One technique involves forming a trench in the first semiconductor layer, lining the sidewalls of the trench with first conductivity type semiconductor material, followed by filling the trench with second conductivity semiconductor material. Another technique involves performing masked ion implantations at the first surface of the first semiconductor layer to form doped wells that extend into the first semiconductor layer. These doped wells provide the first, second, and third pillars of the doped superjunction region. After the doped superjunction region is formed, a semiconductor second layer is epitaxially grown on the first semiconductor layer such that the second semiconductor layer covers the doped superjunction region. The gate trench is formed in the second semiconductor layer, with the bottom of the gate trench extending to the doped superjunction region. Active device regions, e.g., source, body, collector, emitter, etc., are formed in the second semiconductor layer.
The disclosed power semiconductor device and corresponding methods for forming the power semiconductor device have several notable advantages. For example, the structure of the doped superjunction region at the bottom of the gate trench avoids very high electric fields at the vicinity of bottom of the gate trench and thus advantageously improves the robustness of the device with respect to cosmic ray radiation. Moreover, the structure of the doped superjunction region beneficially improves the electrical performance of the device including switching losses and switching speed, while maintaining desirable breakdown voltage and on-resistance. Furthermore, the processes used to form the doped superjunction substantially less expensive, more reliable, and more controllable in comparison to prior art techniques for forming superjunction structures.
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Optionally, the insulated gate bipolar transistor 100 may include a first conductivity type field stop region 126 that is more highly doped than the drift region 112, and is interposed between the drift region 112 and the collector region 114. The field stop region 126 is configured to reduce the peak electric field at the collector side of the device and thereby improve the breakdown characteristics. In the case of a short circuit condition or a cosmic ray radiation event, a high electric field may arise in the vicinity of the field-stop region 126 due to high electron current density in this region. The field stop region 126 may have a doping concentration in a range between 5×1014 cm−3 and 1×1017 cm−3. In the depicted embodiment, the field stop region 126 is disposed only at the interface with the collector region 114. Alternatively, multiple field stop regions can be vertically throughout the lower half of the drift region 112.
As a further option, the insulated gate bipolar transistor 100 may include a first conductivity type injection region 127 that is more highly doped than the drift region 112, and is interposed between the drift region 112 and the body region 110. The injection region 127 enhances on-state conduction performance by injecting majority carriers into the drift region 112. The first conductivity type injection region 127 may have a doping concentration in a range between 5×1014cm−3and 1×1018 cm−3.
The insulated gate bipolar transistor 100 further includes a doped superjunction region 128. The doped superjunction region 128 is disposed within the drift region 112 beneath the gate trench 120. According to an embodiment, the doped superjunction region 128 directly adjoins the bottom of the gate trench 120. The doped superjunction region 128 extends from the bottom of the gate trench 120 in a vertical direction towards the second surface 106 of the semiconductor body 102. The doped superjunction region 128 contains at least two discrete regions with a different doping type or concentration than the surrounding drift region 112. For example, these various doped regions of the many each have a majority carrier concentration in the range of 5×1014 cm−3 and 1017 cm−3.
According to an embodiment, the doped superjunction region 128 includes first, second and third doped pillars 130, 132, 134. The first, second and third doped pillars 130, 132, 134 can in general be formed in any shape that is elongated in the vertical direction of the semiconductor body 102. According to one embodiment, the first, second and third doped pillars 130, 132, 134 are shapes as vertical stripes. Each of these stripes may have a substantially identical width. According to other embodiments, the stripes have differing widths. According to one embodiment, the first and third doped pillars 130, 134 have a second conductivity type majority carrier concentration and the second pillar 132 has a first conductivity type majority carrier concentration. Alternatively, the first and third doped pillars 130, 134 can have the first conductivity type majority carrier concentration and the second doped pillar 132 can have the second conductivity type majority carrier concentration. Either configuration is possible, regardless of the conductivity type of the drift region 112. At least the second doped pillar 132 may directly adjoin the bottom of the gate trench 120. Optionally, all three of the first, second, and third doped pillars 130, 132, 134 may directly adjoin the bottom of the gate trench 120.
According to an embodiment, the distance (D1) between a bottom of the doped superjunction region 128 and the field stop region 126 is greater than 50% of a vertical thickness (D2) of the drift region of the device. As used herein, the vertical thickness (D2) of the drift region is measured as the shortest distance between the body region 110 and the field stop region 126 in a direction perpendicular to the first and second surfaces 104, 106 of the semiconductor body 102. In embodiments that include the injection region 127, the vertical thickness (D2) of the drift region 112 encompasses this region as well. The vertical length of the doped superjunction region 128 can vary, depending on the desired electrical attributes of the device. For example, the distance between the bottom of the doped superjunction region 128 and the field stop region 126 can be greater than 70% of a vertical thickness of the drift region 112, and can be greater than 90% of a vertical thickness of the drift region 112. The vertical length of the doped superjunction region 128 can be in the range of 1 to 20 μm, and can be 5 or 10 μm in some embodiments. The top of the doped superjunction region 128 can be spaced apart from the injection region 127 by a portion of the drift region as depicted in
Selected method steps for forming various embodiments of the insulated gate bipolar transistor 100 of
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Two different embodiments for providing the first semiconductor layer 136 are depicted in
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The first and third doped wells 166, 172 have a majority carrier concentration corresponding to that of the first and third doped pillars 130, 134, i.e., in the range of 5×1014 cm−3 and 1017 cm−3.
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The inventors have discovered several advantages to the methods for forming the power semiconductor device in comparison to prior art techniques. These advantages include reduced processing cost and improved repeatability and yield in comparison to prior art techniques. Conventionally, superjunction structures for power semiconductor devices are formed from elongated p-type pillars in an n-type drift region 112 (or vice-versa). These elongated pillars are typically adjacent and laterally offset form the gate trench 120. Conventional techniques for forming these structures include a multilayer epitaxial growth process that involves the successive formation of doped regions in each epitaxial layer. Alternatively, these elongated pillars can be formed by a deep trench technique that involves the formation of high aspect ratio trenches. In either case, these processing steps are costly, time consuming and difficult to control. In particular, it is difficult to form these elongated pillars with a substantially homogenous doping concentrations. Charge imbalance in these structures can detrimentally impact the blocking capability of the device. By contrast, the presently disclosed methods used to form the doped superjunction region 128 involve cost-effective and highly controllable techniques, including ion implantation, trench etching, and epitaxial growth. Many fewer epitaxial cycles are required in comparison to a multilayer epitaxial growth process. Moreover, the doping concentration of the pillars in the doped superjunction region 128 is highly uniform as a result of these techniques. In some cases, process variation may produce first, second, and third doped pillars 130, 132, 134 having varying vertical heights, e.g., as depicted in
Furthermore, the inventors have discovered several improvements to the electrical characteristics of the power semiconductor device in comparison to the prior art devices. These advantages include a drift region structure that produces the combined benefits of shielding the bottom of the gate trench 120 from high electric fields while simultaneously introducing compensating charges in the drift region of the device that improve the switching performance of the device. Because the doped superjunction is located at the bottom of the gate trench 120 and includes a p-n junction, an electrically insulating space charge region arises that reduces the electric field strength at the bottom of the gate trench 120 and hardens the device against failure mechanisms associated with high electric field strength, including cosmic ray radiation.
In regards to switching performance, the doped superjunction utilizes the superjunction principle to lower turn-off losses, decrease delay time and decrease turn-off time with minimal impact on on-state resistance and breakdown voltage. Generally speaking, the switching performance of a power transistor depends upon how quickly the device can remove free carriers from the drift region during turn-off so that the device can enter a blocking state. Although one can improve the switching performance by decreasing the doping concentration of the drift region, this results in an unfavorable increase to the on-state resistance of the device and higher ohmic losses. The superjunction principle beneficially shifts this tradeoff by introducing compensating charges in the drift region. By introducing compensating charges in the drift region, a space charge region will arise more quickly when the device is turned off. As a result, improved turn-off losses, shorter delay time and shorter turn-off time can be realized without compromising on-state performance.
The inventors have found in particular that the currently disclosed design of the doped superjunction region 128, which does not extend more than 50% of a vertical thickness of the drift region 112, provides favorable electrical characteristics in comparison to conventional superjunction structures. Generally speaking, it is desirable to balance charges as much as possible in the drift region of the device for rapid switching time. To this end, the conventional superjunction structures for vertical power semiconductor devices vertically extend completely, or close to completely, to the bottom of the drift region. In this way, a complete charge balance or near complete charge balance throughout the device can be achieved. However, this design may lead to very fast switching speeds, which can be problematic in some cases. For example, in certain applications, fast switching times can lead to higher voltage overshoot and enable higher switching frequency which then induces a significant amount of electromagnetic interference (EMI). Some applications place an upper limit for dV/dt (i.e., switching speed) to 5 kV/μs because anything higher can lead to reliability issues. The device described herein exhibits significant reduction in the turn-off losses without much change in the on-state voltage. Meanwhile, the switching speed (dV/dt) only marginally increases in comparison to power semiconductor devices that do not include any superjunction structures. Put another way, the limited depth doped superjunction region 128 described herein nearly approximates the beneficial characteristics of conventional superjunction structures relating to switching efficiency while avoiding the drawbacks of conventional superjunction structures associated with ultra-fast switching times.
The present specification refers to a “first” and a “second” conductivity type of dopants that semiconductor portions are doped with. The first conductivity type may be n-type and the second conductivity type may be p-type (or vice versa). As is generally known, depending on the doping type or the polarity of the source and drain regions, MOSFETs may be n-channel or p-channel MOSFETs. For example, in an n-channel MOSFET, the source and the drain region are doped with n-type dopants, and the current direction is from the drain region to the source region. In a p-channel MOSFET, the source and the drain region are doped with p-type dopants, and the current direction is from the source region to the drain region. Insulated gate bipolar transistors can likewise be configured with a MOSFET portion that is an n-channel MOSFET or a p-channel MOSFET. Bipolar transistors can be p-n-p devices or n-p-n devices. As is to be clearly understood, within the context of the present specification, the doping types may be reversed. If a specific current path is described using directional language, this description is to be merely understood to indicate the path and not the polarity of the current flow, i.e. whether the transistor is a p-channel or an n-channel transistor.
The terms “wafer,” “substrate,” and “semiconductor substrate” used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood to include silicon, silicon-on-insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could as well be silicon-germanium, germanium, or gallium arsenide. According to embodiments of the present application, generally, silicon carbide (SiC) or gallium nitride (GaN) is a further example of the semiconductor substrate material.
The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die.
The term “vertical” used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.
Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper,” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having,” “containing,” “including,” “comprising,” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “an,” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Claims
1. A method of forming a vertical trenched gate transistor, comprising:
- forming a semiconductor body comprising first and second vertically spaced apart surfaces, a gate trench that vertically extends from the first surface of the semiconductor body towards the second surface, a gate electrode disposed in the gate trench, and a gate dielectric disposed in the gate trench and electrically insulating the gate electrode from adjacent semiconductor material; and
- forming a doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body, the doped superjunction region comprising first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another, the second pillar laterally centered between the first and third pillars and having an opposite conductivity type as the first and third pillars.
2. The method of claim 1, wherein forming the semiconductor body comprises:
- providing a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces; and
- epitaxially depositing a second semiconductor layer of the first conductivity type on the first semiconductor layer,
- wherein the doped superjunction is formed by applying semiconductor processing to the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer.
3. The method of claim 2, wherein forming the doped superjunction region comprises:
- forming a first trench in the first semiconductor layer vertically extending from the first surface of the first semiconductor layer;
- forming a first doped semiconductor region of the first conductivity type around a perimeter of the first trench such that the first doped semiconductor region lines a bottom and sidewalls of the first trench;
- forming a second doped semiconductor region of a second conductivity type that is opposite form the first conductivity type in the first trench between sections of the first doped semiconductor region that line the sidewalls of the first trench; and
- wherein the second doped semiconductor region provides the second doped pillar of the doped superjunction region, and
- wherein the sections of the first doped semiconductor region that line the sidewalls of the first trench provide the first and third doped pillars of the doped superjunction region.
4. The method of claim 3, wherein forming the first doped region comprises implanting dopant atoms into the perimeter of the first trench, the dopant atoms penetrating the bottom and sidewalls of the first trench thereby forming the first doped region within the first semiconductor layer.
5. The method of claim 3, wherein forming the first doped region around the perimeter of the first trench comprises epitaxially depositing a third semiconductor layer that lines the bottom and sidewalls of the first trench thereby forming the first doped region within the first trench, wherein a thickness of the third semiconductor layer is controlled such that a void remains in the first trench between sections of the third semiconductor layer.
6. The method of claim 3, wherein forming the second doped semiconductor region comprises, after forming the first doped region, epitaxially depositing a fourth semiconductor layer that completely fills the first trench.
7. The method of claim 2, wherein forming the doped superjunction region comprises:
- performing masked ion implantation at the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer thereby forming doped wells that vertically extend from the first surface of the first semiconductor layer into the first semiconductor layer.
8. The method of claim 7, wherein performing masked ion implantation comprises forming first and second doped wells that vertically extend from the first surface of the first semiconductor layer into the first semiconductor layer, the first doped well being wider than the second doped well, the second doped well being arranged in a lateral center of the first doped well such that portions of the first well are disposed on both lateral sides of the second well, wherein the second doped well provides the second doped pillar of the doped superjunction region, and wherein the portions of the first well that are disposed on both lateral sides of the second well provide the first and third doped pillars of the doped superjunction region.
9. The method of claim 7, wherein performing masked ion implantation comprises forming first, second, and third wells of approximately equal width that directly laterally adjoin one another, wherein the second well is laterally interposed between the first and third wells, wherein the second well provides the second doped pillar of the doped superjunction region, and wherein the first and third wells provide the first and third doped pillars of the doped superjunction region.
10. The method of claim 1, wherein forming the semiconductor body comprises providing a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces, wherein the gate trench is formed by etching semiconductor material from the first surface of the first semiconductor layer, wherein the doped superjunction region is formed by implanting first and second conductivity type dopants into a bottom of the gate trench.
11. The method of claim 1, wherein the second doped pillar has a second conductivity type that is opposite the first conductivity type, and wherein the first and third doped pillars have the first conductivity type and are more highly doped than the first semiconductor layer.
12. The method of claim 1, wherein the second doped pillar has the first conductivity type and is more highly doped than the first semiconductor layer, and wherein the first and third doped pillars have a second conductivity type that is opposite the first conductivity type.
13. The method of claim 1, further comprising:
- forming a second conductivity type body region vertically extending from the first surface semiconductor body, the second conductivity type being opposite the first conductivity type;
- forming a first conductivity type source region that is contained within the second conductivity type body region and directly adjoins the first surface of the semiconductor body and the gate trench;
- forming a second conductivity type collector region that extends from the second surface of the semiconductor body towards the gate trench; and
- forming a first conductivity type field stop region that is disposed between the collector region and the drift region,
- wherein a drift region of the device comprises first conductivity type semiconductor material disposed between the body region and the field stop region, and
- wherein a distance between a bottom of the doped superjunction region and the field stop region is greater than 50% of a vertical thickness of the drift region, the vertical thickness of the drift region being measured as a shortest distance between the body region and the field stop region.
14. The method of claim 13, wherein the distance between the bottom of the doped superjunction region and the field stop region is greater than 70% of a vertical thickness of the drift region.
15. The method of claim 1, wherein semiconductor body comprises silicon, and wherein providing the semiconductor body comprises at least one of:
- providing a bulk silicon substrate and epitaxially growing one or more semiconductor layers having the first conductivity type on the bulk silicon substrate;
- providing a FZ (floating zone) silicon wafer with an intrinsic doping of the first conductivity type;
- providing a MCZ (magnetic Czochralski) silicon wafer with an intrinsic doping of the first conductivity type.
16. The method of claim 1, wherein the semiconductor body comprises silicon-carbide.
17. A method of forming a vertical trenched gate transistor in a semiconductor body, the semiconductor body having first and second vertically spaced apart surfaces, the vertical trenched gate transistor comprising an n-type source region extending form the first surface into the semiconductor body, a p-type body region disposed beneath and adjoining the source region, an n-type drift region disposed beneath and adjoining the body region, an n-type field stop region that is more highly doped than the drift region disposed beneath and adjoining the doped n-type drift region, a gate trench extending from the first surface through the source and body regions, and a gate electrode disposed in the gate trench and being configured to control a vertical current flowing between the first and second surfaces, the method comprising:
- forming a doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body, the doped superjunction region comprising first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another, the second pillar laterally centered between the first and third pillars and having an opposite conductivity type as the first and third pillars.
18. The method of claim 17, wherein the semiconductor body is provided by:
- providing a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces; and
- epitaxially depositing a second semiconductor layer of the first conductivity type on the first semiconductor layer,
- wherein the doped superjunction is formed by applying semiconductor processing to the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer.
19. The method of claim 18, wherein forming the doped superjunction region comprises:
- forming a first trench that vertically extends beneath the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer;
- forming a first doped semiconductor region around a perimeter of the first trench such that the first doped semiconductor region lines a bottom and sidewalls of the first trench; and
- forming a second doped semiconductor region in the first trench between sections of the first doped semiconductor region that line the sidewalls of the first trench,
- wherein forming the first doped semiconductor region comprises at least one of:
- implanting n-type dopant atoms into the perimeter of the first trench; and
- epitaxially depositing a third n-type semiconductor layer that lines the bottom and sidewalls of the first trench.
20. The method of claim 18, wherein forming the doped superjunction region comprises:
- performing masked ion implantation at the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer thereby forming doped wells that vertically extend beneath the first surface of the first semiconductor layer.
21. The method of claim 18, wherein the semiconductor body is provided by a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces, wherein the gate trench is formed by etching semiconductor material from the first surface of the first semiconductor layer, wherein the doped superjunction region is formed by implanting first and second conductivity type dopants into a bottom of the gate trench.
22. A vertical trenched gate transistor being formed in a semiconductor body having first and second vertically spaced apart surfaces, the vertical trenched gate transistor comprising:
- an n-type source region extending form the first surface into the semiconductor body;
- a p-type body region disposed beneath and adjoining the source region;
- an n-type drift region disposed beneath the body region;
- an n-type field stop region that is more highly doped than the drift region disposed beneath and adjoining the drift region;
- a gate trench extending from the first surface through the source and body regions, and a gate electrode disposed in the gate trench and being configured to control a vertical current flowing between the first and second surfaces;
- a doped superjunction region directly adjoining and disposed beneath the gate trench, the doped superjunction region comprising first, second, and third doped pillars, the second pillar laterally centered between the first and third pillars and forming a p-n junction with the first and third pillars,
- wherein the first and third doped pillars each comprise a planar uppermost boundary that is substantially parallel to the first surface.
23. The vertical trenched gate transistor of claim 22, wherein the distance between a bottom of the doped superjunction region and the field stop region is greater than 70% of a vertical thickness of the drift region.
24. The vertical trenched gate transistor of claim 22, wherein the distance between a bottom of the doped superjunction region and the field stop region is greater than 90% of a vertical thickness of the drift region.
25. The vertical trenched gate transistor of claim 22, wherein the second doped pillar is an n-type region with a higher doping concentration than the drift region, and wherein the first and third pillars are p-type regions.
26. The vertical trenched gate transistor of claim 22, wherein the planar uppermost boundaries of the first and third pillars are vertically spaced apart from the body region by a portion of the drift region.
27. The vertical trenched gate transistor of claim 22, wherein the first, second and third doped pillars each comprise a lowermost boundary, the lowermost boundary of the first, second and third doped pillars each being vertically spaced apart from the field stop region by substantially the same distance.
Type: Application
Filed: May 23, 2016
Publication Date: Nov 23, 2017
Inventors: Alice Pei-Shan Hsieh (Unterhaching), Hans-Joachim Schulze (Taufkirchen)
Application Number: 15/161,666