Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190221481
    Abstract: A method for splitting a semiconductor wafer includes incorporating hydrogen atoms into at least a splitting region of a semiconductor wafer. The splitting region includes a concentration of nitrogen atoms higher than 1·1015 cm?3. The method further includes splitting the semiconductor wafer at the splitting region of the semiconductor wafer.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: Hans-Joachim Schulze, Martin Faccinelli, Johannes Georg Laven
  • Patent number: 10355116
    Abstract: A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Bina, Thomas Basler, Matteo Dainese, Hans-Joachim Schulze
  • Patent number: 10347723
    Abstract: A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; forming a first graphene material on a first side of the silicon carbide wafer; bonding the first side of the silicon carbide wafer with the first graphene material to the carrier wafer; and splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Guenther Ruhl, Gunther Lippert, Hans-Joachim Schulze, Thomas Zimmer
  • Patent number: 10340264
    Abstract: Semiconductor device is provided with a semiconductor body that includes a clamping structure including a first pn junction diode and a second pn junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the first pn junction diode is greater than 100 V, and a breakdown voltage of the second pn junction diode is greater than 10 V.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Stephan Voss, Roman Baburske, Thomas Basler, Thomas Kimmer, Hans-Joachim Schulze
  • Patent number: 10337117
    Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon during an extraction time period. The silicon ingot is doped with additional n-type dopant material during at least one sub-period of the extraction time period.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Nico Caspary, Hans-Joachim Schulze
  • Patent number: 10340335
    Abstract: A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Ploss, Hans-Joachim Schulze
  • Publication number: 20190198610
    Abstract: A channel stopper region extending from a first main surface into a component layer of a first conductivity type is formed in an edge region of a component region, the edge region being adjacent to a sawing track region. Afterward, a doped region extending from the first main surface into the component layer is formed in the component region. The channel stopper region is formed by a photolithographic method that is carried out before a first photolithographic method for introducing dopants into a section of the component region outside the channel stopper region.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Inventors: Elmar Falck, Franz-Josef Niedernostheide, Hans-Joachim Schulze
  • Publication number: 20190198621
    Abstract: A wide band gap semiconductor device includes a first doping region of a first conductivity type and a second doping region of a second conductivity type. A drift portion of the second doping region has a first average net doping concentration lower than 1e17 cm?3. A highly doped portion of the second doping region has a second average net doping concentration higher than 5e18 cm?3. A compensation portion of the second doping region located between the drift and highly doped portions extends from a first area with a net doping concentration higher than 1e16 cm?3 and lower than 1e17 cm?3 to a second area with a net doping concentration higher than 5e18 cm?3. A maximum gradient of the net doping concentration within at least a part of the compensation portion extending from the second area towards the first area for at least 100 nm is lower than 5e22 cm?4.
    Type: Application
    Filed: December 26, 2018
    Publication date: June 27, 2019
    Inventors: Josef Lutz, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20190198650
    Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Applicant: Infineon Technologies AG
    Inventors: Thomas WUEBBEN, Peter IRSIGLER, Hans-Joachim SCHULZE
  • Publication number: 20190198649
    Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region. Related methods of manufacture are also described.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze
  • Patent number: 10332973
    Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
  • Patent number: 10325809
    Abstract: A method for splitting a semiconductor wafer includes incorporating hydrogen atoms into at least a splitting region of a semiconductor wafer. The splitting region includes a concentration of nitrogen atoms higher than 1·1015 cm?3. The method further includes splitting the semiconductor wafer at the splitting region of the semiconductor wafer.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Martin Faccinelli, Johannes Georg Laven
  • Patent number: 10325996
    Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder, Helmut Strack, Frank Kahlmann, Gerhard Miller
  • Patent number: 10325804
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10317338
    Abstract: A method of determining the carbon content in a silicon sample may include: generating electrically active polyatomic complexes within the silicon sample. Each polyatomic complex may include at least one carbon atom. The method may further include: determining a quantity indicative of the content of the generated polyatomic complexes in the silicon sample, and determining the carbon content in the silicon sample from the determined quantity.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Naveen Goud Ganagona, Moriz Jelinek, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10319599
    Abstract: A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Helmut Oefner, Roland Rupp
  • Patent number: 10312258
    Abstract: A semiconductor device includes a semiconductor substrate with a first surface. The device further includes one or more semiconductor devices formed or the first surface in an active area. The device further includes a plurality of cavities in the semiconductor substrate beneath the first surface. The device further includes dielectric support structures between each of the cavities and spaced apart from the first surface. The dielectric support structures support a part of the semiconductor substrate between the active area and the cavities. The dielectric support structures include an oxide.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 4, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Laven, Matteo Dainese, Hans-Joachim Schulze
  • Publication number: 20190165090
    Abstract: A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 ?m to 60 ?m. The semiconductor body is annealed.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Oana Julia Spulber, Stephan Voss
  • Publication number: 20190157438
    Abstract: Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm?3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm?3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: Hans-Joachim Schulze, Philip Christoph Brandt, Andre Rainer Stegner
  • Publication number: 20190157395
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 23, 2019
    Inventors: Hans-Joachim Schulze, Roland Rupp