Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908694
    Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Michael Hell, Caspar Leendertz, Kristijan Luka Mletschnig, Hans-Joachim Schulze
  • Publication number: 20240055257
    Abstract: The disclosure relates to a method for manufacturing a contact on a SiC substrate, wherein the method includes: providing a crystalline SiC substrate; modifying a crystal structure in a surface area of the SiC substrate such that a carbon-enriched SiC portion is generated in the surface area; forming a contact layer on the SiC substrate by depositing a metallic contact material onto the surface area that includes the carbon-enriched SiC portion; and thermal annealing of at least a part of the carbon-enriched SiC portion of the SiC substrate and at least a part of the contact layer, such that a ternary metallic phase portion including at least the metallic contact material, silicon, and carbon is generated. Furthermore, SiC semiconductor devices are described, which include a crystalline SiC substrate and a contact layer including a ternary metallic phase portion directly in contact with the SiC substrate surface.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 15, 2024
    Inventors: Saurabh Roy, Werner Schustereder, Ravi Keshav Joshi, Hans-Joachim Schulze, Daria Krasnozhon
  • Publication number: 20240047457
    Abstract: A power semiconductor device includes at a first side and electrically isolated from first and second load terminals, first control electrodes for controlling a load current in first semiconductor channel structures formed in an active region at the first side, and at a second side and electrically isolated from the first and second load terminals, second control electrodes for controlling the load current in second semiconductor channel structures formed in the active region at the second side. At the second side and in a contiguous area of modified control (AMC) belonging to the active region and having a lateral extension of at least 30% of a thickness of a semiconductor body of the device, either no second control electrodes are provided or the second control electrodes are less effective in removing free charge carriers out of the power semiconductor device than the second control electrodes outside the AMC.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 8, 2024
    Inventors: Francisco Javier Santos Rodriguez, Roman Baburske, Hans-Joachim Schulze, Daniel Schlögl
  • Patent number: 11887894
    Abstract: A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Günter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11888024
    Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Ploss, Hans-Joachim Schulze
  • Publication number: 20240030032
    Abstract: The present disclosure generally relates to a method of manufacturing a contact on a silicon carbide semiconductor substrate wherein the method comprises providing a 4H—SiC semiconductor substrate, irradiating a surface area of the 4H—SiC semiconductor substrate with a first thermal annealing laser beam, thereby generating a phase separation of the surface area comprising at least a 3C—SiC layer, and depositing a contact material onto the 3C—SiC layer to form a contact layer on the semiconductor substrate. The disclosure further relates to a silicon carbide semiconductor device with an Ohmic contact comprising a 4H—SiC semiconductor substrate, a 3C—SiC layer, and a contact layer directly in contact with the 3C—SiC layer at the semiconductor surface.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Inventors: Saurabh ROY, Ravi Keshav JOSHI, Hans-Joachim SCHULZE, Bernhard GOLLER, Daria KRASNOZHON
  • Patent number: 11881406
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11881397
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20230411460
    Abstract: A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Saurabh Roy, Thomas Aichinger, Hans-Joachim Schulze
  • Patent number: 11848377
    Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: December 19, 2023
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Matteo Dainese, Elmar Falck, Franz-Josef Niedernostheide, Manfred Pfaffenlehner
  • Patent number: 11843045
    Abstract: A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: December 12, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Beninger-Bina, Thomas Basler, Matteo Dainese, Hans-Joachim Schulze
  • Publication number: 20230395394
    Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Patent number: 11837528
    Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 5, 2023
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20230361196
    Abstract: A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20230352531
    Abstract: A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 2, 2023
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Publication number: 20230343871
    Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; a trench formed in a first main surface of the semiconductor substrate; a field plate electrode in the trench and reaching a same level as the first main surface of the semiconductor substrate; an insulating material that separates the field plate electrode from the semiconductor substrate; and a material embedded in the field plate electrode. The field plate electrode is made of a different material than the material embedded in the field plate electrode. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. Additional device embodiments and methods of producing the semiconductor device are also described.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Inventors: Stefan Karner, Oliver Blank, Günter Denifl, Germano Galasso, Saurabh Roy, Hans-Joachim Schulze, Michael Stadtmueller
  • Patent number: 11791383
    Abstract: A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 17, 2023
    Assignee: Infineon Technologies AG
    Inventors: Saurabh Roy, Thomas Aichinger, Hans-Joachim Schulze
  • Publication number: 20230317797
    Abstract: A wide band gap semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. The semiconductor device further includes a first region of a first conductivity type adjoining at least partially the first surface, a drift region of a second conductivity type, a highly doped second region adjoining the second surface, and a buffer region of the second conductivity type arranged between the drift region and the highly doped second region. A vertical profile of a doping concentration of the buffer region includes at least one step in a first section and is increasing approximately exponentially toward the second surface in a second section. The first section is arranged between the second section and the highly doped second region.
    Type: Application
    Filed: March 22, 2023
    Publication date: October 5, 2023
    Inventors: Hans-Joachim Schulze, Rudolf Elpelt, Jens Peter Konrath, Konrad Schraml
  • Publication number: 20230317456
    Abstract: A method of manufacturing a semiconductor device in a semiconductor body having a first surface and a second surface is proposed. Semiconductor device elements are formed in the semiconductor body by processing the semiconductor body at the first surface. A wiring area is formed over the first surface of the semiconductor body. The semiconductor body is attached to a carrier via the wiring area. Thereafter, ions are implanted through the second surface into the semiconductor body. The ions are ions of a doping element, or ions, which induce doping by complex formation, or ions of a heavy metal. A surface region of the semiconductor body at the second surface is irradiated with a plurality of laser pulses. Thereafter, the carrier is removed from the semiconductor body.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 5, 2023
    Inventors: Moriz Jelinek, Hans-Joachim Schulze, Werner Schustereder, Daniel Schlögl, Francisco Javier Santos Rodriguez
  • Publication number: 20230299147
    Abstract: Disclosed is a method that includes: measuring at least one characteristic of a superjunction region of a SiC superjunction device, wherein the superjunction region is arranged in a semiconductor body and comprises a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type; and generating dopant like defects of one doping type in the superjunction region in a doping process. At least one parameter of the doping process is adjusted dependent on the at least one measured characteristic. The doping process includes an implantation process in which particles are implanted into the semiconductor body to form crystal defects in the semiconductor body in the superjunction region, and an annealing process in order to form the dopant like defects based on the crystal defects.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 21, 2023
    Inventors: Moriz JELINEK, Jens Peter KONRATH, Hans-Joachim SCHULZE, Andre Rainer STEGNER