Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211703
    Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: January 28, 2025
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Publication number: 20250022872
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Application
    Filed: September 26, 2024
    Publication date: January 16, 2025
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Publication number: 20250014902
    Abstract: A method of manufacturing a semiconductor device includes forming a doped region in a semiconductor body. Forming the doped region includes: introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by a first ion implantation process; thereafter, applying a first heat treatment to the semiconductor body; and thereafter, introducing second dopants through the first surface of the semiconductor body at the first vertical reference level by a second ion implantation process. An atomic number of the first dopants is equal to an atomic number of the second dopants. An ion implantation energy of the second ion implantation process differs by less than 20% from an ion implantation energy of the first ion implantation process. An ion implantation dose of the second ion implantation process differs by less than 20% from an ion implantation dose of the first ion implantation process.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 9, 2025
    Inventors: Axel König, Kristijan Luka Mletschnig, Andreas Vörckel, Caspar Leendertz, Werner Schustereder, Hans-Joachim Schulze
  • Publication number: 20240371772
    Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SIC) semiconductor body including a trench structure. The trench structure extends into the SiC semiconductor body at a first surface of the SiC semiconductor body. The trench structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the SiC semiconductor body. An interlayer dielectric structure is arranged on the trench structure. The interlayer dielectric structure includes at least one of an aluminum nitride layer, a silicon nitride layer, an aluminum oxide layer, or a boron nitride layer. The vertical power semiconductor device further includes a source or emitter electrode on the interlayer dielectric structure.
    Type: Application
    Filed: April 19, 2024
    Publication date: November 7, 2024
    Inventors: Saurabh Roy, Josef Schätz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 12136623
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Patent number: 12107141
    Abstract: A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Z1/2 defects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Z1/2 defects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 1, 2024
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack
  • Patent number: 12107128
    Abstract: A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: October 1, 2024
    Assignee: Infineon Technologies AG
    Inventors: Saurabh Roy, Thomas Aichinger, Hans-Joachim Schulze
  • Patent number: 12107130
    Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: October 1, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Patent number: 12057316
    Abstract: A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a <0001> direction or a <11-23> direction.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: August 6, 2024
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Paul Ellinghaus, Axel Koenig, Caspar Leendertz, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 12027591
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 5*102/cm2; attaching an acceptor layer at the graphene layer to form a wafer-stack, the acceptor layer comprising silicon carbide having a second defect density higher than the first defect density; forming an epitaxial silicon carbide layer; splitting the wafer-stack along a split plane in the silicon carbide substrate to form a device wafer comprising the graphene layer and a silicon carbide split layer at the graphene layer; and further processing the device wafer at the upper side.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: July 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Publication number: 20240154020
    Abstract: A semiconductor device includes a semiconductor body having first and second opposite surfaces along a vertical direction, and an active diode area. The active diode area includes: a p-doped anode region adjoining the first surface; an n-doped drift region between the anode region and the second surface; an n-doped cathode contact region adjoining the second surface; a p-doped injection region adjoining the second surface and the cathode contact region; and a p-doped auxiliary region between the drift region and the cathode contact region. The auxiliary region includes first and second sub-regions. In a top view, the first sub-region covers at least part of the injection region and the second sub-region covers at least part of the cathode contact region. In the top view, the auxiliary region includes a plurality of openings covering from 0.1% to an 20% of a surface area of the active diode area at the second surface.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 9, 2024
    Inventors: Benedikt Stoib, Hans-Joachim Schulze, Marten Müller, Daniel Schlögl, Moriz Jelinek, Holger Schulze
  • Publication number: 20240153759
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 9, 2024
    Inventors: Iris MODER, Bernhard GOLLER, Tobias Franz Wolfgang HOECHBAUER, Roland RUPP, Francisco Javier SANTOS RODRIGUEZ, Hans-Joachim SCHULZE
  • Publication number: 20240145588
    Abstract: A vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to each other along a vertical direction. The SiC semiconductor body includes at least one SiC semiconductor layer on a SiC semiconductor substrate. A pn junction is formed in the at least one SiC semiconductor layer. A first load electrode is arranged over the first surface. The vertical power semiconductor device further includes a plurality of first trenches extending into the SiC semiconductor substrate from the second surface. A second load electrode is arranged over the second surface. The second load electrode is electrically connected to the SiC semiconductor substrate via one or more sidewalls of the plurality of first trenches.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Thomas Ralf SIEMIENIEC, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20240145247
    Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Moriz JELINEK, Michael HELL, Caspar LEENDERTZ, Kristijan Luka MLETSCHNIG, Hans-Joachim SCHULZE
  • Patent number: 11949006
    Abstract: A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: April 2, 2024
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20240105832
    Abstract: A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 28, 2024
    Inventors: Thomas Ralf SIEMIENIEC, Hans-Joachim SCHULZE, Jens Peter KONRATH
  • Publication number: 20240090355
    Abstract: A piezoresistive transistor device includes a first transistor cell having a first piezoelectric material body and a first piezoresistive material body arranged in a stacked configuration. A first electrical resistance of the first piezoresistive material body is dependent upon a voltage applied across the first piezoelectric material body by way of a pressure applied by the first piezoelectric material body to the first piezoresistive material body. A second transistor cell includes a second piezoelectric material body and a second piezoresistive material body arranged in a stacked configuration. A second electrical resistance of the second piezoresistive material body is dependent upon a voltage applied across the second piezoelectric material body by way of a pressure applied by the second piezoelectric material body to the second piezoresistive material body.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 14, 2024
    Inventors: Saurabh Roy, Josef Anton Moser, Hans-Joachim Schulze
  • Patent number: 11929397
    Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Basler, Caspar Leendertz, Hans-Joachim Schulze
  • Patent number: 11908694
    Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Michael Hell, Caspar Leendertz, Kristijan Luka Mletschnig, Hans-Joachim Schulze
  • Publication number: 20240055257
    Abstract: The disclosure relates to a method for manufacturing a contact on a SiC substrate, wherein the method includes: providing a crystalline SiC substrate; modifying a crystal structure in a surface area of the SiC substrate such that a carbon-enriched SiC portion is generated in the surface area; forming a contact layer on the SiC substrate by depositing a metallic contact material onto the surface area that includes the carbon-enriched SiC portion; and thermal annealing of at least a part of the carbon-enriched SiC portion of the SiC substrate and at least a part of the contact layer, such that a ternary metallic phase portion including at least the metallic contact material, silicon, and carbon is generated. Furthermore, SiC semiconductor devices are described, which include a crystalline SiC substrate and a contact layer including a ternary metallic phase portion directly in contact with the SiC substrate surface.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 15, 2024
    Inventors: Saurabh Roy, Werner Schustereder, Ravi Keshav Joshi, Hans-Joachim Schulze, Daria Krasnozhon