Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149156
    Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Inventors: Thomas Basler, Caspar Leendertz, Hans-Joachim Schulze
  • Publication number: 20220149038
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Patent number: 11315892
    Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 26, 2022
    Inventors: Roman Roth, Frank Hille, Hans-Joachim Schulze
  • Patent number: 11309410
    Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
  • Patent number: 11302795
    Abstract: A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack
  • Patent number: 11282926
    Abstract: A semiconductor device includes a SiC body having a first semiconductor area of a first conductivity type and a second semiconductor area of a second conductivity type. The first semiconductor area is electrically contacted with a first surface of the SiC body and forms a pn junction with the second semiconductor area. The first and second semiconductor areas are arranged on one another in a vertical direction perpendicular to the first surface. The first semiconductor area has first and second dopant species. An average dopant concentration of the first dopant species in a first part of the first semiconductor area adjoining the first surface is greater than an average dopant concentration of the second dopant species. An average dopant concentration of the second dopant species in a second part of the first semiconductor area adjoining the second semiconductor area is greater than a dopant concentration of the first dopant species.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 22, 2022
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Wolfgang Bergner, Andre Rainer Stegner
  • Publication number: 20220085215
    Abstract: A power semiconductor diode includes a semiconductor body having first and second main surfaces opposite to each other along a vertical direction. A drift region of a second conductivity type is arranged between an anode region of a first conductivity type and the second main surface. A field stop region of the second conductivity type is arranged between the drift region and the second main surface. A dopant concentration profile of the field stop region along the vertical direction includes a maximum peak. An injection region of the first conductivity type is arranged between the field stop region and the second main surface, with a pn-junction between the injection and field stop regions. A cathode contact region of the second conductivity type is arranged between the field stop region and the second main surface. A first vertical distance between the pn-junction and the maximum peak ranges from 200 nm to 1500 nm.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 17, 2022
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Patent number: 11276754
    Abstract: An embodiment of a semiconductor device includes a silicon carbide semiconductor body including source and body regions of opposite conductivity types. A trench structure extends from a first surface into the silicon carbide semiconductor body along a vertical direction, and includes a gate electrode and a gate dielectric. A contact is electrically connected to the source region at the first surface. The source region includes a first source sub-region directly adjoining the contact at a source contact area of the first surface, a second source sub-region, and a third source sub-region. The second sub-region is arranged between the first and third sub-regions along the vertical direction. A doping concentration profile along the vertical direction of the source region includes a doping concentration minimum in the second sub-region and a doping concentration maximum in the third sub-region. Each of the second and third sub-regions overlaps with the source contact area.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Basler, Caspar Leendertz, Hans-Joachim Schulze
  • Patent number: 11276680
    Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Pedone, Hans-Joachim Schulze, Rolf Gerlach, Christian Kasztelan, Anton Mauder, Hubert Rothleitner, Wolfgang Scholz, Philipp Seng, Peter Tuerkes
  • Patent number: 11264464
    Abstract: A silicon carbide device includes a transistor cell with a front side doping region, a body region, and a drift region. The body region includes a first portion having a first average net doping concentration and a second portion having a second average net doping concentration. The first portion and the second portion have an extension of at least 50 nm in a vertical direction. The first average net doping concentration is at least two times the second average net doping concentration, and the first average net doping concentration is at least 1·1017 cm?3.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 1, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Thomas Basler, Andre Rainer Stegner
  • Patent number: 11264459
    Abstract: A power semiconductor device includes a semiconductor body having front and back sides. The semiconductor body includes drift, field stop and emitter adjustment regions each of a first conductivity type. The field stop region is arranged between the drift region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the drift region. The emitter adjustment region is arranged between the field stop region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the field stop region. The semiconductor body has a concentration of interstitial oxygen of at least 1E17 cm?3. The field stop region includes a region where the dopant concentration is higher than that in the drift region at least by a factor of three. At least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Moriz Jelinek, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Christian Philipp Sandow, Hans-Joachim Schulze
  • Patent number: 11251269
    Abstract: An embodiment of a semiconductor device includes a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction. A body region of a first conductivity type adjoins a sidewall of the trench gate structure and includes a first body sub-region adjoining the sidewall and a second body sub-region adjoining the sidewall. At least one profile of dopants of the first conductivity type along the vertical direction includes a first doping peak in the first body sub-region and a second doping peak in the second body sub-region. A doping concentration of the first doping peak is larger than a doping concentration of the second doping peak.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Ploss, Thomas Aichinger, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11250966
    Abstract: An apparatus for processing a plurality of semiconductor wafers, the apparatus including a spallation chamber, a neutron producing material mounted in the spallation chamber, a neutron moderator, and an irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Markus Bina, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20220042204
    Abstract: A method of manufacturing CZ silicon wafers is proposed. The method includes extracting a CZ silicon ingot over an extraction time period from a silicon melt including dopants being predominantly n-type. The method further includes introducing boron into the CZ silicon ingot over at least part of the extraction time period by controlling a boron supply to the silicon melt by a boron source. The method further includes determining a specific resistivity, a boron concentration, and a carbon concentration along a crystal axis of the CZ silicon ingot. The method further includes slicing the CZ silicon ingot or a section of the CZ silicon ingot into CZ silicon wafers. The method further includes determining at least two groups of the CZ silicon wafers depending on at least two of the specific resistivity, the boron concentration, and the carbon concentration.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 10, 2022
    Inventors: Hans-Joachim Schulze, Helmut Oefner
  • Patent number: 11242616
    Abstract: A silicon ingot has opposite ends. A specific resistance, measured along an axis between the opposite ends of the silicon ingot, has at least one point of inflection where a concavity of the specific resistance changes along the axis. According to another embodiment, a silicon ingot has a first ingot part and a second ingot part between opposite ends of the silicon ingot. The first ingot part has a different specific resistance than the second ingot part. In a region of the silicon ingot between the first and second ingot parts, the specific resistance has at least one point of inflection where a concavity of the specific resistance changes.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: February 8, 2022
    Assignee: Infineon Technologies AG
    Inventors: Nico Caspary, Hans-Joachim Schulze
  • Publication number: 20220037165
    Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 3, 2022
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Patent number: 11239384
    Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 1, 2022
    Assignee: INFINEON TECHNOLOGIESAG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20220029013
    Abstract: A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Anton Mauder, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20220013625
    Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body including a semiconductor substrate and a semiconductor layer on the semiconductor substrate. The semiconductor body has a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. A first part of the drift region is arranged in the semiconductor substrate. A second part of the drift region is arranged in the semiconductor layer. The vertical power semiconductor device further includes a field stop region arranged in the semiconductor substrate, wherein a doping concentration of the field stop region averaged along the vertical direction is larger than a doping concentration of the drift region averaged along the vertical direction.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 13, 2022
    Inventors: Hans-Joachim Schulze, Philipp Kohler-Redlich, Thomas Laska, Franz-Josef Niedernostheide, Vera van Treek
  • Patent number: 11195695
    Abstract: An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Michael Brugger, Hans-Joachim Schulze, Werner Schustereder, Peter Zupan