Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200251580
    Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Daniel Hölzl, Henning Kraack, Gabor Mezoesi, Hans-Joachim Schulze, Waqas Mumtaz Syed
  • Patent number: 10734507
    Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region. Related methods of manufacture are also described.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze
  • Publication number: 20200243340
    Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10724149
    Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
  • Patent number: 10724148
    Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon over an extraction time period. Boron is added to the molten silicon over at least part of the extraction time period.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Nico Caspary, Hans-Joachim Schulze
  • Publication number: 20200224326
    Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: Infineon Technologies AG
    Inventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
  • Publication number: 20200227518
    Abstract: A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.
    Type: Application
    Filed: March 24, 2020
    Publication date: July 16, 2020
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Patent number: 10714377
    Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Bernhard Goller, Iris Moder, Hans-Joachim Schulze
  • Patent number: 10707865
    Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 7, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Martina Seider-Schmidt, Hans-Joachim Schulze, Oliver Hellmund, Sebastian Schmidt, Peter Irsigler
  • Patent number: 10700168
    Abstract: A wide band gap semiconductor device includes a first doping region of a first conductivity type and a second doping region of a second conductivity type. A drift portion of the second doping region has a first average net doping concentration lower than 1e17 cm?3. A highly doped portion of the second doping region has a second average net doping concentration higher than 5e18 cm?3. A compensation portion of the second doping region located between the drift and highly doped portions extends from a first area with a net doping concentration higher than 1e16 cm?3 and lower than 1e17 cm?3 to a second area with a net doping concentration higher than 5e18 cm?3. A maximum gradient of the net doping concentration within at least a part of the compensation portion extending from the second area towards the first area for at least 100 nm is lower than 5e22 cm?4.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Josef Lutz, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20200203513
    Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Jens Peter KONRATH, Wolfgang BERGNER, Christian HECHT, Hans-Joachim SCHULZE, Andre Rainer STEGNER
  • Publication number: 20200194550
    Abstract: A power semiconductor device includes a semiconductor body having front and back sides. The semiconductor body includes drift, field stop and emitter adjustment regions each of a first conductivity type. The field stop region is arranged between the drift region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the drift region. The emitter adjustment region is arranged between the field stop region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the field stop region. The semiconductor body has a concentration of interstitial oxygen of at least 1E17 cm?3. The field stop region includes a region where the dopant concentration is higher than that in the drift region at least by a factor of three. At least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 18, 2020
    Inventors: Roman Baburske, Moriz Jelinek, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Christian Philipp Sandow, Hans-Joachim Schulze
  • Publication number: 20200185906
    Abstract: A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Johannes Georg Laven, Thomas Basler, Hans-Joachim Schulze
  • Patent number: 10679857
    Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10679978
    Abstract: A module is disclosed. In one example, the module includes a carrier, an at least partially thermally conductive and electrically insulating body mounted on only a part of a main surface of the carrier, an at least partially electrically conductive redistribution structure on the thermally conductive and electrically insulating body, an electronic chip mounted on the redistribution structure and above the thermally conductive and electrically insulating body, and an encapsulant encapsulating at least part of the carrier, at least part of the thermally conductive and electrically insulating body, at least part of the redistribution structure, and at least part of the electronic chip.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alexander Roth, Juergen Hoegerl, Hans-Joachim Schulze, Hans-Joerg Timme
  • Patent number: 10680089
    Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
  • Patent number: 10679855
    Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Publication number: 20200176580
    Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 4, 2020
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Patent number: 10672875
    Abstract: A method for forming a silicon carbide semiconductor device includes forming at least one graphene layer on a surface of a semiconductor substrate and forming a silicon carbide layer of the silicon carbide semiconductor device on the at least one graphene layer. At least one of forming the silicon carbide layer and forming the at least one graphene layer includes: heating the semiconductor substrate an inert gas atmosphere until a predefined temperature is reached.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Guenther Ruhl, Hans-Joachim Schulze
  • Patent number: 10670474
    Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christian Kegler, Johannes Georg Laven, Hans-Joachim Schulze, Guenther Ruhl, Joachim Mahler